projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| d626aeed BD |
1 | /* linux/arch/arm/mach-s3c6410/cpu.c |
| 2 | * | |
| 3 | * Copyright 2008 Simtec Electronics | |
| 4 | * Copyright 2008 Simtec Electronics | |
| 5 | * Ben Dooks <ben@simtec.co.uk> | |
| 6 | * http://armlinux.simtec.co.uk/ | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #include <linux/kernel.h> | |
| 14 | #include <linux/types.h> | |
| 15 | #include <linux/interrupt.h> | |
| 16 | #include <linux/list.h> | |
| 17 | #include <linux/timer.h> | |
| 18 | #include <linux/init.h> | |
| 19 | #include <linux/clk.h> | |
| 20 | #include <linux/io.h> | |
| 21 | #include <linux/sysdev.h> | |
| 22 | #include <linux/serial_core.h> | |
| 23 | #include <linux/platform_device.h> | |
| 24 | ||
| 25 | #include <asm/mach/arch.h> | |
| 26 | #include <asm/mach/map.h> | |
| 27 | #include <asm/mach/irq.h> | |
| 28 | ||
| 29 | #include <mach/hardware.h> | |
| 30 | #include <asm/irq.h> | |
| 31 | ||
| 32 | #include <plat/cpu-freq.h> | |
| 33 | #include <plat/regs-serial.h> | |
| 34 | ||
| 35 | #include <plat/cpu.h> | |
| 36 | #include <plat/devs.h> | |
| 37 | #include <plat/clock.h> | |
| 5cc7fd88 | 38 | #include <plat/sdhci.h> |
| cf18acf0 | 39 | #include <plat/s3c6400.h> |
| d626aeed BD |
40 | #include <plat/s3c6410.h> |
| 41 | ||
| 42 | /* Initial IO mappings */ | |
| 43 | ||
| 44 | static struct map_desc s3c6410_iodesc[] __initdata = { | |
| 45 | }; | |
| 46 | ||
| 47 | /* s3c6410_map_io | |
| 48 | * | |
| 49 | * register the standard cpu IO areas | |
| 50 | */ | |
| 51 | ||
| 52 | void __init s3c6410_map_io(void) | |
| 53 | { | |
| 54 | iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc)); | |
| 5cc7fd88 BD |
55 | |
| 56 | /* initialise device information early */ | |
| 57 | s3c6410_default_sdhci0(); | |
| a2205cd2 | 58 | s3c6410_default_sdhci1(); |
| d626aeed BD |
59 | } |
| 60 | ||
| 61 | void __init s3c6410_init_clocks(int xtal) | |
| 62 | { | |
| 39669f59 | 63 | printk(KERN_DEBUG "%s: initialising clocks\n", __func__); |
| d626aeed | 64 | s3c24xx_register_baseclocks(xtal); |
| 4b31d8b2 | 65 | s3c64xx_register_clocks(); |
| cf18acf0 BD |
66 | s3c6400_register_clocks(); |
| 67 | s3c6400_setup_clocks(); | |
| d626aeed BD |
68 | } |
| 69 | ||
| d9b79fb5 BD |
70 | void __init s3c6410_init_irq(void) |
| 71 | { | |
| 72 | /* VIC0 is missing IRQ7, VIC1 is fully populated. */ | |
| 73 | s3c64xx_init_irq(~0 & ~(1 << 7), ~0); | |
| 74 | } | |
| 75 | ||
| d626aeed BD |
76 | struct sysdev_class s3c6410_sysclass = { |
| 77 | .name = "s3c6410-core", | |
| 78 | }; | |
| 79 | ||
| 80 | static struct sys_device s3c6410_sysdev = { | |
| 81 | .cls = &s3c6410_sysclass, | |
| 82 | }; | |
| 83 | ||
| 84 | static int __init s3c6410_core_init(void) | |
| 85 | { | |
| 86 | return sysdev_class_register(&s3c6410_sysclass); | |
| 87 | } | |
| 88 | ||
| 89 | core_initcall(s3c6410_core_init); | |
| 90 | ||
| 91 | int __init s3c6410_init(void) | |
| 92 | { | |
| 93 | printk("S3C6410: Initialising architecture\n"); | |
| 94 | ||
| 95 | return sysdev_register(&s3c6410_sysdev); | |
| 96 | } |