Commit | Line | Data |
---|---|---|
e4d06e39 BD |
1 | /* linux/arch/arm/mach-s3c2443/clock.c |
2 | * | |
4bed36b2 | 3 | * Copyright (c) 2007, 2010 Simtec Electronics |
e4d06e39 BD |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C2443 Clock control support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/init.h> | |
af337f3e | 24 | |
e4d06e39 BD |
25 | #include <linux/module.h> |
26 | #include <linux/kernel.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/err.h> | |
edbaa603 | 30 | #include <linux/device.h> |
e4d06e39 BD |
31 | #include <linux/clk.h> |
32 | #include <linux/mutex.h> | |
e4d06e39 | 33 | #include <linux/serial_core.h> |
fced80c7 | 34 | #include <linux/io.h> |
e4d06e39 BD |
35 | |
36 | #include <asm/mach/map.h> | |
37 | ||
a09e64fb | 38 | #include <mach/hardware.h> |
e4d06e39 | 39 | |
a09e64fb | 40 | #include <mach/regs-s3c2443-clock.h> |
e4d06e39 | 41 | |
e425382e BD |
42 | #include <plat/cpu-freq.h> |
43 | ||
a2b7ba9c | 44 | #include <plat/s3c2443.h> |
d5120ae7 | 45 | #include <plat/clock.h> |
9aa753c4 | 46 | #include <plat/clock-clksrc.h> |
a2b7ba9c | 47 | #include <plat/cpu.h> |
e4d06e39 BD |
48 | |
49 | /* We currently have to assume that the system is running | |
50 | * from the XTPll input, and that all ***REFCLKs are being | |
51 | * fed from it, as we cannot read the state of OM[4] from | |
52 | * software. | |
53 | * | |
54 | * It would be possible for each board initialisation to | |
55 | * set the correct muxing at initialisation | |
56 | */ | |
57 | ||
e4d06e39 BD |
58 | /* clock selections */ |
59 | ||
ba7622a1 BD |
60 | /* armdiv |
61 | * | |
62 | * this clock is sourced from msysclk and can have a number of | |
63 | * divider values applied to it to then be fed into armclk. | |
aab08eeb HS |
64 | * The real clock definition is done in s3c2443-clock.c, |
65 | * only the armdiv divisor table must be defined here. | |
ba7622a1 BD |
66 | */ |
67 | ||
41f23a09 BD |
68 | static unsigned int armdiv[16] = { |
69 | [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1, | |
70 | [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2, | |
71 | [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3, | |
72 | [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4, | |
73 | [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6, | |
74 | [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8, | |
75 | [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12, | |
76 | [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, | |
77 | }; | |
78 | ||
e4d06e39 BD |
79 | /* hsspi |
80 | * | |
81 | * high-speed spi clock, sourced from esysclk | |
82 | */ | |
83 | ||
9aa753c4 BD |
84 | static struct clksrc_clk clk_hsspi = { |
85 | .clk = { | |
8b069b77 | 86 | .name = "hsspi-if", |
4bed36b2 | 87 | .parent = &clk_esysclk.clk, |
9aa753c4 BD |
88 | .ctrlbit = S3C2443_SCLKCON_HSSPICLK, |
89 | .enable = s3c2443_clkcon_enable_s, | |
b3bf41be | 90 | }, |
9aa753c4 | 91 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, |
e4d06e39 BD |
92 | }; |
93 | ||
e4d06e39 BD |
94 | |
95 | /* clk_hsmcc_div | |
96 | * | |
97 | * this clock is sourced from epll, and is fed through a divider, | |
98 | * to a mux controlled by sclkcon where either it or a extclk can | |
99 | * be fed to the hsmmc block | |
100 | */ | |
101 | ||
9aa753c4 BD |
102 | static struct clksrc_clk clk_hsmmc_div = { |
103 | .clk = { | |
104 | .name = "hsmmc-div", | |
e83626f2 | 105 | .devname = "s3c-sdhci.1", |
4bed36b2 | 106 | .parent = &clk_esysclk.clk, |
b3bf41be | 107 | }, |
9aa753c4 | 108 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, |
e4d06e39 BD |
109 | }; |
110 | ||
111 | static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) | |
112 | { | |
113 | unsigned long clksrc = __raw_readl(S3C2443_SCLKCON); | |
114 | ||
115 | clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT | | |
116 | S3C2443_SCLKCON_HSMMCCLK_EPLL); | |
117 | ||
118 | if (parent == &clk_epll) | |
119 | clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL; | |
120 | else if (parent == &clk_ext) | |
121 | clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT; | |
122 | else | |
123 | return -EINVAL; | |
124 | ||
125 | if (clk->usage > 0) { | |
126 | __raw_writel(clksrc, S3C2443_SCLKCON); | |
127 | } | |
128 | ||
129 | clk->parent = parent; | |
130 | return 0; | |
131 | } | |
132 | ||
133 | static int s3c2443_enable_hsmmc(struct clk *clk, int enable) | |
134 | { | |
135 | return s3c2443_setparent_hsmmc(clk, clk->parent); | |
136 | } | |
137 | ||
138 | static struct clk clk_hsmmc = { | |
139 | .name = "hsmmc-if", | |
e83626f2 | 140 | .devname = "s3c-sdhci.1", |
9aa753c4 | 141 | .parent = &clk_hsmmc_div.clk, |
e4d06e39 | 142 | .enable = s3c2443_enable_hsmmc, |
b3bf41be BD |
143 | .ops = &(struct clk_ops) { |
144 | .set_parent = s3c2443_setparent_hsmmc, | |
145 | }, | |
e4d06e39 BD |
146 | }; |
147 | ||
e4d06e39 BD |
148 | /* standard clock definitions */ |
149 | ||
4e04691b | 150 | static struct clk init_clocks_off[] = { |
e4d06e39 | 151 | { |
e4d06e39 | 152 | .name = "sdi", |
e4d06e39 BD |
153 | .parent = &clk_p, |
154 | .enable = s3c2443_clkcon_enable_p, | |
155 | .ctrlbit = S3C2443_PCLKCON_SDI, | |
e4d06e39 BD |
156 | }, { |
157 | .name = "spi", | |
e83626f2 | 158 | .devname = "s3c2410-spi.0", |
e4d06e39 BD |
159 | .parent = &clk_p, |
160 | .enable = s3c2443_clkcon_enable_p, | |
161 | .ctrlbit = S3C2443_PCLKCON_SPI0, | |
162 | }, { | |
163 | .name = "spi", | |
e83626f2 | 164 | .devname = "s3c2410-spi.1", |
e4d06e39 BD |
165 | .parent = &clk_p, |
166 | .enable = s3c2443_clkcon_enable_p, | |
167 | .ctrlbit = S3C2443_PCLKCON_SPI1, | |
168 | } | |
169 | }; | |
170 | ||
e4d06e39 BD |
171 | /* clocks to add straight away */ |
172 | ||
9aa753c4 | 173 | static struct clksrc_clk *clksrcs[] __initdata = { |
e4d06e39 BD |
174 | &clk_hsspi, |
175 | &clk_hsmmc_div, | |
9aa753c4 BD |
176 | }; |
177 | ||
178 | static struct clk *clks[] __initdata = { | |
e4d06e39 BD |
179 | &clk_hsmmc, |
180 | }; | |
181 | ||
d25a8f94 HS |
182 | static struct clk_lookup s3c2443_clk_lookup[] = { |
183 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc), | |
5c2f2917 | 184 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk), |
d25a8f94 HS |
185 | }; |
186 | ||
e425382e BD |
187 | void __init s3c2443_init_clocks(int xtal) |
188 | { | |
e425382e | 189 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); |
e425382e BD |
190 | int ptr; |
191 | ||
af337f3e BD |
192 | clk_epll.rate = s3c2443_get_epll(epllcon, xtal); |
193 | clk_epll.parent = &clk_epllref.clk; | |
194 | ||
33ccedfd | 195 | s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, |
d9a3bfbd HS |
196 | armdiv, ARRAY_SIZE(armdiv), |
197 | S3C2443_CLKDIV0_ARMDIV_MASK); | |
e425382e | 198 | |
4e04691b | 199 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
e4d06e39 | 200 | |
9aa753c4 BD |
201 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) |
202 | s3c_register_clksrc(clksrcs[ptr], 1); | |
203 | ||
e4d06e39 | 204 | /* We must be careful disabling the clocks we are not intending to |
3a4fa0a2 | 205 | * be using at boot time, as subsystems such as the LCD which do |
e4d06e39 BD |
206 | * their own DMA requests to the bus can cause the system to lockup |
207 | * if they where in the middle of requesting bus access. | |
208 | * | |
209 | * Disabling the LCD clock if the LCD is active is very dangerous, | |
210 | * and therefore the bootloader should be careful to not enable | |
211 | * the LCD clock if it is not needed. | |
212 | */ | |
213 | ||
214 | /* install (and disable) the clocks we do not need immediately */ | |
215 | ||
4e04691b BD |
216 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
217 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
d25a8f94 | 218 | clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup)); |
9d325f23 BD |
219 | |
220 | s3c_pwmclk_init(); | |
e4d06e39 | 221 | } |