[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / arch / arm / mach-s3c2443 / clock.c

/* linux/arch/arm/mach-s3c2443/clock.c
 *
 * Copyright (c) 2007, 2010 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2443 Clock control support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/sysdev.h>
#include <linux/clk.h>
#include <linux/mutex.h>
#include <linux/serial_core.h>
#include <linux/io.h>

#include <asm/mach/map.h>

#include <mach/hardware.h>

#include <mach/regs-s3c2443-clock.h>

#include <plat/cpu-freq.h>

#include <plat/s3c2443.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
#include <plat/cpu.h>

/* We currently have to assume that the system is running
 * from the XTPll input, and that all ***REFCLKs are being
 * fed from it, as we cannot read the state of OM[4] from
 * software.
 *
 * It would be possible for each board initialisation to
 * set the correct muxing at initialisation
*/

/* clock selections */

static struct clk clk_i2s_ext = {
	.name		= "i2s-ext",
	.id		= -1,
};

/* armdiv
 *
 * this clock is sourced from msysclk and can have a number of
 * divider values applied to it to then be fed into armclk.
*/

/* armdiv divisor table */

static unsigned int armdiv[16] = {
	[S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 1,
	[S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 2,
	[S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 3,
	[S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 4,
	[S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 6,
	[S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 8,
	[S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 12,
	[S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 16,
};

static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
{
	clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;

	return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
}

static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
					      unsigned long rate)
{
	unsigned long parent = clk_get_rate(clk->parent);
	unsigned long calc;
	unsigned best = 256; /* bigger than any value */
	unsigned div;
	int ptr;

	for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
		div = armdiv[ptr];
		calc = parent / div;
		if (calc <= rate && div < best)
			best = div;
	}

	return parent / best;
}

static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
{
	unsigned long parent = clk_get_rate(clk->parent);
	unsigned long calc;
	unsigned div;
	unsigned best = 256; /* bigger than any value */
	int ptr;
	int val = -1;

	for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
		div = armdiv[ptr];
		calc = parent / div;
		if (calc <= rate && div < best) {
			best = div;
			val = ptr;
		}
	}

	if (val >= 0) {
		unsigned long clkcon0;

		clkcon0 = __raw_readl(S3C2443_CLKDIV0);
		clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
		clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
		__raw_writel(clkcon0, S3C2443_CLKDIV0);
	}

	return (val == -1) ? -EINVAL : 0;
}

static struct clk clk_armdiv = {
	.name		= "armdiv",
	.id		= -1,
	.parent		= &clk_msysclk.clk,
	.ops		= &(struct clk_ops) {
		.round_rate = s3c2443_armclk_roundrate,
		.set_rate = s3c2443_armclk_setrate,
	},
};

/* armclk
 *
 * this is the clock fed into the ARM core itself, from armdiv or from hclk.
 */

static struct clk *clk_arm_sources[] = {
	[0] = &clk_armdiv,
	[1] = &clk_h,
};

static struct clksrc_clk clk_arm = {
	.clk	= {
		.name		= "armclk",
		.id		= -1,
	},
	.sources = &(struct clksrc_sources) {
		.sources = clk_arm_sources,
		.nr_sources = ARRAY_SIZE(clk_arm_sources),
	},
	.reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
};

/* hsspi
 *
 * high-speed spi clock, sourced from esysclk
*/

static struct clksrc_clk clk_hsspi = {
	.clk	= {
		.name		= "hsspi",
		.id		= -1,
		.parent		= &clk_esysclk.clk,
		.ctrlbit	= S3C2443_SCLKCON_HSSPICLK,
		.enable		= s3c2443_clkcon_enable_s,
	},
	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
};


/* clk_hsmcc_div
 *
 * this clock is sourced from epll, and is fed through a divider,
 * to a mux controlled by sclkcon where either it or a extclk can
 * be fed to the hsmmc block
*/

static struct clksrc_clk clk_hsmmc_div = {
	.clk	= {
		.name		= "hsmmc-div",
		.id		= -1,
		.parent		= &clk_esysclk.clk,
	},
	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
};

static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
{
	unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);

	clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
		    S3C2443_SCLKCON_HSMMCCLK_EPLL);

	if (parent == &clk_epll)
		clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
	else if (parent == &clk_ext)
		clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
	else
		return -EINVAL;

	if (clk->usage > 0) {
		__raw_writel(clksrc, S3C2443_SCLKCON);
	}

	clk->parent = parent;
	return 0;
}

static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
{
	return s3c2443_setparent_hsmmc(clk, clk->parent);
}

static struct clk clk_hsmmc = {
	.name		= "hsmmc-if",
	.id		= -1,
	.parent		= &clk_hsmmc_div.clk,
	.enable		= s3c2443_enable_hsmmc,
	.ops		= &(struct clk_ops) {
		.set_parent	= s3c2443_setparent_hsmmc,
	},
};

/* i2s_eplldiv
 *
 * This clock is the output from the I2S divisor of ESYSCLK, and is separate
 * from the mux that comes after it (cannot merge into one single clock)
*/

static struct clksrc_clk clk_i2s_eplldiv = {
	.clk	= {
		.name		= "i2s-eplldiv",
		.id		= -1,
		.parent		= &clk_esysclk.clk,
	},
	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
};

/* i2s-ref
 *
 * i2s bus reference clock, selectable from external, esysclk or epllref
 *
 * Note, this used to be two clocks, but was compressed into one.
*/

struct clk *clk_i2s_srclist[] = {
	[0] = &clk_i2s_eplldiv.clk,
	[1] = &clk_i2s_ext,
	[2] = &clk_epllref.clk,
	[3] = &clk_epllref.clk,
};

static struct clksrc_clk clk_i2s = {
	.clk	= {
		.name		= "i2s-if",
		.id		= -1,
		.ctrlbit	= S3C2443_SCLKCON_I2SCLK,
		.enable		= s3c2443_clkcon_enable_s,

	},
	.sources = &(struct clksrc_sources) {
		.sources = clk_i2s_srclist,
		.nr_sources = ARRAY_SIZE(clk_i2s_srclist),
	},
	.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
};

/* standard clock definitions */

static struct clk init_clocks_off[] = {
	{
		.name		= "sdi",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_SDI,
	}, {
		.name		= "iis",
		.id		= -1,
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_IIS,
	}, {
		.name		= "spi",
		.id		= 0,
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_SPI0,
	}, {
		.name		= "spi",
		.id		= 1,
		.parent		= &clk_p,
		.enable		= s3c2443_clkcon_enable_p,
		.ctrlbit	= S3C2443_PCLKCON_SPI1,
	}
};

static struct clk init_clocks[] = {
};

/* clocks to add straight away */

static struct clksrc_clk *clksrcs[] __initdata = {
	&clk_arm,
	&clk_i2s_eplldiv,
	&clk_i2s,
	&clk_hsspi,
	&clk_hsmmc_div,
};

static struct clk *clks[] __initdata = {
	&clk_hsmmc,
	&clk_armdiv,
};

void __init_or_cpufreq s3c2443_setup_clocks(void)
{
	s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
}

void __init s3c2443_init_clocks(int xtal)
{
	unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
	int ptr;

	clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
	clk_epll.parent = &clk_epllref.clk;

	s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);

	s3c2443_setup_clocks();

	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_register_clksrc(clksrcs[ptr], 1);

	/* register clocks from clock array */

	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));

	/* We must be careful disabling the clocks we are not intending to
	 * be using at boot time, as subsystems such as the LCD which do
	 * their own DMA requests to the bus can cause the system to lockup
	 * if they where in the middle of requesting bus access.
	 *
	 * Disabling the LCD clock if the LCD is active is very dangerous,
	 * and therefore the bootloader should be careful to not enable
	 * the LCD clock if it is not needed.
	*/

	/* install (and disable) the clocks we do not need immediately */

	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c_pwmclk_init();
}
Commit	Line	Data
e4d06e39 BD	1	/* linux/arch/arm/mach-s3c2443/clock.c
e4d06e39 BD	2	*
4bed36b2	3	* Copyright (c) 2007, 2010 Simtec Electronics
e4d06e39 BD	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* S3C2443 Clock control support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22
	23	#include <linux/init.h>
af337f3e	24
e4d06e39 BD	25	#include <linux/module.h>
	26	#include <linux/kernel.h>
	27	#include <linux/list.h>
	28	#include <linux/errno.h>
	29	#include <linux/err.h>
	30	#include <linux/sysdev.h>
	31	#include <linux/clk.h>
	32	#include <linux/mutex.h>
e4d06e39	33	#include <linux/serial_core.h>
fced80c7	34	#include <linux/io.h>
e4d06e39 BD	35
	36	#include <asm/mach/map.h>
	37
a09e64fb	38	#include <mach/hardware.h>
e4d06e39	39
a09e64fb	40	#include <mach/regs-s3c2443-clock.h>
e4d06e39	41
e425382e BD	42	#include <plat/cpu-freq.h>
e425382e BD	43
a2b7ba9c	44	#include <plat/s3c2443.h>
d5120ae7	45	#include <plat/clock.h>
9aa753c4	46	#include <plat/clock-clksrc.h>
a2b7ba9c	47	#include <plat/cpu.h>
e4d06e39 BD	48
	49	/* We currently have to assume that the system is running
	50	* from the XTPll input, and that all ***REFCLKs are being
	51	* fed from it, as we cannot read the state of OM[4] from
	52	* software.
	53	*
	54	* It would be possible for each board initialisation to
	55	* set the correct muxing at initialisation
	56	*/
	57
e4d06e39 BD	58	/* clock selections */
e4d06e39 BD	59
e4d06e39 BD	60	static struct clk clk_i2s_ext = {
	61	.name = "i2s-ext",
	62	.id = -1,
	63	};
	64
ba7622a1 BD	65	/* armdiv
	66	*
	67	* this clock is sourced from msysclk and can have a number of
	68	* divider values applied to it to then be fed into armclk.
	69	*/
	70
41f23a09 BD	71	/* armdiv divisor table */
	72
	73	static unsigned int armdiv[16] = {
	74	[S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
	75	[S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
	76	[S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
	77	[S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
	78	[S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
	79	[S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
	80	[S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
	81	[S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
	82	};
	83
	84	static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
	85	{
	86	clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
	87
	88	return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
	89	}
	90
	91	static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
	92	unsigned long rate)
	93	{
	94	unsigned long parent = clk_get_rate(clk->parent);
	95	unsigned long calc;
	96	unsigned best = 256; /* bigger than any value */
	97	unsigned div;
	98	int ptr;
	99
	100	for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
	101	div = armdiv[ptr];
	102	calc = parent / div;
	103	if (calc <= rate && div < best)
	104	best = div;
	105	}
	106
	107	return parent / best;
	108	}
	109
	110	static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
	111	{
	112	unsigned long parent = clk_get_rate(clk->parent);
	113	unsigned long calc;
	114	unsigned div;
	115	unsigned best = 256; /* bigger than any value */
	116	int ptr;
	117	int val = -1;
	118
	119	for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
	120	div = armdiv[ptr];
	121	calc = parent / div;
	122	if (calc <= rate && div < best) {
	123	best = div;
	124	val = ptr;
	125	}
	126	}
	127
	128	if (val >= 0) {
	129	unsigned long clkcon0;
	130
	131	clkcon0 = __raw_readl(S3C2443_CLKDIV0);
	132	clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
	133	clkcon0 \|= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
	134	__raw_writel(clkcon0, S3C2443_CLKDIV0);
135	}
136
137	return (val == -1) ? -EINVAL : 0;
138	}
139
ba7622a1 BD	140	static struct clk clk_armdiv = {
	141	.name = "armdiv",
	142	.id = -1,
4bed36b2	143	.parent = &clk_msysclk.clk,
41f23a09 BD	144	.ops = &(struct clk_ops) {
	145	.round_rate = s3c2443_armclk_roundrate,
	146	.set_rate = s3c2443_armclk_setrate,
	147	},
ba7622a1 BD	148	};
	149
	150	/* armclk
	151	*
4bed36b2	152	* this is the clock fed into the ARM core itself, from armdiv or from hclk.
ba7622a1 BD	153	*/
ba7622a1 BD	154
4bed36b2 BD	155	static struct clk *clk_arm_sources[] = {
	156	[0] = &clk_armdiv,
	157	[1] = &clk_h,
	158	};
ba7622a1	159
4bed36b2 BD	160	static struct clksrc_clk clk_arm = {
	161	.clk = {
	162	.name = "armclk",
	163	.id = -1,
b3bf41be	164	},
4bed36b2 BD	165	.sources = &(struct clksrc_sources) {
	166	.sources = clk_arm_sources,
	167	.nr_sources = ARRAY_SIZE(clk_arm_sources),
	168	},
	169	.reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
ba7622a1	170	};
e4d06e39	171
e4d06e39 BD	172	/* hsspi
	173	*
	174	* high-speed spi clock, sourced from esysclk
	175	*/
	176
9aa753c4 BD	177	static struct clksrc_clk clk_hsspi = {
	178	.clk = {
	179	.name = "hsspi",
	180	.id = -1,
4bed36b2	181	.parent = &clk_esysclk.clk,
9aa753c4 BD	182	.ctrlbit = S3C2443_SCLKCON_HSSPICLK,
9aa753c4 BD	183	.enable = s3c2443_clkcon_enable_s,
b3bf41be	184	},
9aa753c4	185	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
e4d06e39 BD	186	};
e4d06e39 BD	187
e4d06e39 BD	188
	189	/* clk_hsmcc_div
	190	*
	191	* this clock is sourced from epll, and is fed through a divider,
	192	* to a mux controlled by sclkcon where either it or a extclk can
	193	* be fed to the hsmmc block
	194	*/
	195
9aa753c4 BD	196	static struct clksrc_clk clk_hsmmc_div = {
	197	.clk = {
	198	.name = "hsmmc-div",
	199	.id = -1,
4bed36b2	200	.parent = &clk_esysclk.clk,
b3bf41be	201	},
9aa753c4	202	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
e4d06e39 BD	203	};
	204
	205	static int s3c2443_setparent_hsmmc(struct clk clk, struct clk parent)
	206	{
	207	unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
	208
	209	clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT \|
	210	S3C2443_SCLKCON_HSMMCCLK_EPLL);
	211
	212	if (parent == &clk_epll)
	213	clksrc \|= S3C2443_SCLKCON_HSMMCCLK_EPLL;
	214	else if (parent == &clk_ext)
	215	clksrc \|= S3C2443_SCLKCON_HSMMCCLK_EXT;
	216	else
	217	return -EINVAL;
	218
	219	if (clk->usage > 0) {
	220	__raw_writel(clksrc, S3C2443_SCLKCON);
	221	}
	222
	223	clk->parent = parent;
	224	return 0;
	225	}
	226
	227	static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
	228	{
	229	return s3c2443_setparent_hsmmc(clk, clk->parent);
	230	}
	231
	232	static struct clk clk_hsmmc = {
	233	.name = "hsmmc-if",
	234	.id = -1,
9aa753c4	235	.parent = &clk_hsmmc_div.clk,
e4d06e39	236	.enable = s3c2443_enable_hsmmc,
b3bf41be BD	237	.ops = &(struct clk_ops) {
	238	.set_parent = s3c2443_setparent_hsmmc,
	239	},
e4d06e39 BD	240	};
	241
	242	/* i2s_eplldiv
	243	*
a8cd4561	244	* This clock is the output from the I2S divisor of ESYSCLK, and is separate
9aa753c4	245	* from the mux that comes after it (cannot merge into one single clock)
e4d06e39 BD	246	*/
e4d06e39 BD	247
9aa753c4 BD	248	static struct clksrc_clk clk_i2s_eplldiv = {
	249	.clk = {
	250	.name = "i2s-eplldiv",
	251	.id = -1,
4bed36b2	252	.parent = &clk_esysclk.clk,
b3bf41be	253	},
9aa753c4	254	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
e4d06e39 BD	255	};
	256
	257	/* i2s-ref
	258	*
	259	* i2s bus reference clock, selectable from external, esysclk or epllref
9aa753c4 BD	260	*
9aa753c4 BD	261	* Note, this used to be two clocks, but was compressed into one.
e4d06e39 BD	262	*/
e4d06e39 BD	263
9aa753c4 BD	264	struct clk *clk_i2s_srclist[] = {
	265	[0] = &clk_i2s_eplldiv.clk,
	266	[1] = &clk_i2s_ext,
	267	[2] = &clk_epllref.clk,
	268	[3] = &clk_epllref.clk,
	269	};
e4d06e39	270
9aa753c4 BD	271	static struct clksrc_clk clk_i2s = {
	272	.clk = {
	273	.name = "i2s-if",
	274	.id = -1,
	275	.ctrlbit = S3C2443_SCLKCON_I2SCLK,
	276	.enable = s3c2443_clkcon_enable_s,
e4d06e39	277
b3bf41be	278	},
9aa753c4 BD	279	.sources = &(struct clksrc_sources) {
	280	.sources = clk_i2s_srclist,
	281	.nr_sources = ARRAY_SIZE(clk_i2s_srclist),
	282	},
	283	.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
e4d06e39 BD	284	};
e4d06e39 BD	285
e4d06e39 BD	286	/* standard clock definitions */
e4d06e39 BD	287
4e04691b	288	static struct clk init_clocks_off[] = {
e4d06e39	289	{
e4d06e39 BD	290	.name = "sdi",
	291	.id = -1,
	292	.parent = &clk_p,
	293	.enable = s3c2443_clkcon_enable_p,
	294	.ctrlbit = S3C2443_PCLKCON_SDI,
e4d06e39 BD	295	}, {
	296	.name = "iis",
	297	.id = -1,
	298	.parent = &clk_p,
	299	.enable = s3c2443_clkcon_enable_p,
	300	.ctrlbit = S3C2443_PCLKCON_IIS,
	301	}, {
	302	.name = "spi",
	303	.id = 0,
	304	.parent = &clk_p,
	305	.enable = s3c2443_clkcon_enable_p,
	306	.ctrlbit = S3C2443_PCLKCON_SPI0,
	307	}, {
	308	.name = "spi",
	309	.id = 1,
	310	.parent = &clk_p,
	311	.enable = s3c2443_clkcon_enable_p,
	312	.ctrlbit = S3C2443_PCLKCON_SPI1,
	313	}
	314	};
	315
	316	static struct clk init_clocks[] = {
e4d06e39 BD	317	};
e4d06e39 BD	318
e4d06e39 BD	319	/* clocks to add straight away */
e4d06e39 BD	320
9aa753c4	321	static struct clksrc_clk *clksrcs[] __initdata = {
4bed36b2	322	&clk_arm,
e4d06e39 BD	323	&clk_i2s_eplldiv,
	324	&clk_i2s,
	325	&clk_hsspi,
	326	&clk_hsmmc_div,
9aa753c4 BD	327	};
	328
	329	static struct clk *clks[] __initdata = {
e4d06e39	330	&clk_hsmmc,
ba7622a1	331	&clk_armdiv,
e4d06e39 BD	332	};
e4d06e39 BD	333
e425382e	334	void __init_or_cpufreq s3c2443_setup_clocks(void)
e4d06e39	335	{
af337f3e	336	s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
e425382e BD	337	}
	338
	339	void __init s3c2443_init_clocks(int xtal)
	340	{
e425382e	341	unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
e425382e BD	342	int ptr;
e425382e BD	343
af337f3e BD	344	clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
	345	clk_epll.parent = &clk_epllref.clk;
	346
	347	s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
e425382e	348
e425382e	349	s3c2443_setup_clocks();
e4d06e39	350
4e04691b	351	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
e4d06e39	352
9aa753c4 BD	353	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
	354	s3c_register_clksrc(clksrcs[ptr], 1);
	355
e4d06e39 BD	356	/* register clocks from clock array */
e4d06e39 BD	357
1d9f13c4	358	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
e4d06e39 BD	359
e4d06e39 BD	360	/* We must be careful disabling the clocks we are not intending to
3a4fa0a2	361	* be using at boot time, as subsystems such as the LCD which do
e4d06e39 BD	362	* their own DMA requests to the bus can cause the system to lockup
	363	* if they where in the middle of requesting bus access.
	364	*
	365	* Disabling the LCD clock if the LCD is active is very dangerous,
	366	* and therefore the bootloader should be careful to not enable
	367	* the LCD clock if it is not needed.
	368	*/
	369
	370	/* install (and disable) the clocks we do not need immediately */
	371
4e04691b BD	372	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
4e04691b BD	373	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
9d325f23 BD	374
9d325f23 BD	375	s3c_pwmclk_init();
e4d06e39	376	}