[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-s3c2440 / s3c2442.c

/* linux/arch/arm/mach-s3c2442/s3c2442.c
 *
 * Copyright (c) 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2442 core and lock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/syscore_ops.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mutex.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <linux/atomic.h>
#include <asm/irq.h>

#include <mach/regs-clock.h>

#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/s3c244x.h>
#include <plat/pm.h>

#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>

/* S3C2442 extended clock support */

static unsigned long s3c2442_camif_upll_round(struct clk *clk,
					      unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	int div;

	if (rate > parent_rate)
		return parent_rate;

	div = parent_rate / rate;

	if (div == 3)
		return parent_rate / 3;

	/* note, we remove the +/- 1 calculations for the divisor */

	div /= 2;

	if (div < 1)
		div = 1;
	else if (div > 16)
		div = 16;

	return parent_rate / (div * 2);
}

static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);

	rate = s3c2442_camif_upll_round(clk, rate);

	camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;

	if (rate == parent_rate) {
		camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
	} else if ((parent_rate / rate) == 3) {
		camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
		camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
	} else {
		camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
		camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
		camdivn |= (((parent_rate / rate) / 2) - 1);
	}

	__raw_writel(camdivn, S3C2440_CAMDIVN);

	return 0;
}

/* Extra S3C2442 clocks */

static struct clk s3c2442_clk_cam = {
	.name		= "camif",
	.id		= -1,
	.enable		= s3c2410_clkcon_enable,
	.ctrlbit	= S3C2440_CLKCON_CAMERA,
};

static struct clk s3c2442_clk_cam_upll = {
	.name		= "camif-upll",
	.id		= -1,
	.ops		= &(struct clk_ops) {
		.set_rate	= s3c2442_camif_upll_setrate,
		.round_rate	= s3c2442_camif_upll_round,
	},
};

static int s3c2442_clk_add(struct sys_device *sysdev)
{
	struct clk *clock_upll;
	struct clk *clock_h;
	struct clk *clock_p;

	clock_p = clk_get(NULL, "pclk");
	clock_h = clk_get(NULL, "hclk");
	clock_upll = clk_get(NULL, "upll");

	if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
		printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
		return -EINVAL;
	}

	s3c2442_clk_cam.parent = clock_h;
	s3c2442_clk_cam_upll.parent = clock_upll;

	s3c24xx_register_clock(&s3c2442_clk_cam);
	s3c24xx_register_clock(&s3c2442_clk_cam_upll);

	clk_disable(&s3c2442_clk_cam);

	return 0;
}

static struct sysdev_driver s3c2442_clk_driver = {
	.add	= s3c2442_clk_add,
};

static __init int s3c2442_clk_init(void)
{
	return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
}

arch_initcall(s3c2442_clk_init);


static struct sys_device s3c2442_sysdev = {
	.cls		= &s3c2442_sysclass,
};

int __init s3c2442_init(void)
{
	printk("S3C2442: Initialising architecture\n");

	register_syscore_ops(&s3c2410_pm_syscore_ops);
	register_syscore_ops(&s3c244x_pm_syscore_ops);
	register_syscore_ops(&s3c24xx_irq_syscore_ops);

	return sysdev_register(&s3c2442_sysdev);
}

void __init s3c2442_map_io(void)
{
	s3c244x_map_io();

	s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down;
	s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down;
}
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2442/s3c2442.c
96ce2385	2	*
491547d4 BD	3	* Copyright (c) 2004-2005 Simtec Electronics
	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
96ce2385	6	*
491547d4	7	* S3C2442 core and lock support
96ce2385 BD	8	*
96ce2385 BD	9	* This program is free software; you can redistribute it and/or modify
491547d4 BD	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
96ce2385 BD	22	*/
96ce2385 BD	23
491547d4 BD	24	#include <linux/init.h>
491547d4 BD	25	#include <linux/module.h>
96ce2385	26	#include <linux/kernel.h>
96ce2385	27	#include <linux/list.h>
491547d4 BD	28	#include <linux/errno.h>
	29	#include <linux/err.h>
	30	#include <linux/device.h>
96ce2385	31	#include <linux/sysdev.h>
bb072c3c	32	#include <linux/syscore_ops.h>
491547d4 BD	33	#include <linux/interrupt.h>
	34	#include <linux/ioport.h>
	35	#include <linux/mutex.h>
812c4e40	36	#include <linux/gpio.h>
491547d4 BD	37	#include <linux/clk.h>
491547d4 BD	38	#include <linux/io.h>
96ce2385	39
491547d4	40	#include <mach/hardware.h>
60063497	41	#include <linux/atomic.h>
491547d4 BD	42	#include <asm/irq.h>
	43
	44	#include <mach/regs-clock.h>
	45
	46	#include <plat/clock.h>
a2b7ba9c	47	#include <plat/cpu.h>
812c4e40	48	#include <plat/s3c244x.h>
bb072c3c	49	#include <plat/pm.h>
812c4e40 VK	50
	51	#include <plat/gpio-core.h>
	52	#include <plat/gpio-cfg.h>
	53	#include <plat/gpio-cfg-helpers.h>
96ce2385	54
491547d4 BD	55	/* S3C2442 extended clock support */
	56
	57	static unsigned long s3c2442_camif_upll_round(struct clk *clk,
	58	unsigned long rate)
	59	{
	60	unsigned long parent_rate = clk_get_rate(clk->parent);
	61	int div;
	62
	63	if (rate > parent_rate)
	64	return parent_rate;
	65
	66	div = parent_rate / rate;
	67
	68	if (div == 3)
	69	return parent_rate / 3;
	70
	71	/* note, we remove the +/- 1 calculations for the divisor */
	72
	73	div /= 2;
	74
	75	if (div < 1)
	76	div = 1;
	77	else if (div > 16)
	78	div = 16;
	79
	80	return parent_rate / (div * 2);
	81	}
	82
	83	static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
	84	{
	85	unsigned long parent_rate = clk_get_rate(clk->parent);
	86	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
	87
	88	rate = s3c2442_camif_upll_round(clk, rate);
	89
	90	camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
	91
	92	if (rate == parent_rate) {
	93	camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
	94	} else if ((parent_rate / rate) == 3) {
	95	camdivn \|= S3C2440_CAMDIVN_CAMCLK_SEL;
	96	camdivn \|= S3C2442_CAMDIVN_CAMCLK_DIV3;
	97	} else {
	98	camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
	99	camdivn \|= S3C2440_CAMDIVN_CAMCLK_SEL;
	100	camdivn \|= (((parent_rate / rate) / 2) - 1);
	101	}
	102
	103	__raw_writel(camdivn, S3C2440_CAMDIVN);
	104
	105	return 0;
	106	}
	107
	108	/* Extra S3C2442 clocks */
	109
	110	static struct clk s3c2442_clk_cam = {
	111	.name = "camif",
	112	.id = -1,
	113	.enable = s3c2410_clkcon_enable,
	114	.ctrlbit = S3C2440_CLKCON_CAMERA,
	115	};
	116
	117	static struct clk s3c2442_clk_cam_upll = {
	118	.name = "camif-upll",
119	.id = -1,
120	.ops = &(struct clk_ops) {
121	.set_rate = s3c2442_camif_upll_setrate,
122	.round_rate = s3c2442_camif_upll_round,
123	},
124	};
125
126	static int s3c2442_clk_add(struct sys_device *sysdev)
127	{
128	struct clk *clock_upll;
129	struct clk *clock_h;
130	struct clk *clock_p;
131
132	clock_p = clk_get(NULL, "pclk");
133	clock_h = clk_get(NULL, "hclk");
134	clock_upll = clk_get(NULL, "upll");
135
136	if (IS_ERR(clock_p) \|\| IS_ERR(clock_h) \|\| IS_ERR(clock_upll)) {
137	printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
138	return -EINVAL;
139	}
140
141	s3c2442_clk_cam.parent = clock_h;
142	s3c2442_clk_cam_upll.parent = clock_upll;
143
144	s3c24xx_register_clock(&s3c2442_clk_cam);
145	s3c24xx_register_clock(&s3c2442_clk_cam_upll);
146
147	clk_disable(&s3c2442_clk_cam);
148
149	return 0;
150	}
151
152	static struct sysdev_driver s3c2442_clk_driver = {
153	.add = s3c2442_clk_add,
154	};
155
156	static __init int s3c2442_clk_init(void)
157	{
158	return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
159	}
160
161	arch_initcall(s3c2442_clk_init);
162
163
96ce2385 BD	164	static struct sys_device s3c2442_sysdev = {
	165	.cls = &s3c2442_sysclass,
	166	};
	167
	168	int __init s3c2442_init(void)
	169	{
	170	printk("S3C2442: Initialising architecture\n");
	171
bb072c3c RW	172	register_syscore_ops(&s3c2410_pm_syscore_ops);
	173	register_syscore_ops(&s3c244x_pm_syscore_ops);
	174	register_syscore_ops(&s3c24xx_irq_syscore_ops);
	175
96ce2385 BD	176	return sysdev_register(&s3c2442_sysdev);
96ce2385 BD	177	}
812c4e40 VK	178
	179	void __init s3c2442_map_io(void)
	180	{
	181	s3c244x_map_io();
	182
	183	s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down;
	184	s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down;
	185	}