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a21765a7 | 1 | /* linux/arch/arm/mach-s3c2442/s3c2442.c |
96ce2385 | 2 | * |
491547d4 BD |
3 | * Copyright (c) 2004-2005 Simtec Electronics |
4 | * http://armlinux.simtec.co.uk/ | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
96ce2385 | 6 | * |
491547d4 | 7 | * S3C2442 core and lock support |
96ce2385 BD |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
491547d4 BD |
10 | * it under the terms of the GNU General Public License as published by |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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22 | */ |
23 | ||
491547d4 BD |
24 | #include <linux/init.h> |
25 | #include <linux/module.h> | |
96ce2385 | 26 | #include <linux/kernel.h> |
96ce2385 | 27 | #include <linux/list.h> |
491547d4 BD |
28 | #include <linux/errno.h> |
29 | #include <linux/err.h> | |
30 | #include <linux/device.h> | |
96ce2385 | 31 | #include <linux/sysdev.h> |
491547d4 BD |
32 | #include <linux/interrupt.h> |
33 | #include <linux/ioport.h> | |
34 | #include <linux/mutex.h> | |
812c4e40 | 35 | #include <linux/gpio.h> |
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36 | #include <linux/clk.h> |
37 | #include <linux/io.h> | |
96ce2385 | 38 | |
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39 | #include <mach/hardware.h> |
40 | #include <asm/atomic.h> | |
41 | #include <asm/irq.h> | |
42 | ||
43 | #include <mach/regs-clock.h> | |
44 | ||
45 | #include <plat/clock.h> | |
a2b7ba9c | 46 | #include <plat/cpu.h> |
812c4e40 VK |
47 | #include <plat/s3c244x.h> |
48 | ||
49 | #include <plat/gpio-core.h> | |
50 | #include <plat/gpio-cfg.h> | |
51 | #include <plat/gpio-cfg-helpers.h> | |
96ce2385 | 52 | |
491547d4 BD |
53 | /* S3C2442 extended clock support */ |
54 | ||
55 | static unsigned long s3c2442_camif_upll_round(struct clk *clk, | |
56 | unsigned long rate) | |
57 | { | |
58 | unsigned long parent_rate = clk_get_rate(clk->parent); | |
59 | int div; | |
60 | ||
61 | if (rate > parent_rate) | |
62 | return parent_rate; | |
63 | ||
64 | div = parent_rate / rate; | |
65 | ||
66 | if (div == 3) | |
67 | return parent_rate / 3; | |
68 | ||
69 | /* note, we remove the +/- 1 calculations for the divisor */ | |
70 | ||
71 | div /= 2; | |
72 | ||
73 | if (div < 1) | |
74 | div = 1; | |
75 | else if (div > 16) | |
76 | div = 16; | |
77 | ||
78 | return parent_rate / (div * 2); | |
79 | } | |
80 | ||
81 | static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate) | |
82 | { | |
83 | unsigned long parent_rate = clk_get_rate(clk->parent); | |
84 | unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); | |
85 | ||
86 | rate = s3c2442_camif_upll_round(clk, rate); | |
87 | ||
88 | camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3; | |
89 | ||
90 | if (rate == parent_rate) { | |
91 | camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL; | |
92 | } else if ((parent_rate / rate) == 3) { | |
93 | camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; | |
94 | camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3; | |
95 | } else { | |
96 | camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK; | |
97 | camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; | |
98 | camdivn |= (((parent_rate / rate) / 2) - 1); | |
99 | } | |
100 | ||
101 | __raw_writel(camdivn, S3C2440_CAMDIVN); | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | /* Extra S3C2442 clocks */ | |
107 | ||
108 | static struct clk s3c2442_clk_cam = { | |
109 | .name = "camif", | |
110 | .id = -1, | |
111 | .enable = s3c2410_clkcon_enable, | |
112 | .ctrlbit = S3C2440_CLKCON_CAMERA, | |
113 | }; | |
114 | ||
115 | static struct clk s3c2442_clk_cam_upll = { | |
116 | .name = "camif-upll", | |
117 | .id = -1, | |
118 | .ops = &(struct clk_ops) { | |
119 | .set_rate = s3c2442_camif_upll_setrate, | |
120 | .round_rate = s3c2442_camif_upll_round, | |
121 | }, | |
122 | }; | |
123 | ||
124 | static int s3c2442_clk_add(struct sys_device *sysdev) | |
125 | { | |
126 | struct clk *clock_upll; | |
127 | struct clk *clock_h; | |
128 | struct clk *clock_p; | |
129 | ||
130 | clock_p = clk_get(NULL, "pclk"); | |
131 | clock_h = clk_get(NULL, "hclk"); | |
132 | clock_upll = clk_get(NULL, "upll"); | |
133 | ||
134 | if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { | |
135 | printk(KERN_ERR "S3C2442: Failed to get parent clocks\n"); | |
136 | return -EINVAL; | |
137 | } | |
138 | ||
139 | s3c2442_clk_cam.parent = clock_h; | |
140 | s3c2442_clk_cam_upll.parent = clock_upll; | |
141 | ||
142 | s3c24xx_register_clock(&s3c2442_clk_cam); | |
143 | s3c24xx_register_clock(&s3c2442_clk_cam_upll); | |
144 | ||
145 | clk_disable(&s3c2442_clk_cam); | |
146 | ||
147 | return 0; | |
148 | } | |
149 | ||
150 | static struct sysdev_driver s3c2442_clk_driver = { | |
151 | .add = s3c2442_clk_add, | |
152 | }; | |
153 | ||
154 | static __init int s3c2442_clk_init(void) | |
155 | { | |
156 | return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver); | |
157 | } | |
158 | ||
159 | arch_initcall(s3c2442_clk_init); | |
160 | ||
161 | ||
96ce2385 BD |
162 | static struct sys_device s3c2442_sysdev = { |
163 | .cls = &s3c2442_sysclass, | |
164 | }; | |
165 | ||
166 | int __init s3c2442_init(void) | |
167 | { | |
168 | printk("S3C2442: Initialising architecture\n"); | |
169 | ||
170 | return sysdev_register(&s3c2442_sysdev); | |
171 | } | |
812c4e40 VK |
172 | |
173 | void __init s3c2442_map_io(void) | |
174 | { | |
175 | s3c244x_map_io(); | |
176 | ||
177 | s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down; | |
178 | s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down; | |
179 | } |