[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-s3c2410 / s3c2440-clock.c

/* linux/arch/arm/mach-s3c2410/s3c2440-clock.c
 *
 * Copyright (c) 2004-2005 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2440 Clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mutex.h>
#include <linux/clk.h>

#include <asm/hardware.h>
#include <asm/atomic.h>
#include <asm/irq.h>
#include <asm/io.h>

#include <asm/arch/regs-clock.h>

#include "clock.h"
#include "cpu.h"

/* S3C2440 extended clock support */

static unsigned long s3c2440_camif_upll_round(struct clk *clk,
					      unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	int div;

	if (rate > parent_rate)
		return parent_rate;

	/* note, we remove the +/- 1 calculations for the divisor */

	div = (parent_rate / rate) / 2;

	if (div < 1)
		div = 1;
	else if (div > 16)
		div = 16;

	return parent_rate / (div * 2);
}

static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
{
	unsigned long parent_rate = clk_get_rate(clk->parent);
	unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);

	rate = s3c2440_camif_upll_round(clk, rate);

	camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);

	if (rate != parent_rate) {
		camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
		camdivn |= (((parent_rate / rate) / 2) - 1);
	}

	__raw_writel(camdivn, S3C2440_CAMDIVN);

	return 0;
}

/* Extra S3C2440 clocks */

static struct clk s3c2440_clk_cam = {
	.name		= "camif",
	.id		= -1,
	.enable		= s3c24xx_clkcon_enable,
	.ctrlbit	= S3C2440_CLKCON_CAMERA,
};

static struct clk s3c2440_clk_cam_upll = {
	.name		= "camif-upll",
	.id		= -1,
	.set_rate	= s3c2440_camif_upll_setrate,
	.round_rate	= s3c2440_camif_upll_round,
};

static struct clk s3c2440_clk_ac97 = {
	.name		= "ac97",
	.id		= -1,
	.enable		= s3c24xx_clkcon_enable,
	.ctrlbit	= S3C2440_CLKCON_CAMERA,
};

static int s3c2440_clk_add(struct sys_device *sysdev)
{
	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
	unsigned long clkdivn;
	struct clk *clk_h;
	struct clk *clk_p;
	struct clk *clk_upll;

	printk("S3C2440: Clock Support, DVS %s\n",
	       (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");

	clk_p = clk_get(NULL, "pclk");
	clk_h = clk_get(NULL, "hclk");
	clk_upll = clk_get(NULL, "upll");

	if (IS_ERR(clk_p) || IS_ERR(clk_h) || IS_ERR(clk_upll)) {
		printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
		return -EINVAL;
	}

	/* check rate of UPLL, and if it is near 96MHz, then change
	 * to using half the UPLL rate for the system */

	if (clk_get_rate(clk_upll) > (94 * MHZ)) {
		clk_usb_bus.rate = clk_get_rate(clk_upll) / 2;

		mutex_lock(&clocks_mutex);

		clkdivn = __raw_readl(S3C2410_CLKDIVN);
		clkdivn |= S3C2440_CLKDIVN_UCLK;
		__raw_writel(camdivn, S3C2410_CLKDIVN);

		mutex_unlock(&clocks_mutex);
	}

	s3c2440_clk_cam.parent = clk_h;
	s3c2440_clk_ac97.parent = clk_p;
	s3c2440_clk_cam_upll.parent = clk_upll;

	s3c24xx_register_clock(&s3c2440_clk_ac97);
	s3c24xx_register_clock(&s3c2440_clk_cam);
	s3c24xx_register_clock(&s3c2440_clk_cam_upll);

	clk_disable(&s3c2440_clk_ac97);
	clk_disable(&s3c2440_clk_cam);

	return 0;
}

static struct sysdev_driver s3c2440_clk_driver = {
	.add	= s3c2440_clk_add,
};

static __init int s3c24xx_clk_driver(void)
{
	return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
}

arch_initcall(s3c24xx_clk_driver);
Commit	Line	Data
a8d11e3d BD	1	/* linux/arch/arm/mach-s3c2410/s3c2440-clock.c
	2	*
	3	* Copyright (c) 2004-2005 Simtec Electronics
	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* S3C2440 Clock support
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23
	24	#include <linux/init.h>
	25	#include <linux/module.h>
	26	#include <linux/kernel.h>
	27	#include <linux/list.h>
	28	#include <linux/errno.h>
	29	#include <linux/err.h>
	30	#include <linux/device.h>
	31	#include <linux/sysdev.h>
a8d11e3d BD	32	#include <linux/interrupt.h>
a8d11e3d BD	33	#include <linux/ioport.h>
36c64af4	34	#include <linux/mutex.h>
f8ce2547	35	#include <linux/clk.h>
a8d11e3d BD	36
	37	#include <asm/hardware.h>
	38	#include <asm/atomic.h>
	39	#include <asm/irq.h>
	40	#include <asm/io.h>
	41
a8d11e3d BD	42	#include <asm/arch/regs-clock.h>
	43
	44	#include "clock.h"
	45	#include "cpu.h"
	46
	47	/* S3C2440 extended clock support */
	48
e44c0396 BD	49	static unsigned long s3c2440_camif_upll_round(struct clk *clk,
	50	unsigned long rate)
	51	{
	52	unsigned long parent_rate = clk_get_rate(clk->parent);
	53	int div;
	54
	55	if (rate > parent_rate)
	56	return parent_rate;
	57
	58	/* note, we remove the +/- 1 calculations for the divisor */
	59
	60	div = (parent_rate / rate) / 2;
	61
	62	if (div < 1)
	63	div = 1;
	64	else if (div > 16)
	65	div = 16;
	66
	67	return parent_rate / (div * 2);
	68	}
	69
	70	static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
	71	{
	72	unsigned long parent_rate = clk_get_rate(clk->parent);
	73	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
	74
	75	rate = s3c2440_camif_upll_round(clk, rate);
	76
	77	camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL \| S3C2440_CAMDIVN_CAMCLK_MASK);
	78
	79	if (rate != parent_rate) {
	80	camdivn \|= S3C2440_CAMDIVN_CAMCLK_SEL;
	81	camdivn \|= (((parent_rate / rate) / 2) - 1);
	82	}
	83
	84	__raw_writel(camdivn, S3C2440_CAMDIVN);
	85
	86	return 0;
	87	}
	88
	89	/* Extra S3C2440 clocks */
	90
a8d11e3d BD	91	static struct clk s3c2440_clk_cam = {
	92	.name = "camif",
	93	.id = -1,
	94	.enable = s3c24xx_clkcon_enable,
	95	.ctrlbit = S3C2440_CLKCON_CAMERA,
	96	};
	97
e44c0396 BD	98	static struct clk s3c2440_clk_cam_upll = {
	99	.name = "camif-upll",
	100	.id = -1,
	101	.set_rate = s3c2440_camif_upll_setrate,
	102	.round_rate = s3c2440_camif_upll_round,
	103	};
	104
a8d11e3d BD	105	static struct clk s3c2440_clk_ac97 = {
	106	.name = "ac97",
	107	.id = -1,
	108	.enable = s3c24xx_clkcon_enable,
	109	.ctrlbit = S3C2440_CLKCON_CAMERA,
	110	};
	111
	112	static int s3c2440_clk_add(struct sys_device *sysdev)
	113	{
01b9c414	114	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
36c64af4	115	unsigned long clkdivn;
a8d11e3d BD	116	struct clk *clk_h;
a8d11e3d BD	117	struct clk *clk_p;
36c64af4	118	struct clk *clk_upll;
a8d11e3d	119
8e40a2f9	120	printk("S3C2440: Clock Support, DVS %s\n",
01b9c414	121	(camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
a8d11e3d BD	122
	123	clk_p = clk_get(NULL, "pclk");
	124	clk_h = clk_get(NULL, "hclk");
36c64af4	125	clk_upll = clk_get(NULL, "upll");
a8d11e3d	126
36c64af4	127	if (IS_ERR(clk_p) \|\| IS_ERR(clk_h) \|\| IS_ERR(clk_upll)) {
a8d11e3d BD	128	printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
	129	return -EINVAL;
	130	}
	131
36c64af4 BD	132	/* check rate of UPLL, and if it is near 96MHz, then change
	133	* to using half the UPLL rate for the system */
	134
	135	if (clk_get_rate(clk_upll) > (94 * MHZ)) {
	136	clk_usb_bus.rate = clk_get_rate(clk_upll) / 2;
	137
	138	mutex_lock(&clocks_mutex);
	139
	140	clkdivn = __raw_readl(S3C2410_CLKDIVN);
	141	clkdivn \|= S3C2440_CLKDIVN_UCLK;
	142	__raw_writel(camdivn, S3C2410_CLKDIVN);
	143
	144	mutex_unlock(&clocks_mutex);
	145	}
	146
a8d11e3d BD	147	s3c2440_clk_cam.parent = clk_h;
a8d11e3d BD	148	s3c2440_clk_ac97.parent = clk_p;
e44c0396	149	s3c2440_clk_cam_upll.parent = clk_upll;
a8d11e3d BD	150
	151	s3c24xx_register_clock(&s3c2440_clk_ac97);
	152	s3c24xx_register_clock(&s3c2440_clk_cam);
e44c0396	153	s3c24xx_register_clock(&s3c2440_clk_cam_upll);
a8d11e3d BD	154
	155	clk_disable(&s3c2440_clk_ac97);
	156	clk_disable(&s3c2440_clk_cam);
	157
	158	return 0;
	159	}
	160
	161	static struct sysdev_driver s3c2440_clk_driver = {
	162	.add = s3c2440_clk_add,
	163	};
	164
	165	static __init int s3c24xx_clk_driver(void)
	166	{
	167	return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
	168	}
	169
	170	arch_initcall(s3c24xx_clk_driver);