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862184fe RK |
1 | /* |
2 | * linux/arch/arm/mach-realview/platsmp.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
934848da | 15 | #include <linux/jiffies.h> |
862184fe | 16 | #include <linux/smp.h> |
fced80c7 | 17 | #include <linux/io.h> |
862184fe RK |
18 | |
19 | #include <asm/cacheflush.h> | |
a09e64fb | 20 | #include <mach/hardware.h> |
7dd19e75 | 21 | #include <asm/mach-types.h> |
dff2ab16 | 22 | #include <asm/unified.h> |
862184fe | 23 | |
a09e64fb RK |
24 | #include <mach/board-eb.h> |
25 | #include <mach/board-pb11mp.h> | |
1b504bbe | 26 | #include <mach/board-pbx.h> |
49613d4d | 27 | #include <asm/smp_scu.h> |
b7b0ba94 | 28 | |
1bbdf637 CM |
29 | #include "core.h" |
30 | ||
862184fe RK |
31 | extern void realview_secondary_startup(void); |
32 | ||
33 | /* | |
34 | * control for which core is the next to come out of the secondary | |
35 | * boot "holding pen" | |
36 | */ | |
37 | volatile int __cpuinitdata pen_release = -1; | |
38 | ||
3705ff6d RK |
39 | /* |
40 | * Write pen_release in a way that is guaranteed to be visible to all | |
41 | * observers, irrespective of whether they're taking part in coherency | |
42 | * or not. This is necessary for the hotplug code to work reliably. | |
43 | */ | |
ec15038f | 44 | static void __cpuinit write_pen_release(int val) |
3705ff6d RK |
45 | { |
46 | pen_release = val; | |
47 | smp_wmb(); | |
48 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | |
49 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | |
50 | } | |
51 | ||
1bbdf637 CM |
52 | static void __iomem *scu_base_addr(void) |
53 | { | |
54 | if (machine_is_realview_eb_mp()) | |
55 | return __io_address(REALVIEW_EB11MP_SCU_BASE); | |
56 | else if (machine_is_realview_pb11mp()) | |
57 | return __io_address(REALVIEW_TC11MP_SCU_BASE); | |
1b504bbe CT |
58 | else if (machine_is_realview_pbx() && |
59 | (core_tile_pbx11mp() || core_tile_pbxa9mp())) | |
60 | return __io_address(REALVIEW_PBX_TILE_SCU_BASE); | |
1bbdf637 CM |
61 | else |
62 | return (void __iomem *)0; | |
63 | } | |
64 | ||
862184fe RK |
65 | static DEFINE_SPINLOCK(boot_lock); |
66 | ||
67 | void __cpuinit platform_secondary_init(unsigned int cpu) | |
68 | { | |
862184fe RK |
69 | /* |
70 | * if any interrupts are already enabled for the primary | |
71 | * core (e.g. timer irq), then they will not have been enabled | |
72 | * for us: do so | |
73 | */ | |
38489533 | 74 | gic_secondary_init(0); |
862184fe RK |
75 | |
76 | /* | |
77 | * let the primary processor know we're out of the | |
78 | * pen, then head off into the C entry point | |
79 | */ | |
3705ff6d | 80 | write_pen_release(-1); |
862184fe RK |
81 | |
82 | /* | |
83 | * Synchronise with the boot thread. | |
84 | */ | |
85 | spin_lock(&boot_lock); | |
86 | spin_unlock(&boot_lock); | |
87 | } | |
88 | ||
89 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
90 | { | |
91 | unsigned long timeout; | |
92 | ||
93 | /* | |
94 | * set synchronisation state between this boot processor | |
95 | * and the secondary one | |
96 | */ | |
97 | spin_lock(&boot_lock); | |
98 | ||
99 | /* | |
100 | * The secondary processor is waiting to be released from | |
101 | * the holding pen - release it, then wait for it to flag | |
102 | * that it has been released by resetting pen_release. | |
103 | * | |
104 | * Note that "pen_release" is the hardware CPU ID, whereas | |
105 | * "cpu" is Linux's internal ID. | |
106 | */ | |
3705ff6d | 107 | write_pen_release(cpu); |
862184fe RK |
108 | |
109 | /* | |
aec66ba1 RK |
110 | * Send the secondary CPU a soft interrupt, thereby causing |
111 | * the boot monitor to read the system wide flags register, | |
112 | * and branch to the address found there. | |
862184fe | 113 | */ |
ad3b6993 | 114 | smp_cross_call(cpumask_of(cpu), 1); |
862184fe RK |
115 | |
116 | timeout = jiffies + (1 * HZ); | |
117 | while (time_before(jiffies, timeout)) { | |
0e0ba769 | 118 | smp_rmb(); |
862184fe RK |
119 | if (pen_release == -1) |
120 | break; | |
121 | ||
122 | udelay(10); | |
123 | } | |
124 | ||
125 | /* | |
126 | * now the secondary core is starting up let it run its | |
127 | * calibrations, then wait for it to finish | |
128 | */ | |
129 | spin_unlock(&boot_lock); | |
130 | ||
131 | return pen_release != -1 ? -ENOSYS : 0; | |
132 | } | |
133 | ||
7bbb7940 RK |
134 | /* |
135 | * Initialise the CPU possible map early - this describes the CPUs | |
136 | * which may be present or become present in the system. | |
137 | */ | |
138 | void __init smp_init_cpus(void) | |
139 | { | |
fd778f0a RK |
140 | void __iomem *scu_base = scu_base_addr(); |
141 | unsigned int i, ncores; | |
7bbb7940 | 142 | |
fd778f0a | 143 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
862184fe RK |
144 | |
145 | /* sanity check */ | |
862184fe RK |
146 | if (ncores > NR_CPUS) { |
147 | printk(KERN_WARNING | |
148 | "Realview: no. of cores (%d) greater than configured " | |
149 | "maximum of %d - clipping\n", | |
150 | ncores, NR_CPUS); | |
151 | ncores = NR_CPUS; | |
152 | } | |
153 | ||
bbc3d14e RK |
154 | for (i = 0; i < ncores; i++) |
155 | set_cpu_possible(i, true); | |
156 | } | |
862184fe | 157 | |
05c74a6c | 158 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
bbc3d14e | 159 | { |
bbc3d14e | 160 | int i; |
862184fe RK |
161 | |
162 | /* | |
7bbb7940 RK |
163 | * Initialise the present map, which describes the set of CPUs |
164 | * actually populated at the present time. | |
862184fe | 165 | */ |
7bbb7940 | 166 | for (i = 0; i < max_cpus; i++) |
e03cdade | 167 | set_cpu_present(i, true); |
862184fe | 168 | |
05c74a6c RK |
169 | scu_enable(scu_base_addr()); |
170 | ||
862184fe | 171 | /* |
05c74a6c RK |
172 | * Write the address of secondary startup into the |
173 | * system-wide flags register. The BootMonitor waits | |
174 | * until it receives a soft interrupt, and then the | |
175 | * secondary CPU branches to this address. | |
862184fe | 176 | */ |
05c74a6c RK |
177 | __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)), |
178 | __io_address(REALVIEW_SYS_FLAGSSET)); | |
862184fe | 179 | } |