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[ARM] 3366/1: Allow the 16bpp mode configuration in the CLCD control register
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-realview / core.c
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CM		 1/*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/config.h>
22#include <linux/init.h>
1be7228d 23#include <linux/platform_device.h>
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CM		 24#include <linux/dma-mapping.h>
25#include <linux/sysdev.h>
26#include <linux/interrupt.h>
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RK		 27#include <linux/amba/bus.h>
28#include <linux/amba/clcd.h>
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CM		 29
30#include <asm/system.h>
31#include <asm/hardware.h>
32#include <asm/io.h>
33#include <asm/irq.h>
34#include <asm/leds.h>
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CM		 35#include <asm/hardware/arm_timer.h>
36#include <asm/hardware/icst307.h>
37
38#include <asm/mach/arch.h>
39#include <asm/mach/flash.h>
40#include <asm/mach/irq.h>
41#include <asm/mach/time.h>
42#include <asm/mach/map.h>
43#include <asm/mach/mmc.h>
44
45#include <asm/hardware/gic.h>
46
47#include "core.h"
48#include "clock.h"
49
50#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
51
52/*
53 * This is the RealView sched_clock implementation. This has
54 * a resolution of 41.7ns, and a maximum value of about 179s.
55 */
56unsigned long long sched_clock(void)
57{
58 unsigned long long v;
59
60 v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
61 do_div(v, 3);
62
63 return v;
64}
65
66
67#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
68
69static int realview_flash_init(void)
70{
71 u32 val;
72
73 val = __raw_readl(REALVIEW_FLASHCTRL);
74 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
75 __raw_writel(val, REALVIEW_FLASHCTRL);
76
77 return 0;
78}
79
80static void realview_flash_exit(void)
81{
82 u32 val;
83
84 val = __raw_readl(REALVIEW_FLASHCTRL);
85 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
86 __raw_writel(val, REALVIEW_FLASHCTRL);
87}
88
89static void realview_flash_set_vpp(int on)
90{
91 u32 val;
92
93 val = __raw_readl(REALVIEW_FLASHCTRL);
94 if (on)
95 val |= REALVIEW_FLASHPROG_FLVPPEN;
96 else
97 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
98 __raw_writel(val, REALVIEW_FLASHCTRL);
99}
100
101static struct flash_platform_data realview_flash_data = {
102 .map_name = "cfi_probe",
103 .width = 4,
104 .init = realview_flash_init,
105 .exit = realview_flash_exit,
106 .set_vpp = realview_flash_set_vpp,
107};
108
109static struct resource realview_flash_resource = {
110 .start = REALVIEW_FLASH_BASE,
111 .end = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
112 .flags = IORESOURCE_MEM,
113};
114
115struct platform_device realview_flash_device = {
116 .name = "armflash",
117 .id = 0,
118 .dev = {
119 .platform_data = &realview_flash_data,
120 },
121 .num_resources = 1,
122 .resource = &realview_flash_resource,
123};
124
125static struct resource realview_smc91x_resources[] = {
126 [0] = {
127 .start = REALVIEW_ETH_BASE,
128 .end = REALVIEW_ETH_BASE + SZ_64K - 1,
129 .flags = IORESOURCE_MEM,
130 },
131 [1] = {
132 .start = IRQ_ETH,
133 .end = IRQ_ETH,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138struct platform_device realview_smc91x_device = {
139 .name = "smc91x",
140 .id = 0,
141 .num_resources = ARRAY_SIZE(realview_smc91x_resources),
142 .resource = realview_smc91x_resources,
143};
144
145#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
146
147static unsigned int realview_mmc_status(struct device *dev)
148{
149 struct amba_device *adev = container_of(dev, struct amba_device, dev);
150 u32 mask;
151
152 if (adev->res.start == REALVIEW_MMCI0_BASE)
153 mask = 1;
154 else
155 mask = 2;
156
157 return readl(REALVIEW_SYSMCI) & mask;
158}
159
160struct mmc_platform_data realview_mmc0_plat_data = {
161 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
162 .status = realview_mmc_status,
163};
164
165struct mmc_platform_data realview_mmc1_plat_data = {
166 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
167 .status = realview_mmc_status,
168};
169
170/*
171 * Clock handling
172 */
173static const struct icst307_params realview_oscvco_params = {
174 .ref = 24000,
175 .vco_max = 200000,
176 .vd_min = 4 + 8,
177 .vd_max = 511 + 8,
178 .rd_min = 1 + 2,
179 .rd_max = 127 + 2,
180};
181
182static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
183{
184 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
f557f5e5 185 void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
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CM		 186 u32 val;
187
188 val = readl(sys_osc) & ~0x7ffff;
189 val |= vco.v | (vco.r << 9) | (vco.s << 16);
190
191 writel(0xa05f, sys_lock);
192 writel(val, sys_osc);
193 writel(0, sys_lock);
194}
195
196struct clk realview_clcd_clk = {
197 .name = "CLCDCLK",
198 .params = &realview_oscvco_params,
199 .setvco = realview_oscvco_set,
200};
201
202/*
203 * CLCD support.
204 */
205#define SYS_CLCD_MODE_MASK (3 << 0)
206#define SYS_CLCD_MODE_888 (0 << 0)
207#define SYS_CLCD_MODE_5551 (1 << 0)
208#define SYS_CLCD_MODE_565_RLSB (2 << 0)
209#define SYS_CLCD_MODE_565_BLSB (3 << 0)
210#define SYS_CLCD_NLCDIOON (1 << 2)
211#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
212#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
213#define SYS_CLCD_ID_MASK (0x1f << 8)
214#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
215#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
216#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
217#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
218#define SYS_CLCD_ID_VGA (0x1f << 8)
219
220static struct clcd_panel vga = {
221 .mode = {
222 .name = "VGA",
223 .refresh = 60,
224 .xres = 640,
225 .yres = 480,
226 .pixclock = 39721,
227 .left_margin = 40,
228 .right_margin = 24,
229 .upper_margin = 32,
230 .lower_margin = 11,
231 .hsync_len = 96,
232 .vsync_len = 2,
233 .sync = 0,
234 .vmode = FB_VMODE_NONINTERLACED,
235 },
236 .width = -1,
237 .height = -1,
238 .tim2 = TIM2_BCD | TIM2_IPC,
239 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
240 .bpp = 16,
241};
242
243static struct clcd_panel sanyo_3_8_in = {
244 .mode = {
245 .name = "Sanyo QVGA",
246 .refresh = 116,
247 .xres = 320,
248 .yres = 240,
249 .pixclock = 100000,
250 .left_margin = 6,
251 .right_margin = 6,
252 .upper_margin = 5,
253 .lower_margin = 5,
254 .hsync_len = 6,
255 .vsync_len = 6,
256 .sync = 0,
257 .vmode = FB_VMODE_NONINTERLACED,
258 },
259 .width = -1,
260 .height = -1,
261 .tim2 = TIM2_BCD,
262 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
263 .bpp = 16,
264};
265
266static struct clcd_panel sanyo_2_5_in = {
267 .mode = {
268 .name = "Sanyo QVGA Portrait",
269 .refresh = 116,
270 .xres = 240,
271 .yres = 320,
272 .pixclock = 100000,
273 .left_margin = 20,
274 .right_margin = 10,
275 .upper_margin = 2,
276 .lower_margin = 2,
277 .hsync_len = 10,
278 .vsync_len = 2,
279 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
280 .vmode = FB_VMODE_NONINTERLACED,
281 },
282 .width = -1,
283 .height = -1,
284 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
285 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
286 .bpp = 16,
287};
288
289static struct clcd_panel epson_2_2_in = {
290 .mode = {
291 .name = "Epson QCIF",
292 .refresh = 390,
293 .xres = 176,
294 .yres = 220,
295 .pixclock = 62500,
296 .left_margin = 3,
297 .right_margin = 2,
298 .upper_margin = 1,
299 .lower_margin = 0,
300 .hsync_len = 3,
301 .vsync_len = 2,
302 .sync = 0,
303 .vmode = FB_VMODE_NONINTERLACED,
304 },
305 .width = -1,
306 .height = -1,
307 .tim2 = TIM2_BCD | TIM2_IPC,
308 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
309 .bpp = 16,
310};
311
312/*
313 * Detect which LCD panel is connected, and return the appropriate
314 * clcd_panel structure. Note: we do not have any information on
315 * the required timings for the 8.4in panel, so we presently assume
316 * VGA timings.
317 */
318static struct clcd_panel *realview_clcd_panel(void)
319{
320 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
321 struct clcd_panel *panel = &vga;
322 u32 val;
323
324 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
325 if (val == SYS_CLCD_ID_SANYO_3_8)
326 panel = &sanyo_3_8_in;
327 else if (val == SYS_CLCD_ID_SANYO_2_5)
328 panel = &sanyo_2_5_in;
329 else if (val == SYS_CLCD_ID_EPSON_2_2)
330 panel = &epson_2_2_in;
331 else if (val == SYS_CLCD_ID_VGA)
332 panel = &vga;
333 else {
334 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
335 val);
336 panel = &vga;
337 }
338
339 return panel;
340}
341
342/*
343 * Disable all display connectors on the interface module.
344 */
345static void realview_clcd_disable(struct clcd_fb *fb)
346{
347 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
348 u32 val;
349
350 val = readl(sys_clcd);
351 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
352 writel(val, sys_clcd);
353}
354
355/*
356 * Enable the relevant connector on the interface module.
357 */
358static void realview_clcd_enable(struct clcd_fb *fb)
359{
360 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
361 u32 val;
362
363 val = readl(sys_clcd);
364 val &= ~SYS_CLCD_MODE_MASK;
365
366 switch (fb->fb.var.green.length) {
367 case 5:
368 val |= SYS_CLCD_MODE_5551;
369 break;
370 case 6:
371 val |= SYS_CLCD_MODE_565_RLSB;
372 break;
373 case 8:
374 val |= SYS_CLCD_MODE_888;
375 break;
376 }
377
378 /*
379 * Set the MUX
380 */
381 writel(val, sys_clcd);
382
383 /*
384 * And now enable the PSUs
385 */
386 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
387 writel(val, sys_clcd);
388}
389
390static unsigned long framesize = SZ_1M;
391
392static int realview_clcd_setup(struct clcd_fb *fb)
393{
394 dma_addr_t dma;
395
396 fb->panel = realview_clcd_panel();
397
398 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
399 &dma, GFP_KERNEL);
400 if (!fb->fb.screen_base) {
401 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
402 return -ENOMEM;
403 }
404
405 fb->fb.fix.smem_start = dma;
406 fb->fb.fix.smem_len = framesize;
407
408 return 0;
409}
410
411static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
412{
413 return dma_mmap_writecombine(&fb->dev->dev, vma,
414 fb->fb.screen_base,
415 fb->fb.fix.smem_start,
416 fb->fb.fix.smem_len);
417}
418
419static void realview_clcd_remove(struct clcd_fb *fb)
420{
421 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
422 fb->fb.screen_base, fb->fb.fix.smem_start);
423}
424
425struct clcd_board clcd_plat_data = {
426 .name = "RealView",
427 .check = clcdfb_check,
428 .decode = clcdfb_decode,
429 .disable = realview_clcd_disable,
430 .enable = realview_clcd_enable,
431 .setup = realview_clcd_setup,
432 .mmap = realview_clcd_mmap,
433 .remove = realview_clcd_remove,
434};
435
436#ifdef CONFIG_LEDS
437#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
438
439void realview_leds_event(led_event_t ledevt)
440{
441 unsigned long flags;
442 u32 val;
443
444 local_irq_save(flags);
445 val = readl(VA_LEDS_BASE);
446
447 switch (ledevt) {
448 case led_idle_start:
449 val = val & ~REALVIEW_SYS_LED0;
450 break;
451
452 case led_idle_end:
453 val = val | REALVIEW_SYS_LED0;
454 break;
455
456 case led_timer:
457 val = val ^ REALVIEW_SYS_LED1;
458 break;
459
460 case led_halted:
461 val = 0;
462 break;
463
464 default:
465 break;
466 }
467
468 writel(val, VA_LEDS_BASE);
469 local_irq_restore(flags);
470}
471#endif /* CONFIG_LEDS */
472
473/*
474 * Where is the timer (VA)?
475 */
476#define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE)
477#define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
478#define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE)
479#define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
480
481/*
482 * How long is the timer interval?
483 */
484#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
485#if TIMER_INTERVAL >= 0x100000
486#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
487#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
488#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
489#elif TIMER_INTERVAL >= 0x10000
490#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
491#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
492#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
493#else
494#define TIMER_RELOAD (TIMER_INTERVAL)
495#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
496#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
497#endif
498
499/*
500 * Returns number of ms since last clock interrupt. Note that interrupts
501 * will have been disabled by do_gettimeoffset()
502 */
503static unsigned long realview_gettimeoffset(void)
504{
505 unsigned long ticks1, ticks2, status;
506
507 /*
508 * Get the current number of ticks. Note that there is a race
509 * condition between us reading the timer and checking for
510 * an interrupt. We get around this by ensuring that the
511 * counter has not reloaded between our two reads.
512 */
513 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
514 do {
515 ticks1 = ticks2;
516 status = __raw_readl(__io_address(REALVIEW_GIC_DIST_BASE + GIC_DIST_PENDING_SET)
517 + ((IRQ_TIMERINT0_1 >> 5) << 2));
518 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
519 } while (ticks2 > ticks1);
520
521 /*
522 * Number of ticks since last interrupt.
523 */
524 ticks1 = TIMER_RELOAD - ticks2;
525
526 /*
527 * Interrupt pending? If so, we've reloaded once already.
528 *
529 * FIXME: Need to check this is effectively timer 0 that expires
530 */
531 if (status & IRQMASK_TIMERINT0_1)
532 ticks1 += TIMER_RELOAD;
533
534 /*
535 * Convert the ticks to usecs
536 */
537 return TICKS2USECS(ticks1);
538}
539
540/*
541 * IRQ handler for the timer
542 */
543static irqreturn_t realview_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
544{
545 write_seqlock(&xtime_lock);
546
547 // ...clear the interrupt
548 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
549
550 timer_tick(regs);
551
2a98beb6 552#if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
dbebb4cb
RK		 553 smp_send_timer();
554 update_process_times(user_mode(regs));
555#endif
556
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CM		 557 write_sequnlock(&xtime_lock);
558
559 return IRQ_HANDLED;
560}
561
562static struct irqaction realview_timer_irq = {
563 .name = "RealView Timer Tick",
564 .flags = SA_INTERRUPT | SA_TIMER,
565 .handler = realview_timer_interrupt,
566};
567
568/*
569 * Set up timer interrupt, and return the current time in seconds.
570 */
571static void __init realview_timer_init(void)
572{
573 u32 val;
574
575 /*
576 * set clock frequency:
577 * REALVIEW_REFCLK is 32KHz
578 * REALVIEW_TIMCLK is 1MHz
579 */
580 val = readl(__io_address(REALVIEW_SCTL_BASE));
581 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
582 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
583 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
584 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
585 __io_address(REALVIEW_SCTL_BASE));
586
587 /*
588 * Initialise to a known state (all timers off)
589 */
590 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
591 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
592 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
593 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
594
595 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
596 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
597 writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
598 TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
599
600 /*
601 * Make irqs happen for the system timer
602 */
603 setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq);
604}
605
606struct sys_timer realview_timer = {
607 .init = realview_timer_init,
608 .offset = realview_gettimeoffset,
609};
kernel source for telekom puls (alcatel/mediatek)