[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-pxa / pxa25x.c

/*
 *  linux/arch/arm/mach-pxa/pxa25x.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 * Code specific to PXA21x/25x/26x variants.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Since this file should be linked before any other machine specific file,
 * the __initcall() here will be executed first.  This serves as default
 * initialization stuff for PXA machines which can be overridden later if
 * need be.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/suspend.h>
#include <linux/sysdev.h>

#include <asm/hardware.h>
#include <asm/arch/irqs.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/mfp-pxa25x.h>
#include <asm/arch/pm.h>
#include <asm/arch/dma.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/*
 * Various clock factors driven by the CCCR register.
 */

/* Crystal Frequency to Memory Frequency Multiplier (L) */
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };

/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };

/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };

/* Crystal clock */
#define BASE_CLK	3686400

/*
 * Get the clock frequency as reflected by CCCR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa25x_get_clk_frequency_khz(int info)
{
	unsigned long cccr, turbo;
	unsigned int l, L, m, M, n2, N;

	cccr = CCCR;
	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );

	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
	m  =  M_clk_mult[(cccr >> 5) & 0x03];
	n2 = N2_clk_mult[(cccr >> 7) & 0x07];

	L = l * BASE_CLK;
	M = m * L;
	N = n2 * M / 2;

	if(info)
	{
		L += 5000;
		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
			L / 1000000, (L % 1000000) / 10000, l );
		M += 5000;
		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
			M / 1000000, (M % 1000000) / 10000, m );
		N += 5000;
		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
			(turbo & 1) ? "" : "in" );
	}

	return (turbo & 1) ? (N/1000) : (M/1000);
}

/*
 * Return the current memory clock frequency in units of 10kHz
 */
unsigned int pxa25x_get_memclk_frequency_10khz(void)
{
	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
}

static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
{
	return pxa25x_get_memclk_frequency_10khz() * 10000;
}

static const struct clkops clk_pxa25x_lcd_ops = {
	.enable		= clk_cken_enable,
	.disable	= clk_cken_disable,
	.getrate	= clk_pxa25x_lcd_getrate,
};

/*
 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
 */
static struct clk pxa25x_hwuart_clk =
	INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
;

/*
 * PXA 2xx clock declarations. Order is important (see aliases below)
 * Please be careful not to disrupt the ordering.
 */
static struct clk pxa25x_clks[] = {
	INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
	INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
	INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
	INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
	INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
	INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
	INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),

	INIT_CKEN("SSPCLK",  SSP, 3686400, 0, &pxa25x_device_ssp.dev),
	INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
	INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),

	INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),

	/*
	INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
	INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
	INIT_CKEN("I2SCLK",  I2S,  14745600, 0, NULL),
	*/
	INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
};

static struct clk gpio7_clk = INIT_CKOTHER("GPIO7_CK", &pxa25x_clks[4], NULL);

#ifdef CONFIG_PM

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */
enum {	SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,

	SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
	SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
	SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,

	SLEEP_SAVE_PSTR,

	SLEEP_SAVE_CKEN,

	SLEEP_SAVE_COUNT
};


static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);

	SAVE(GAFR0_L); SAVE(GAFR0_U);
	SAVE(GAFR1_L); SAVE(GAFR1_U);
	SAVE(GAFR2_L); SAVE(GAFR2_U);

	SAVE(CKEN);
	SAVE(PSTR);

	/* Clear GPIO transition detect bits */
	GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
}

static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
{
	/* ensure not to come back here if it wasn't intended */
	PSPR = 0;

	/* restore registers */
	RESTORE(GAFR0_L); RESTORE(GAFR0_U);
	RESTORE(GAFR1_L); RESTORE(GAFR1_U);
	RESTORE(GAFR2_L); RESTORE(GAFR2_U);
	RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);

	PSSR = PSSR_RDH | PSSR_PH;

	RESTORE(CKEN);
	RESTORE(PSTR);
}

static void pxa25x_cpu_pm_enter(suspend_state_t state)
{
	/* Clear reset status */
	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;

	switch (state) {
	case PM_SUSPEND_MEM:
		/* set resume return address */
		PSPR = virt_to_phys(pxa_cpu_resume);
		pxa25x_cpu_suspend(PWRMODE_SLEEP);
		break;
	}
}

static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.valid		= suspend_valid_only_mem,
	.save		= pxa25x_cpu_pm_save,
	.restore	= pxa25x_cpu_pm_restore,
	.enter		= pxa25x_cpu_pm_enter,
};

static void __init pxa25x_init_pm(void)
{
	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
}
#else
static inline void pxa25x_init_pm(void) {}
#endif

/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
 */

static int pxa25x_set_wake(unsigned int irq, unsigned int on)
{
	int gpio = IRQ_TO_GPIO(irq);
	uint32_t mask = 0;

	if (gpio >= 0 && gpio < 85)
		return gpio_set_wake(gpio, on);

	if (irq == IRQ_RTCAlrm) {
		mask = PWER_RTC;
		goto set_pwer;
	}

	return -EINVAL;

set_pwer:
	if (on)
		PWER |= mask;
	else
		PWER &=~mask;

	return 0;
}

void __init pxa25x_init_irq(void)
{
	pxa_init_irq(32, pxa25x_set_wake);
	pxa_init_gpio(85, pxa25x_set_wake);
}

static struct platform_device *pxa25x_devices[] __initdata = {
	&pxa_device_udc,
	&pxa_device_ffuart,
	&pxa_device_btuart,
	&pxa_device_stuart,
	&pxa_device_i2s,
	&pxa_device_rtc,
	&pxa25x_device_ssp,
	&pxa25x_device_nssp,
	&pxa25x_device_assp,
};

static struct sys_device pxa25x_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	},
};

static int __init pxa25x_init(void)
{
	int i, ret = 0;

	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
	if (cpu_is_pxa25x())
		clks_register(&pxa25x_hwuart_clk, 1);

	if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
		clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));

		if ((ret = pxa_init_dma(16)))
			return ret;

		pxa25x_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
			ret = sysdev_register(&pxa25x_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(pxa25x_devices,
					   ARRAY_SIZE(pxa25x_devices));
		if (ret)
			return ret;
	}

	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
	if (cpu_is_pxa25x())
		ret = platform_device_register(&pxa_device_hwuart);

	clks_register(&gpio7_clk, 1);

	return ret;
}

postcore_initcall(pxa25x_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/pxa25x.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Jun 15, 2001
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code specific to PXA21x/25x/26x variants.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* Since this file should be linked before any other machine specific file,
	15	* the __initcall() here will be executed first. This serves as default
	16	* initialization stuff for PXA machines which can be overridden later if
	17	* need be.
	18	*/
	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
34f3231f	22	#include <linux/platform_device.h>
95d9ffbe	23	#include <linux/suspend.h>
c0165504	24	#include <linux/sysdev.h>
1da177e4 LT	25
1da177e4 LT	26	#include <asm/hardware.h>
cd49104d	27	#include <asm/arch/irqs.h>
1da177e4	28	#include <asm/arch/pxa-regs.h>
c0a596d6	29	#include <asm/arch/mfp-pxa25x.h>
e176bb05	30	#include <asm/arch/pm.h>
f53f066c	31	#include <asm/arch/dma.h>
1da177e4 LT	32
1da177e4 LT	33	#include "generic.h"
46c41e62	34	#include "devices.h"
a6dba20c	35	#include "clock.h"
1da177e4 LT	36
	37	/*
	38	* Various clock factors driven by the CCCR register.
	39	*/
	40
	41	/* Crystal Frequency to Memory Frequency Multiplier (L) */
	42	static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
	43
	44	/* Memory Frequency to Run Mode Frequency Multiplier (M) */
	45	static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
	46
	47	/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
	48	/* Note: we store the value N * 2 here. */
	49	static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
	50
	51	/* Crystal clock */
	52	#define BASE_CLK 3686400
	53
	54	/*
	55	* Get the clock frequency as reflected by CCCR and the turbo flag.
	56	* We assume these values have been applied via a fcs.
	57	* If info is not 0 we also display the current settings.
	58	*/
15a40333	59	unsigned int pxa25x_get_clk_frequency_khz(int info)
1da177e4 LT	60	{
	61	unsigned long cccr, turbo;
	62	unsigned int l, L, m, M, n2, N;
	63
	64	cccr = CCCR;
	65	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
	66
	67	l = L_clk_mult[(cccr >> 0) & 0x1f];
	68	m = M_clk_mult[(cccr >> 5) & 0x03];
	69	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
	70
	71	L = l * BASE_CLK;
	72	M = m * L;
	73	N = n2 * M / 2;
	74
	75	if(info)
	76	{
	77	L += 5000;
	78	printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
	79	L / 1000000, (L % 1000000) / 10000, l );
	80	M += 5000;
	81	printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
	82	M / 1000000, (M % 1000000) / 10000, m );
	83	N += 5000;
	84	printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
	85	N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
	86	(turbo & 1) ? "" : "in" );
	87	}
	88
	89	return (turbo & 1) ? (N/1000) : (M/1000);
	90	}
	91
1da177e4 LT	92	/*
	93	* Return the current memory clock frequency in units of 10kHz
	94	*/
15a40333	95	unsigned int pxa25x_get_memclk_frequency_10khz(void)
1da177e4 LT	96	{
	97	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
	98	}
	99
a6dba20c RK	100	static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
	101	{
	102	return pxa25x_get_memclk_frequency_10khz() * 10000;
	103	}
	104
	105	static const struct clkops clk_pxa25x_lcd_ops = {
	106	.enable = clk_cken_enable,
	107	.disable = clk_cken_disable,
	108	.getrate = clk_pxa25x_lcd_getrate,
	109	};
	110
	111	/*
	112	* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
	113	* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
	114	* 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
	115	*/
e01dbdb4 DES	116	static struct clk pxa25x_hwuart_clk =
	117	INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
	118	;
	119
bdb08cb2 RK	120	/*
	121	* PXA 2xx clock declarations. Order is important (see aliases below)
	122	* Please be careful not to disrupt the ordering.
	123	*/
a6dba20c RK	124	static struct clk pxa25x_clks[] = {
	125	INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
	126	INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
	127	INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
435b6e94	128	INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
a6dba20c RK	129	INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
	130	INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
	131	INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
d8e0db11	132
	133	INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev),
	134	INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
	135	INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
	136
27b98a67 MB	137	INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
27b98a67 MB	138
a6dba20c RK	139	/*
	140	INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
	141	INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
a6dba20c	142	INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
a6dba20c	143	*/
435b6e94	144	INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
a6dba20c RK	145	};
a6dba20c RK	146
bdb08cb2 RK	147	static struct clk gpio7_clk = INIT_CKOTHER("GPIO7_CK", &pxa25x_clks[4], NULL);
bdb08cb2 RK	148
a8fa3f0c	149	#ifdef CONFIG_PM
8775420d	150
711be5cc EM	151	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
	152	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
	153
711be5cc EM	154	/*
	155	* List of global PXA peripheral registers to preserve.
	156	* More ones like CP and general purpose register values are preserved
	157	* with the stack pointer in sleep.S.
	158	*/
649de51b	159	enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
711be5cc EM	160
	161	SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
	162	SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
	163	SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
	164
	165	SLEEP_SAVE_PSTR,
	166
711be5cc EM	167	SLEEP_SAVE_CKEN,
711be5cc EM	168
649de51b	169	SLEEP_SAVE_COUNT
711be5cc EM	170	};
	171
	172
	173	static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
	174	{
711be5cc EM	175	SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
	176
	177	SAVE(GAFR0_L); SAVE(GAFR0_U);
	178	SAVE(GAFR1_L); SAVE(GAFR1_U);
	179	SAVE(GAFR2_L); SAVE(GAFR2_U);
	180
711be5cc EM	181	SAVE(CKEN);
711be5cc EM	182	SAVE(PSTR);
56b11288 RP	183
	184	/* Clear GPIO transition detect bits */
	185	GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
711be5cc EM	186	}
	187
	188	static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
	189	{
56b11288 RP	190	/* ensure not to come back here if it wasn't intended */
	191	PSPR = 0;
	192
711be5cc	193	/* restore registers */
711be5cc EM	194	RESTORE(GAFR0_L); RESTORE(GAFR0_U);
	195	RESTORE(GAFR1_L); RESTORE(GAFR1_U);
	196	RESTORE(GAFR2_L); RESTORE(GAFR2_U);
711be5cc EM	197	RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
711be5cc EM	198
56b11288 RP	199	PSSR = PSSR_RDH \| PSSR_PH;
56b11288 RP	200
711be5cc	201	RESTORE(CKEN);
711be5cc EM	202	RESTORE(PSTR);
	203	}
	204
	205	static void pxa25x_cpu_pm_enter(suspend_state_t state)
8775420d	206	{
dc38e2ad RK	207	/* Clear reset status */
	208	RCSR = RCSR_HWR \| RCSR_WDR \| RCSR_SMR \| RCSR_GPR;
	209
8775420d TP	210	switch (state) {
	211	case PM_SUSPEND_MEM:
	212	/* set resume return address */
	213	PSPR = virt_to_phys(pxa_cpu_resume);
b750a093	214	pxa25x_cpu_suspend(PWRMODE_SLEEP);
8775420d TP	215	break;
	216	}
	217	}
a8fa3f0c	218
711be5cc	219	static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
649de51b	220	.save_count = SLEEP_SAVE_COUNT,
26398a70	221	.valid = suspend_valid_only_mem,
711be5cc EM	222	.save = pxa25x_cpu_pm_save,
	223	.restore = pxa25x_cpu_pm_restore,
	224	.enter = pxa25x_cpu_pm_enter,
e176bb05	225	};
711be5cc EM	226
	227	static void __init pxa25x_init_pm(void)
	228	{
	229	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
	230	}
f79299ca	231	#else
f79299ca	232	static inline void pxa25x_init_pm(void) {}
a8fa3f0c	233	#endif
e176bb05	234
c95530c7	235	/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
	236	*/
	237
	238	static int pxa25x_set_wake(unsigned int irq, unsigned int on)
	239	{
	240	int gpio = IRQ_TO_GPIO(irq);
c0a596d6	241	uint32_t mask = 0;
	242
	243	if (gpio >= 0 && gpio < 85)
	244	return gpio_set_wake(gpio, on);
c95530c7	245
	246	if (irq == IRQ_RTCAlrm) {
	247	mask = PWER_RTC;
	248	goto set_pwer;
	249	}
	250
	251	return -EINVAL;
	252
	253	set_pwer:
	254	if (on)
	255	PWER \|= mask;
	256	else
	257	PWER &=~mask;
	258
	259	return 0;
	260	}
	261
cd49104d EM	262	void __init pxa25x_init_irq(void)
cd49104d EM	263	{
b9e25ace	264	pxa_init_irq(32, pxa25x_set_wake);
b9e25ace	265	pxa_init_gpio(85, pxa25x_set_wake);
cd49104d EM	266	}
cd49104d EM	267
34f3231f	268	static struct platform_device *pxa25x_devices[] __initdata = {
e09d02e1	269	&pxa_device_udc,
e09d02e1 EM	270	&pxa_device_ffuart,
	271	&pxa_device_btuart,
	272	&pxa_device_stuart,
e09d02e1	273	&pxa_device_i2s,
e09d02e1	274	&pxa_device_rtc,
d8e0db11	275	&pxa25x_device_ssp,
	276	&pxa25x_device_nssp,
	277	&pxa25x_device_assp,
34f3231f RK	278	};
34f3231f RK	279
c0165504	280	static struct sys_device pxa25x_sysdev[] = {
	281	{
	282	.cls = &pxa_irq_sysclass,
16dfdbf0	283	}, {
16dfdbf0	284	.cls = &pxa_gpio_sysclass,
c0165504	285	},
	286	};
	287
e176bb05 RK	288	static int __init pxa25x_init(void)
e176bb05 RK	289	{
c0165504	290	int i, ret = 0;
f53f066c	291
e01dbdb4 DES	292	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
	293	if (cpu_is_pxa25x())
	294	clks_register(&pxa25x_hwuart_clk, 1);
	295
e176bb05	296	if (cpu_is_pxa21x() \|\| cpu_is_pxa25x()) {
a6dba20c RK	297	clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
a6dba20c RK	298
f53f066c EM	299	if ((ret = pxa_init_dma(16)))
f53f066c EM	300	return ret;
f79299ca	301
711be5cc	302	pxa25x_init_pm();
f79299ca	303
c0165504	304	for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
	305	ret = sysdev_register(&pxa25x_sysdev[i]);
	306	if (ret)
	307	pr_err("failed to register sysdev[%d]\n", i);
	308	}
	309
34f3231f RK	310	ret = platform_add_devices(pxa25x_devices,
34f3231f RK	311	ARRAY_SIZE(pxa25x_devices));
c0165504	312	if (ret)
c0165504	313	return ret;
e176bb05	314	}
c0165504	315
34f3231f RK	316	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
34f3231f RK	317	if (cpu_is_pxa25x())
e09d02e1	318	ret = platform_device_register(&pxa_device_hwuart);
34f3231f	319
bdb08cb2 RK	320	clks_register(&gpio7_clk, 1);
bdb08cb2 RK	321
34f3231f	322	return ret;
e176bb05 RK	323	}
e176bb05 RK	324
1c104e0e	325	postcore_initcall(pxa25x_init);