projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 2781681e RK |
1 | /* |
| 2 | * arch/arm/mach-pnx4008/include/mach/timex.h | |
| 3 | * | |
| 4 | * PNX4008 timers header file | |
| 5 | * | |
| 6 | * Author: Dmitry Chigirev <source@mvista.com> | |
| 7 | * | |
| 8 | * 2005 (c) MontaVista Software, Inc. This file is licensed under | |
| 9 | * the terms of the GNU General Public License version 2. This program | |
| 10 | * is licensed "as is" without any warranty of any kind, whether express | |
| 11 | * or implied. | |
| 12 | */ | |
| 13 | #ifndef PNX_TIME_H | |
| 14 | #define PNX_TIME_H | |
| 15 | ||
| 16 | #include <linux/io.h> | |
| 17 | #include <mach/hardware.h> | |
| 18 | ||
| 19 | #define TICKS2USECS(x) (x) | |
| 20 | ||
| 21 | /* MilliSecond Timer - Chapter 21 Page 202 */ | |
| 22 | ||
| 23 | #define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0)) | |
| 24 | #define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4)) | |
| 25 | #define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8)) | |
| 26 | #define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14)) | |
| 27 | #define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18)) | |
| 28 | #define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c)) | |
| 29 | ||
| 30 | /* High Speed Timer - Chpater 22, Page 205 */ | |
| 31 | ||
| 32 | #define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0)) | |
| 33 | #define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4)) | |
| 34 | #define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8)) | |
| 35 | #define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC)) | |
| 36 | #define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10)) | |
| 37 | #define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14)) | |
| 38 | #define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18)) | |
| 39 | #define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c)) | |
| 40 | #define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20)) | |
| 41 | #define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28)) | |
| 42 | #define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C)) | |
| 43 | #define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30)) | |
| 44 | ||
| 45 | /* IMPORTANT: both timers are UPCOUNTING */ | |
| 46 | ||
| 47 | /* xSTIM_MCTRL bit definitions */ | |
| 48 | #define MR0_INT 1 | |
| 49 | #define RESET_COUNT0 (1<<1) | |
| 50 | #define STOP_COUNT0 (1<<2) | |
| 51 | #define MR1_INT (1<<3) | |
| 52 | #define RESET_COUNT1 (1<<4) | |
| 53 | #define STOP_COUNT1 (1<<5) | |
| 54 | #define MR2_INT (1<<6) | |
| 55 | #define RESET_COUNT2 (1<<7) | |
| 56 | #define STOP_COUNT2 (1<<8) | |
| 57 | ||
| 58 | /* xSTIM_CTRL bit definitions */ | |
| 59 | #define COUNT_ENAB 1 | |
| 60 | #define RESET_COUNT (1<<1) | |
| 61 | #define DEBUG_EN (1<<2) | |
| 62 | ||
| 63 | /* xSTIM_INT bit definitions */ | |
| 64 | #define MATCH0_INT 1 | |
| 65 | #define MATCH1_INT (1<<1) | |
| 66 | #define MATCH2_INT (1<<2) | |
| 67 | #define RTC_TICK0 (1<<4) | |
| 68 | #define RTC_TICK1 (1<<5) | |
| 69 | ||
| 70 | #endif |