[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-orion5x / pci.c

/*
 * arch/arm/mach-orion5x/pci.c
 *
 * PCI and PCIe functions for Marvell Orion System On Chip
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include "common.h"

/*****************************************************************************
 * Orion has one PCIe controller and one PCI controller.
 *
 * Note1: The local PCIe bus number is '0'. The local PCI bus number
 * follows the scanned PCIe bridged busses, if any.
 *
 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
 * device bus, Orion registers, etc. However this code only enable the
 * access to DDR banks.
 ****************************************************************************/


/*****************************************************************************
 * PCIe controller
 ****************************************************************************/
#define PCIE_BASE	((void __iomem *)ORION5X_PCIE_VIRT_BASE)

void __init orion5x_pcie_id(u32 *dev, u32 *rev)
{
	*dev = orion_pcie_dev_id(PCIE_BASE);
	*rev = orion_pcie_rev(PCIE_BASE);
}

static int pcie_valid_config(int bus, int dev)
{
	/*
	 * Don't go out when trying to access --
	 * 1. nonexisting device on local bus
	 * 2. where there's no device connected (no link)
	 */
	if (bus == 0 && dev == 0)
		return 1;

	if (!orion_pcie_link_up(PCIE_BASE))
		return 0;

	if (bus == 0 && dev != 1)
		return 0;

	return 1;
}


/*
 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion5x_pcie_lock);

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&orion5x_pcie_lock, flags);
	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);

	return ret;
}

static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
			   int where, int size, u32 *val)
{
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	/*
	 * We only support access to the non-extended configuration
	 * space when using the WA access method (or we would have to
	 * sacrifice 256M of CPU virtual address space.)
	 */
	if (where >= 0x100) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
				    bus, devfn, where, size, val);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	unsigned long flags;
	int ret;

	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&orion5x_pcie_lock, flags);
	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};


static int __init pcie_setup(struct pci_sys_data *sys)
{
	struct resource *res;
	int dev;

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);

	/*
	 * Check whether to apply Orion-1/Orion-NAS PCIe config
	 * read transaction workaround.
	 */
	dev = orion_pcie_dev_id(PCIE_BASE);
	if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
		printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
				   "read transaction workaround\n");
		orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
					  ORION5X_PCIE_WA_SIZE);
		pcie_ops.read = pcie_rd_conf_wa;
	}

	/*
	 * Request resources.
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
		panic("pcie_setup unable to alloc resources");

	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCIe I/O Space";
	res[0].flags = IORESOURCE_IO;
	res[0].start = ORION5X_PCIE_IO_BUS_BASE;
	res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCIe IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCIe Memory Space";
	res[1].flags = IORESOURCE_MEM;
	res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCIe Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}

/*****************************************************************************
 * PCI controller
 ****************************************************************************/
#define PCI_MODE		ORION5X_PCI_REG(0xd00)
#define PCI_CMD			ORION5X_PCI_REG(0xc00)
#define PCI_P2P_CONF		ORION5X_PCI_REG(0x1d14)
#define PCI_CONF_ADDR		ORION5X_PCI_REG(0xc78)
#define PCI_CONF_DATA		ORION5X_PCI_REG(0xc7c)

/*
 * PCI_MODE bits
 */
#define PCI_MODE_64BIT			(1 << 2)
#define PCI_MODE_PCIX			((1 << 4) | (1 << 5))

/*
 * PCI_CMD bits
 */
#define PCI_CMD_HOST_REORDER		(1 << 29)

/*
 * PCI_P2P_CONF bits
 */
#define PCI_P2P_BUS_OFFS		16
#define PCI_P2P_BUS_MASK		(0xff << PCI_P2P_BUS_OFFS)
#define PCI_P2P_DEV_OFFS		24
#define PCI_P2P_DEV_MASK		(0x1f << PCI_P2P_DEV_OFFS)

/*
 * PCI_CONF_ADDR bits
 */
#define PCI_CONF_REG(reg)		((reg) & 0xfc)
#define PCI_CONF_FUNC(func)		(((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev)		(((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus)		(((bus) & 0xff) << 16)
#define PCI_CONF_ADDR_EN		(1 << 31)

/*
 * Internal configuration space
 */
#define PCI_CONF_FUNC_STAT_CMD		0
#define PCI_CONF_REG_STAT_CMD		4
#define PCIX_STAT			0x64
#define PCIX_STAT_BUS_OFFS		8
#define PCIX_STAT_BUS_MASK		(0xff << PCIX_STAT_BUS_OFFS)

/*
 * PCI Address Decode Windows registers
 */
#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
				 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
				 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
				 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
#define PCI_BAR_REMAP_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
				 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
				 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
				 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
#define PCI_BAR_ENABLE		ORION5X_PCI_REG(0xc3c)
#define PCI_ADDR_DECODE_CTRL	ORION5X_PCI_REG(0xd3c)

/*
 * PCI configuration helpers for BAR settings
 */
#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)

/*
 * PCI config cycles are done by programming the PCI_CONF_ADDR register
 * and then reading the PCI_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion5x_pci_lock);

static int orion5x_pci_cardbus_mode;

static int orion5x_pci_local_bus_nr(void)
{
	u32 conf = readl(PCI_P2P_CONF);
	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
}

static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
					u32 where, u32 size, u32 *val)
{
	unsigned long flags;
	spin_lock_irqsave(&orion5x_pci_lock, flags);

	writel(PCI_CONF_BUS(bus) |
		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);

	*val = readl(PCI_CONF_DATA);

	if (size == 1)
		*val = (*val >> (8*(where & 0x3))) & 0xff;
	else if (size == 2)
		*val = (*val >> (8*(where & 0x3))) & 0xffff;

	spin_unlock_irqrestore(&orion5x_pci_lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
					u32 where, u32 size, u32 val)
{
	unsigned long flags;
	int ret = PCIBIOS_SUCCESSFUL;

	spin_lock_irqsave(&orion5x_pci_lock, flags);

	writel(PCI_CONF_BUS(bus) |
		PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
		PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);

	if (size == 4) {
		__raw_writel(val, PCI_CONF_DATA);
	} else if (size == 2) {
		__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	} else if (size == 1) {
		__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	} else {
		ret = PCIBIOS_BAD_REGISTER_NUMBER;
	}

	spin_unlock_irqrestore(&orion5x_pci_lock, flags);

	return ret;
}

static int orion5x_pci_valid_config(int bus, u32 devfn)
{
	if (bus == orion5x_pci_local_bus_nr()) {
		/*
		 * Don't go out for local device
		 */
		if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
			return 0;

		/*
		 * When the PCI signals are directly connected to a
		 * Cardbus slot, ignore all but device IDs 0 and 1.
		 */
		if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
			return 0;
	}

	return 1;
}

static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 *val)
{
	if (!orion5x_pci_valid_config(bus->number, devfn)) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 val)
{
	if (!orion5x_pci_valid_config(bus->number, devfn))
		return PCIBIOS_DEVICE_NOT_FOUND;

	return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

static struct pci_ops pci_ops = {
	.read = orion5x_pci_rd_conf,
	.write = orion5x_pci_wr_conf,
};

static void __init orion5x_pci_set_bus_nr(int nr)
{
	u32 p2p = readl(PCI_P2P_CONF);

	if (readl(PCI_MODE) & PCI_MODE_PCIX) {
		/*
		 * PCI-X mode
		 */
		u32 pcix_status, bus, dev;
		bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
		dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
		orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
		pcix_status &= ~PCIX_STAT_BUS_MASK;
		pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
		orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
	} else {
		/*
		 * PCI Conventional mode
		 */
		p2p &= ~PCI_P2P_BUS_MASK;
		p2p |= (nr << PCI_P2P_BUS_OFFS);
		writel(p2p, PCI_P2P_CONF);
	}
}

static void __init orion5x_pci_master_slave_enable(void)
{
	int bus_nr, func, reg;
	u32 val;

	bus_nr = orion5x_pci_local_bus_nr();
	func = PCI_CONF_FUNC_STAT_CMD;
	reg = PCI_CONF_REG_STAT_CMD;
	orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
	val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
}

static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
{
	u32 win_enable;
	int bus;
	int i;

	/*
	 * First, disable windows.
	 */
	win_enable = 0xffffffff;
	writel(win_enable, PCI_BAR_ENABLE);

	/*
	 * Setup windows for DDR banks.
	 */
	bus = orion5x_pci_local_bus_nr();

	for (i = 0; i < dram->num_cs; i++) {
		struct mbus_dram_window *cs = dram->cs + i;
		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
		u32 reg;
		u32 val;

		/*
		 * Write DRAM bank base address register.
		 */
		reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
		orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
		val = (cs->base & 0xfffff000) | (val & 0xfff);
		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);

		/*
		 * Write DRAM bank size register.
		 */
		reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
		writel((cs->size - 1) & 0xfffff000,
			PCI_BAR_SIZE_DDR_CS(cs->cs_index));
		writel(cs->base & 0xfffff000,
			PCI_BAR_REMAP_DDR_CS(cs->cs_index));

		/*
		 * Enable decode window for this chip select.
		 */
		win_enable &= ~(1 << cs->cs_index);
	}

	/*
	 * Re-enable decode windows.
	 */
	writel(win_enable, PCI_BAR_ENABLE);

	/*
	 * Disable automatic update of address remaping when writing to BARs.
	 */
	orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
}

static int __init pci_setup(struct pci_sys_data *sys)
{
	struct resource *res;

	/*
	 * Point PCI unit MBUS decode windows to DRAM space.
	 */
	orion5x_setup_pci_wins(&orion5x_mbus_dram_info);

	/*
	 * Master + Slave enable
	 */
	orion5x_pci_master_slave_enable();

	/*
	 * Force ordering
	 */
	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);

	/*
	 * Request resources
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
		panic("pci_setup unable to alloc resources");

	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCI I/O Space";
	res[0].flags = IORESOURCE_IO;
	res[0].start = ORION5X_PCI_IO_BUS_BASE;
	res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCI IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCI Memory Space";
	res[1].flags = IORESOURCE_MEM;
	res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCI Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}


/*****************************************************************************
 * General PCIe + PCI
 ****************************************************************************/
static void __devinit rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static int orion5x_pci_disabled __initdata;

void __init orion5x_pci_disable(void)
{
	orion5x_pci_disabled = 1;
}

void __init orion5x_pci_set_cardbus_mode(void)
{
	orion5x_pci_cardbus_mode = 1;
}

int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
{
	int ret = 0;

	if (nr == 0) {
		orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
		ret = pcie_setup(sys);
	} else if (nr == 1 && !orion5x_pci_disabled) {
		orion5x_pci_set_bus_nr(sys->busnr);
		ret = pci_setup(sys);
	}

	return ret;
}

struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
{
	struct pci_bus *bus;

	if (nr == 0) {
		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	} else if (nr == 1 && !orion5x_pci_disabled) {
		bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
	} else {
		bus = NULL;
		BUG();
	}

	return bus;
}

int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	int bus = dev->bus->number;

	/*
	 * PCIe endpoint?
	 */
	if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
		return IRQ_ORION5X_PCIE0_INT;

	return -1;
}
Commit	Line	Data
038ee083	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/pci.c
038ee083	3	*
159ffb3a	4	* PCI and PCIe functions for Marvell Orion System On Chip
038ee083 TP	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
038ee083 TP	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
1f2223b1	15	#include <linux/mbus.h>
ff89c462	16	#include <asm/irq.h>
038ee083	17	#include <asm/mach/pci.h>
6f088f1d	18	#include <plat/pcie.h>
038ee083 TP	19	#include "common.h"
	20
	21	/*****************************************************************************
159ffb3a	22	* Orion has one PCIe controller and one PCI controller.
038ee083	23	*
159ffb3a LB	24	* Note1: The local PCIe bus number is '0'. The local PCI bus number
159ffb3a LB	25	* follows the scanned PCIe bridged busses, if any.
038ee083	26	*
159ffb3a	27	* Note2: It is possible for PCI/PCIe agents to access many subsystem's
038ee083 TP	28	* space, by configuring BARs and Address Decode Windows, e.g. flashes on
	29	* device bus, Orion registers, etc. However this code only enable the
	30	* access to DDR banks.
	31	****************************************************************************/
	32
	33
	34	/*****************************************************************************
159ffb3a	35	* PCIe controller
038ee083	36	****************************************************************************/
9dd0b194	37	#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
038ee083	38
9dd0b194	39	void __init orion5x_pcie_id(u32 dev, u32 rev)
038ee083	40	{
abc0197d LB	41	*dev = orion_pcie_dev_id(PCIE_BASE);
abc0197d LB	42	*rev = orion_pcie_rev(PCIE_BASE);
038ee083 TP	43	}
038ee083 TP	44
abc0197d	45	static int pcie_valid_config(int bus, int dev)
038ee083 TP	46	{
	47	/*
	48	* Don't go out when trying to access --
d50c60a8	49	* 1. nonexisting device on local bus
038ee083	50	* 2. where there's no device connected (no link)
038ee083	51	*/
d50c60a8 LB	52	if (bus == 0 && dev == 0)
d50c60a8 LB	53	return 1;
038ee083	54
abc0197d	55	if (!orion_pcie_link_up(PCIE_BASE))
038ee083 TP	56	return 0;
038ee083 TP	57
d50c60a8 LB	58	if (bus == 0 && dev != 1)
	59	return 0;
	60
038ee083 TP	61	return 1;
	62	}
	63
abc0197d LB	64
abc0197d LB	65	/*
159ffb3a	66	* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
abc0197d LB	67	* and then reading the PCIE_CONF_DATA register. Need to make sure these
	68	* transactions are atomic.
	69	*/
9dd0b194	70	static DEFINE_SPINLOCK(orion5x_pcie_lock);
abc0197d LB	71
	72	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	73	int size, u32 *val)
038ee083 TP	74	{
038ee083 TP	75	unsigned long flags;
abc0197d	76	int ret;
038ee083	77
abc0197d	78	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
038ee083 TP	79	*val = 0xffffffff;
	80	return PCIBIOS_DEVICE_NOT_FOUND;
	81	}
	82
9dd0b194	83	spin_lock_irqsave(&orion5x_pcie_lock, flags);
abc0197d	84	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
9dd0b194	85	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
038ee083	86
abc0197d LB	87	return ret;
abc0197d LB	88	}
038ee083	89
abc0197d LB	90	static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
	91	int where, int size, u32 *val)
	92	{
	93	int ret;
038ee083	94
abc0197d LB	95	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
	96	*val = 0xffffffff;
	97	return PCIBIOS_DEVICE_NOT_FOUND;
	98	}
038ee083	99
abc0197d LB	100	/*
	101	* We only support access to the non-extended configuration
	102	* space when using the WA access method (or we would have to
	103	* sacrifice 256M of CPU virtual address space.)
	104	*/
	105	if (where >= 0x100) {
	106	*val = 0xffffffff;
	107	return PCIBIOS_DEVICE_NOT_FOUND;
	108	}
038ee083	109
9dd0b194	110	ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
abc0197d	111	bus, devfn, where, size, val);
038ee083	112
abc0197d LB	113	return ret;
abc0197d LB	114	}
038ee083	115
abc0197d LB	116	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
abc0197d LB	117	int where, int size, u32 val)
038ee083 TP	118	{
	119	unsigned long flags;
	120	int ret;
	121
abc0197d	122	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
038ee083 TP	123	return PCIBIOS_DEVICE_NOT_FOUND;
038ee083 TP	124
9dd0b194	125	spin_lock_irqsave(&orion5x_pcie_lock, flags);
abc0197d	126	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
9dd0b194	127	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
038ee083 TP	128
	129	return ret;
	130	}
	131
159ffb3a	132	static struct pci_ops pcie_ops = {
abc0197d LB	133	.read = pcie_rd_conf,
abc0197d LB	134	.write = pcie_wr_conf,
038ee083 TP	135	};
	136
	137
a9984270	138	static int __init pcie_setup(struct pci_sys_data *sys)
038ee083 TP	139	{
038ee083 TP	140	struct resource *res;
abc0197d	141	int dev;
038ee083	142
1f2223b1	143	/*
abc0197d	144	* Generic PCIe unit setup.
038ee083	145	*/
9dd0b194	146	orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
038ee083 TP	147
038ee083 TP	148	/*
abc0197d LB	149	* Check whether to apply Orion-1/Orion-NAS PCIe config
abc0197d LB	150	* read transaction workaround.
038ee083	151	*/
abc0197d LB	152	dev = orion_pcie_dev_id(PCIE_BASE);
	153	if (dev == MV88F5181_DEV_ID \|\| dev == MV88F5182_DEV_ID) {
	154	printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
	155	"read transaction workaround\n");
386a048a LB	156	orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
386a048a LB	157	ORION5X_PCIE_WA_SIZE);
abc0197d LB	158	pcie_ops.read = pcie_rd_conf_wa;
abc0197d LB	159	}
038ee083 TP	160
038ee083 TP	161	/*
abc0197d	162	* Request resources.
038ee083 TP	163	*/
	164	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	165	if (!res)
abc0197d	166	panic("pcie_setup unable to alloc resources");
038ee083 TP	167
	168	/*
	169	* IORESOURCE_IO
	170	*/
159ffb3a	171	res[0].name = "PCIe I/O Space";
038ee083	172	res[0].flags = IORESOURCE_IO;
9dd0b194 LB	173	res[0].start = ORION5X_PCIE_IO_BUS_BASE;
9dd0b194 LB	174	res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
038ee083	175	if (request_resource(&ioport_resource, &res[0]))
159ffb3a	176	panic("Request PCIe IO resource failed\n");
038ee083 TP	177	sys->resource[0] = &res[0];
	178
	179	/*
	180	* IORESOURCE_MEM
	181	*/
159ffb3a	182	res[1].name = "PCIe Memory Space";
038ee083	183	res[1].flags = IORESOURCE_MEM;
9dd0b194 LB	184	res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
9dd0b194 LB	185	res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
038ee083	186	if (request_resource(&iomem_resource, &res[1]))
159ffb3a	187	panic("Request PCIe Memory resource failed\n");
038ee083 TP	188	sys->resource[1] = &res[1];
	189
	190	sys->resource[2] = NULL;
	191	sys->io_offset = 0;
	192
	193	return 1;
	194	}
	195
	196	/*****************************************************************************
	197	* PCI controller
	198	****************************************************************************/
9dd0b194 LB	199	#define PCI_MODE ORION5X_PCI_REG(0xd00)
	200	#define PCI_CMD ORION5X_PCI_REG(0xc00)
	201	#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
	202	#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
	203	#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
038ee083 TP	204
	205	/*
	206	* PCI_MODE bits
	207	*/
	208	#define PCI_MODE_64BIT (1 << 2)
	209	#define PCI_MODE_PCIX ((1 << 4) \| (1 << 5))
	210
	211	/*
	212	* PCI_CMD bits
	213	*/
	214	#define PCI_CMD_HOST_REORDER (1 << 29)
	215
	216	/*
	217	* PCI_P2P_CONF bits
	218	*/
	219	#define PCI_P2P_BUS_OFFS 16
	220	#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
	221	#define PCI_P2P_DEV_OFFS 24
	222	#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
	223
	224	/*
	225	* PCI_CONF_ADDR bits
	226	*/
	227	#define PCI_CONF_REG(reg) ((reg) & 0xfc)
	228	#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
	229	#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
	230	#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
	231	#define PCI_CONF_ADDR_EN (1 << 31)
	232
	233	/*
	234	* Internal configuration space
	235	*/
	236	#define PCI_CONF_FUNC_STAT_CMD 0
	237	#define PCI_CONF_REG_STAT_CMD 4
	238	#define PCIX_STAT 0x64
	239	#define PCIX_STAT_BUS_OFFS 8
	240	#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
	241
1f2223b1 LB	242	/*
	243	* PCI Address Decode Windows registers
	244	*/
9dd0b194	245	#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
e7068ad3 LB	246	((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
	247	((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
	248	((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
	249	#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
	250	((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
	251	((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
	252	((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
9dd0b194 LB	253	#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
9dd0b194 LB	254	#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
1f2223b1 LB	255
	256	/*
	257	* PCI configuration helpers for BAR settings
	258	*/
	259	#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
	260	#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
	261	#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
	262
038ee083 TP	263	/*
	264	* PCI config cycles are done by programming the PCI_CONF_ADDR register
	265	* and then reading the PCI_CONF_DATA register. Need to make sure these
	266	* transactions are atomic.
	267	*/
9dd0b194	268	static DEFINE_SPINLOCK(orion5x_pci_lock);
038ee083	269
da01bba3 LB	270	static int orion5x_pci_cardbus_mode;
da01bba3 LB	271
92b913b0	272	static int orion5x_pci_local_bus_nr(void)
038ee083	273	{
79e90dd5	274	u32 conf = readl(PCI_P2P_CONF);
038ee083 TP	275	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
	276	}
	277
9dd0b194	278	static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
038ee083 TP	279	u32 where, u32 size, u32 *val)
	280	{
	281	unsigned long flags;
9dd0b194	282	spin_lock_irqsave(&orion5x_pci_lock, flags);
038ee083	283
79e90dd5 LB	284	writel(PCI_CONF_BUS(bus) \|
	285	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	286	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
038ee083	287
79e90dd5	288	*val = readl(PCI_CONF_DATA);
038ee083 TP	289
	290	if (size == 1)
	291	val = (val >> (8*(where & 0x3))) & 0xff;
	292	else if (size == 2)
	293	val = (val >> (8*(where & 0x3))) & 0xffff;
	294
9dd0b194	295	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
038ee083 TP	296
	297	return PCIBIOS_SUCCESSFUL;
	298	}
	299
9dd0b194	300	static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
038ee083 TP	301	u32 where, u32 size, u32 val)
	302	{
	303	unsigned long flags;
	304	int ret = PCIBIOS_SUCCESSFUL;
	305
9dd0b194	306	spin_lock_irqsave(&orion5x_pci_lock, flags);
038ee083	307
79e90dd5 LB	308	writel(PCI_CONF_BUS(bus) \|
	309	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	310	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
038ee083 TP	311
	312	if (size == 4) {
	313	__raw_writel(val, PCI_CONF_DATA);
	314	} else if (size == 2) {
	315	__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	316	} else if (size == 1) {
	317	__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	318	} else {
	319	ret = PCIBIOS_BAD_REGISTER_NUMBER;
	320	}
	321
9dd0b194	322	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
038ee083 TP	323
	324	return ret;
	325	}
	326
da01bba3 LB	327	static int orion5x_pci_valid_config(int bus, u32 devfn)
	328	{
	329	if (bus == orion5x_pci_local_bus_nr()) {
	330	/*
	331	* Don't go out for local device
	332	*/
	333	if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
	334	return 0;
	335
	336	/*
	337	* When the PCI signals are directly connected to a
	338	* Cardbus slot, ignore all but device IDs 0 and 1.
	339	*/
	340	if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
	341	return 0;
	342	}
	343
	344	return 1;
	345	}
	346
9dd0b194	347	static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
038ee083 TP	348	int where, int size, u32 *val)
038ee083 TP	349	{
da01bba3	350	if (!orion5x_pci_valid_config(bus->number, devfn)) {
038ee083 TP	351	*val = 0xffffffff;
	352	return PCIBIOS_DEVICE_NOT_FOUND;
	353	}
	354
9dd0b194	355	return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
038ee083 TP	356	PCI_FUNC(devfn), where, size, val);
	357	}
	358
9dd0b194	359	static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
038ee083 TP	360	int where, int size, u32 val)
038ee083 TP	361	{
da01bba3	362	if (!orion5x_pci_valid_config(bus->number, devfn))
038ee083 TP	363	return PCIBIOS_DEVICE_NOT_FOUND;
038ee083 TP	364
9dd0b194	365	return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
038ee083 TP	366	PCI_FUNC(devfn), where, size, val);
	367	}
	368
159ffb3a	369	static struct pci_ops pci_ops = {
9dd0b194 LB	370	.read = orion5x_pci_rd_conf,
9dd0b194 LB	371	.write = orion5x_pci_wr_conf,
038ee083 TP	372	};
038ee083 TP	373
9dd0b194	374	static void __init orion5x_pci_set_bus_nr(int nr)
038ee083	375	{
79e90dd5	376	u32 p2p = readl(PCI_P2P_CONF);
038ee083	377
79e90dd5	378	if (readl(PCI_MODE) & PCI_MODE_PCIX) {
038ee083 TP	379	/*
	380	* PCI-X mode
	381	*/
	382	u32 pcix_status, bus, dev;
	383	bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
	384	dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
9dd0b194	385	orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
038ee083 TP	386	pcix_status &= ~PCIX_STAT_BUS_MASK;
038ee083 TP	387	pcix_status \|= (nr << PCIX_STAT_BUS_OFFS);
9dd0b194	388	orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
038ee083 TP	389	} else {
	390	/*
	391	* PCI Conventional mode
	392	*/
	393	p2p &= ~PCI_P2P_BUS_MASK;
	394	p2p \|= (nr << PCI_P2P_BUS_OFFS);
79e90dd5	395	writel(p2p, PCI_P2P_CONF);
038ee083 TP	396	}
	397	}
	398
9dd0b194	399	static void __init orion5x_pci_master_slave_enable(void)
038ee083	400	{
d50c60a8	401	int bus_nr, func, reg;
abc0197d	402	u32 val;
038ee083	403
9dd0b194	404	bus_nr = orion5x_pci_local_bus_nr();
038ee083 TP	405	func = PCI_CONF_FUNC_STAT_CMD;
038ee083 TP	406	reg = PCI_CONF_REG_STAT_CMD;
9dd0b194	407	orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
038ee083	408	val \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
9dd0b194	409	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val \| 0x7);
038ee083 TP	410	}
038ee083 TP	411
9dd0b194	412	static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
1f2223b1 LB	413	{
1f2223b1 LB	414	u32 win_enable;
abc0197d	415	int bus;
1f2223b1 LB	416	int i;
	417
	418	/*
	419	* First, disable windows.
	420	*/
	421	win_enable = 0xffffffff;
79e90dd5	422	writel(win_enable, PCI_BAR_ENABLE);
1f2223b1 LB	423
	424	/*
	425	* Setup windows for DDR banks.
	426	*/
9dd0b194	427	bus = orion5x_pci_local_bus_nr();
1f2223b1 LB	428
	429	for (i = 0; i < dram->num_cs; i++) {
	430	struct mbus_dram_window *cs = dram->cs + i;
	431	u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
	432	u32 reg;
	433	u32 val;
	434
	435	/*
	436	* Write DRAM bank base address register.
	437	*/
	438	reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
9dd0b194	439	orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
1f2223b1	440	val = (cs->base & 0xfffff000) \| (val & 0xfff);
9dd0b194	441	orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
1f2223b1 LB	442
	443	/*
	444	* Write DRAM bank size register.
	445	*/
	446	reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
9dd0b194	447	orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
79e90dd5 LB	448	writel((cs->size - 1) & 0xfffff000,
	449	PCI_BAR_SIZE_DDR_CS(cs->cs_index));
	450	writel(cs->base & 0xfffff000,
	451	PCI_BAR_REMAP_DDR_CS(cs->cs_index));
1f2223b1 LB	452
	453	/*
	454	* Enable decode window for this chip select.
	455	*/
	456	win_enable &= ~(1 << cs->cs_index);
	457	}
	458
	459	/*
	460	* Re-enable decode windows.
	461	*/
79e90dd5	462	writel(win_enable, PCI_BAR_ENABLE);
1f2223b1 LB	463
	464	/*
	465	* Disable automatic update of address remaping when writing to BARs.
	466	*/
9dd0b194	467	orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
1f2223b1 LB	468	}
1f2223b1 LB	469
a9984270	470	static int __init pci_setup(struct pci_sys_data *sys)
038ee083 TP	471	{
	472	struct resource *res;
	473
1f2223b1 LB	474	/*
	475	* Point PCI unit MBUS decode windows to DRAM space.
	476	*/
9dd0b194	477	orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
1f2223b1	478
038ee083 TP	479	/*
	480	* Master + Slave enable
	481	*/
9dd0b194	482	orion5x_pci_master_slave_enable();
038ee083 TP	483
	484	/*
	485	* Force ordering
	486	*/
9dd0b194	487	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
038ee083 TP	488
	489	/*
	490	* Request resources
	491	*/
	492	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	493	if (!res)
abc0197d	494	panic("pci_setup unable to alloc resources");
038ee083 TP	495
	496	/*
	497	* IORESOURCE_IO
	498	*/
	499	res[0].name = "PCI I/O Space";
	500	res[0].flags = IORESOURCE_IO;
9dd0b194 LB	501	res[0].start = ORION5X_PCI_IO_BUS_BASE;
9dd0b194 LB	502	res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
038ee083 TP	503	if (request_resource(&ioport_resource, &res[0]))
	504	panic("Request PCI IO resource failed\n");
	505	sys->resource[0] = &res[0];
	506
	507	/*
	508	* IORESOURCE_MEM
	509	*/
	510	res[1].name = "PCI Memory Space";
	511	res[1].flags = IORESOURCE_MEM;
9dd0b194 LB	512	res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
9dd0b194 LB	513	res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
038ee083 TP	514	if (request_resource(&iomem_resource, &res[1]))
	515	panic("Request PCI Memory resource failed\n");
	516	sys->resource[1] = &res[1];
	517
	518	sys->resource[2] = NULL;
	519	sys->io_offset = 0;
	520
	521	return 1;
	522	}
	523
	524
	525	/*****************************************************************************
159ffb3a	526	* General PCIe + PCI
038ee083	527	****************************************************************************/
d50c60a8 LB	528	static void __devinit rc_pci_fixup(struct pci_dev *dev)
	529	{
	530	/*
	531	* Prevent enumeration of root complex.
	532	*/
	533	if (dev->bus->parent == NULL && dev->devfn == 0) {
	534	int i;
	535
	536	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	537	dev->resource[i].start = 0;
	538	dev->resource[i].end = 0;
	539	dev->resource[i].flags = 0;
	540	}
	541	}
	542	}
	543	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
	544
7a6bb262 PA	545	static int orion5x_pci_disabled __initdata;
	546
	547	void __init orion5x_pci_disable(void)
	548	{
	549	orion5x_pci_disabled = 1;
	550	}
	551
da01bba3 LB	552	void __init orion5x_pci_set_cardbus_mode(void)
	553	{
	554	orion5x_pci_cardbus_mode = 1;
	555	}
	556
9dd0b194	557	int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
038ee083 TP	558	{
	559	int ret = 0;
	560
	561	if (nr == 0) {
abc0197d LB	562	orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
abc0197d LB	563	ret = pcie_setup(sys);
7a6bb262	564	} else if (nr == 1 && !orion5x_pci_disabled) {
9dd0b194	565	orion5x_pci_set_bus_nr(sys->busnr);
abc0197d	566	ret = pci_setup(sys);
038ee083 TP	567	}
	568
	569	return ret;
	570	}
	571
9dd0b194	572	struct pci_bus __init orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data sys)
038ee083	573	{
038ee083 TP	574	struct pci_bus *bus;
038ee083 TP	575
038ee083	576	if (nr == 0) {
abc0197d	577	bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
7a6bb262	578	} else if (nr == 1 && !orion5x_pci_disabled) {
abc0197d	579	bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
038ee083	580	} else {
038ee083	581	bus = NULL;
abc0197d	582	BUG();
038ee083 TP	583	}
	584
	585	return bus;
	586	}
92b913b0 LB	587
	588	int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	589	{
	590	int bus = dev->bus->number;
	591
	592	/*
	593	* PCIe endpoint?
	594	*/
7a6bb262	595	if (orion5x_pci_disabled \|\| bus < orion5x_pci_local_bus_nr())
92b913b0 LB	596	return IRQ_ORION5X_PCIE0_INT;
	597
	598	return -1;
	599	}