Commit | Line | Data |
---|---|---|
585cf175 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/common.c |
585cf175 | 3 | * |
9dd0b194 | 4 | * Core functions for Marvell Orion 5x SoCs |
585cf175 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
585cf175 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
ca26f7d3 TP |
15 | #include <linux/platform_device.h> |
16 | #include <linux/serial_8250.h> | |
83b6d822 | 17 | #include <linux/mbus.h> |
144aa3db | 18 | #include <linux/mv643xx_i2c.h> |
15a32632 | 19 | #include <linux/ata_platform.h> |
dcf1cece | 20 | #include <net/dsa.h> |
585cf175 | 21 | #include <asm/page.h> |
be73a347 | 22 | #include <asm/setup.h> |
c67de5b3 | 23 | #include <asm/timex.h> |
be73a347 | 24 | #include <asm/mach/arch.h> |
585cf175 | 25 | #include <asm/mach/map.h> |
2bac1de2 | 26 | #include <asm/mach/time.h> |
4ee1f6b5 | 27 | #include <mach/bridge-regs.h> |
a09e64fb RK |
28 | #include <mach/hardware.h> |
29 | #include <mach/orion5x.h> | |
6f088f1d | 30 | #include <plat/ehci-orion.h> |
1d5a1a6e | 31 | #include <plat/mv_xor.h> |
6f088f1d | 32 | #include <plat/orion_nand.h> |
3b937a7d | 33 | #include <plat/orion_wdt.h> |
6f088f1d | 34 | #include <plat/time.h> |
28a2b450 | 35 | #include <plat/common.h> |
585cf175 TP |
36 | #include "common.h" |
37 | ||
38 | /***************************************************************************** | |
39 | * I/O Address Mapping | |
40 | ****************************************************************************/ | |
9dd0b194 | 41 | static struct map_desc orion5x_io_desc[] __initdata = { |
585cf175 | 42 | { |
9dd0b194 LB |
43 | .virtual = ORION5X_REGS_VIRT_BASE, |
44 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), | |
45 | .length = ORION5X_REGS_SIZE, | |
e7068ad3 LB |
46 | .type = MT_DEVICE, |
47 | }, { | |
9dd0b194 LB |
48 | .virtual = ORION5X_PCIE_IO_VIRT_BASE, |
49 | .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), | |
50 | .length = ORION5X_PCIE_IO_SIZE, | |
e7068ad3 LB |
51 | .type = MT_DEVICE, |
52 | }, { | |
9dd0b194 LB |
53 | .virtual = ORION5X_PCI_IO_VIRT_BASE, |
54 | .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), | |
55 | .length = ORION5X_PCI_IO_SIZE, | |
e7068ad3 LB |
56 | .type = MT_DEVICE, |
57 | }, { | |
9dd0b194 LB |
58 | .virtual = ORION5X_PCIE_WA_VIRT_BASE, |
59 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), | |
60 | .length = ORION5X_PCIE_WA_SIZE, | |
e7068ad3 | 61 | .type = MT_DEVICE, |
585cf175 TP |
62 | }, |
63 | }; | |
64 | ||
9dd0b194 | 65 | void __init orion5x_map_io(void) |
585cf175 | 66 | { |
9dd0b194 | 67 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
585cf175 | 68 | } |
c67de5b3 | 69 | |
044f6c7c | 70 | |
ca26f7d3 | 71 | /***************************************************************************** |
044f6c7c | 72 | * EHCI |
ca26f7d3 | 73 | ****************************************************************************/ |
044f6c7c LB |
74 | static struct orion_ehci_data orion5x_ehci_data = { |
75 | .dram = &orion5x_mbus_dram_info, | |
fb6f5529 | 76 | .phy_version = EHCI_PHY_ORION, |
ca26f7d3 TP |
77 | }; |
78 | ||
5c602551 | 79 | static u64 ehci_dmamask = DMA_BIT_MASK(32); |
ca26f7d3 | 80 | |
ca26f7d3 | 81 | |
044f6c7c LB |
82 | /***************************************************************************** |
83 | * EHCI0 | |
84 | ****************************************************************************/ | |
9dd0b194 | 85 | static struct resource orion5x_ehci0_resources[] = { |
ca26f7d3 | 86 | { |
9dd0b194 | 87 | .start = ORION5X_USB0_PHYS_BASE, |
994cab84 | 88 | .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1, |
ca26f7d3 | 89 | .flags = IORESOURCE_MEM, |
e7068ad3 | 90 | }, { |
9dd0b194 LB |
91 | .start = IRQ_ORION5X_USB0_CTRL, |
92 | .end = IRQ_ORION5X_USB0_CTRL, | |
ca26f7d3 TP |
93 | .flags = IORESOURCE_IRQ, |
94 | }, | |
95 | }; | |
96 | ||
9dd0b194 | 97 | static struct platform_device orion5x_ehci0 = { |
ca26f7d3 TP |
98 | .name = "orion-ehci", |
99 | .id = 0, | |
100 | .dev = { | |
101 | .dma_mask = &ehci_dmamask, | |
5c602551 | 102 | .coherent_dma_mask = DMA_BIT_MASK(32), |
9dd0b194 | 103 | .platform_data = &orion5x_ehci_data, |
ca26f7d3 | 104 | }, |
9dd0b194 LB |
105 | .resource = orion5x_ehci0_resources, |
106 | .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), | |
ca26f7d3 TP |
107 | }; |
108 | ||
044f6c7c LB |
109 | void __init orion5x_ehci0_init(void) |
110 | { | |
111 | platform_device_register(&orion5x_ehci0); | |
112 | } | |
113 | ||
114 | ||
115 | /***************************************************************************** | |
116 | * EHCI1 | |
117 | ****************************************************************************/ | |
118 | static struct resource orion5x_ehci1_resources[] = { | |
119 | { | |
120 | .start = ORION5X_USB1_PHYS_BASE, | |
121 | .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, | |
122 | .flags = IORESOURCE_MEM, | |
123 | }, { | |
124 | .start = IRQ_ORION5X_USB1_CTRL, | |
125 | .end = IRQ_ORION5X_USB1_CTRL, | |
126 | .flags = IORESOURCE_IRQ, | |
127 | }, | |
128 | }; | |
129 | ||
9dd0b194 | 130 | static struct platform_device orion5x_ehci1 = { |
ca26f7d3 TP |
131 | .name = "orion-ehci", |
132 | .id = 1, | |
133 | .dev = { | |
134 | .dma_mask = &ehci_dmamask, | |
5c602551 | 135 | .coherent_dma_mask = DMA_BIT_MASK(32), |
9dd0b194 | 136 | .platform_data = &orion5x_ehci_data, |
ca26f7d3 | 137 | }, |
9dd0b194 LB |
138 | .resource = orion5x_ehci1_resources, |
139 | .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), | |
ca26f7d3 TP |
140 | }; |
141 | ||
044f6c7c LB |
142 | void __init orion5x_ehci1_init(void) |
143 | { | |
144 | platform_device_register(&orion5x_ehci1); | |
145 | } | |
146 | ||
147 | ||
e07c9d85 | 148 | /***************************************************************************** |
5c602551 | 149 | * GE00 |
e07c9d85 | 150 | ****************************************************************************/ |
9dd0b194 | 151 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
e07c9d85 | 152 | { |
7e3819d8 AL |
153 | orion_ge00_init(eth_data, &orion5x_mbus_dram_info, |
154 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, | |
155 | IRQ_ORION5X_ETH_ERR, orion5x_tclk); | |
e07c9d85 TP |
156 | } |
157 | ||
044f6c7c | 158 | |
dcf1cece LB |
159 | /***************************************************************************** |
160 | * Ethernet switch | |
161 | ****************************************************************************/ | |
dcf1cece LB |
162 | void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) |
163 | { | |
7e3819d8 | 164 | orion_ge00_switch_init(d, irq); |
dcf1cece LB |
165 | } |
166 | ||
167 | ||
144aa3db | 168 | /***************************************************************************** |
044f6c7c | 169 | * I2C |
144aa3db | 170 | ****************************************************************************/ |
044f6c7c LB |
171 | void __init orion5x_i2c_init(void) |
172 | { | |
aac7ffa3 AL |
173 | orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); |
174 | ||
044f6c7c LB |
175 | } |
176 | ||
177 | ||
f244baa3 | 178 | /***************************************************************************** |
044f6c7c | 179 | * SATA |
f244baa3 | 180 | ****************************************************************************/ |
9dd0b194 | 181 | static struct resource orion5x_sata_resources[] = { |
f244baa3 | 182 | { |
e7068ad3 LB |
183 | .name = "sata base", |
184 | .start = ORION5X_SATA_PHYS_BASE, | |
185 | .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, | |
186 | .flags = IORESOURCE_MEM, | |
187 | }, { | |
188 | .name = "sata irq", | |
189 | .start = IRQ_ORION5X_SATA, | |
190 | .end = IRQ_ORION5X_SATA, | |
191 | .flags = IORESOURCE_IRQ, | |
192 | }, | |
f244baa3 SB |
193 | }; |
194 | ||
9dd0b194 | 195 | static struct platform_device orion5x_sata = { |
e7068ad3 LB |
196 | .name = "sata_mv", |
197 | .id = 0, | |
f244baa3 | 198 | .dev = { |
5c602551 | 199 | .coherent_dma_mask = DMA_BIT_MASK(32), |
f244baa3 | 200 | }, |
e7068ad3 LB |
201 | .num_resources = ARRAY_SIZE(orion5x_sata_resources), |
202 | .resource = orion5x_sata_resources, | |
f244baa3 SB |
203 | }; |
204 | ||
9dd0b194 | 205 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
f244baa3 | 206 | { |
9dd0b194 LB |
207 | sata_data->dram = &orion5x_mbus_dram_info; |
208 | orion5x_sata.dev.platform_data = sata_data; | |
209 | platform_device_register(&orion5x_sata); | |
f244baa3 SB |
210 | } |
211 | ||
044f6c7c | 212 | |
d323ade1 LB |
213 | /***************************************************************************** |
214 | * SPI | |
215 | ****************************************************************************/ | |
d323ade1 LB |
216 | void __init orion5x_spi_init() |
217 | { | |
980f9f60 | 218 | orion_spi_init(SPI_PHYS_BASE, orion5x_tclk); |
d323ade1 LB |
219 | } |
220 | ||
221 | ||
2bac1de2 | 222 | /***************************************************************************** |
044f6c7c LB |
223 | * UART0 |
224 | ****************************************************************************/ | |
044f6c7c LB |
225 | void __init orion5x_uart0_init(void) |
226 | { | |
28a2b450 AL |
227 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
228 | IRQ_ORION5X_UART0, orion5x_tclk); | |
044f6c7c LB |
229 | } |
230 | ||
044f6c7c LB |
231 | /***************************************************************************** |
232 | * UART1 | |
2bac1de2 | 233 | ****************************************************************************/ |
044f6c7c LB |
234 | void __init orion5x_uart1_init(void) |
235 | { | |
28a2b450 AL |
236 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
237 | IRQ_ORION5X_UART1, orion5x_tclk); | |
044f6c7c | 238 | } |
2bac1de2 | 239 | |
1d5a1a6e SB |
240 | /***************************************************************************** |
241 | * XOR engine | |
242 | ****************************************************************************/ | |
f45964ed SB |
243 | struct mv_xor_platform_shared_data orion5x_xor_shared_data = { |
244 | .dram = &orion5x_mbus_dram_info, | |
245 | }; | |
246 | ||
1d5a1a6e SB |
247 | static struct resource orion5x_xor_shared_resources[] = { |
248 | { | |
249 | .name = "xor low", | |
250 | .start = ORION5X_XOR_PHYS_BASE, | |
251 | .end = ORION5X_XOR_PHYS_BASE + 0xff, | |
252 | .flags = IORESOURCE_MEM, | |
253 | }, { | |
254 | .name = "xor high", | |
255 | .start = ORION5X_XOR_PHYS_BASE + 0x200, | |
256 | .end = ORION5X_XOR_PHYS_BASE + 0x2ff, | |
257 | .flags = IORESOURCE_MEM, | |
258 | }, | |
259 | }; | |
260 | ||
261 | static struct platform_device orion5x_xor_shared = { | |
262 | .name = MV_XOR_SHARED_NAME, | |
263 | .id = 0, | |
f45964ed SB |
264 | .dev = { |
265 | .platform_data = &orion5x_xor_shared_data, | |
266 | }, | |
1d5a1a6e SB |
267 | .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources), |
268 | .resource = orion5x_xor_shared_resources, | |
269 | }; | |
270 | ||
284901a9 | 271 | static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32); |
1d5a1a6e SB |
272 | |
273 | static struct resource orion5x_xor0_resources[] = { | |
274 | [0] = { | |
275 | .start = IRQ_ORION5X_XOR0, | |
276 | .end = IRQ_ORION5X_XOR0, | |
277 | .flags = IORESOURCE_IRQ, | |
278 | }, | |
279 | }; | |
280 | ||
281 | static struct mv_xor_platform_data orion5x_xor0_data = { | |
282 | .shared = &orion5x_xor_shared, | |
283 | .hw_id = 0, | |
284 | .pool_size = PAGE_SIZE, | |
285 | }; | |
286 | ||
287 | static struct platform_device orion5x_xor0_channel = { | |
288 | .name = MV_XOR_NAME, | |
289 | .id = 0, | |
290 | .num_resources = ARRAY_SIZE(orion5x_xor0_resources), | |
291 | .resource = orion5x_xor0_resources, | |
292 | .dev = { | |
293 | .dma_mask = &orion5x_xor_dmamask, | |
6a35528a | 294 | .coherent_dma_mask = DMA_BIT_MASK(64), |
ef4a6777 | 295 | .platform_data = &orion5x_xor0_data, |
1d5a1a6e SB |
296 | }, |
297 | }; | |
298 | ||
299 | static struct resource orion5x_xor1_resources[] = { | |
300 | [0] = { | |
301 | .start = IRQ_ORION5X_XOR1, | |
302 | .end = IRQ_ORION5X_XOR1, | |
303 | .flags = IORESOURCE_IRQ, | |
304 | }, | |
305 | }; | |
306 | ||
307 | static struct mv_xor_platform_data orion5x_xor1_data = { | |
308 | .shared = &orion5x_xor_shared, | |
309 | .hw_id = 1, | |
310 | .pool_size = PAGE_SIZE, | |
311 | }; | |
312 | ||
313 | static struct platform_device orion5x_xor1_channel = { | |
314 | .name = MV_XOR_NAME, | |
315 | .id = 1, | |
316 | .num_resources = ARRAY_SIZE(orion5x_xor1_resources), | |
317 | .resource = orion5x_xor1_resources, | |
318 | .dev = { | |
319 | .dma_mask = &orion5x_xor_dmamask, | |
6a35528a | 320 | .coherent_dma_mask = DMA_BIT_MASK(64), |
ef4a6777 | 321 | .platform_data = &orion5x_xor1_data, |
1d5a1a6e SB |
322 | }, |
323 | }; | |
324 | ||
325 | void __init orion5x_xor_init(void) | |
326 | { | |
327 | platform_device_register(&orion5x_xor_shared); | |
328 | ||
329 | /* | |
330 | * two engines can't do memset simultaneously, this limitation | |
331 | * satisfied by removing memset support from one of the engines. | |
332 | */ | |
333 | dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask); | |
334 | dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask); | |
335 | platform_device_register(&orion5x_xor0_channel); | |
336 | ||
337 | dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask); | |
338 | dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask); | |
339 | dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask); | |
340 | platform_device_register(&orion5x_xor1_channel); | |
341 | } | |
342 | ||
3a8f7441 SAS |
343 | static struct resource orion5x_crypto_res[] = { |
344 | { | |
345 | .name = "regs", | |
346 | .start = ORION5X_CRYPTO_PHYS_BASE, | |
347 | .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff, | |
348 | .flags = IORESOURCE_MEM, | |
349 | }, { | |
350 | .name = "sram", | |
351 | .start = ORION5X_SRAM_PHYS_BASE, | |
352 | .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1, | |
353 | .flags = IORESOURCE_MEM, | |
354 | }, { | |
355 | .name = "crypto interrupt", | |
356 | .start = IRQ_ORION5X_CESA, | |
357 | .end = IRQ_ORION5X_CESA, | |
358 | .flags = IORESOURCE_IRQ, | |
359 | }, | |
360 | }; | |
361 | ||
362 | static struct platform_device orion5x_crypto_device = { | |
363 | .name = "mv_crypto", | |
364 | .id = -1, | |
365 | .num_resources = ARRAY_SIZE(orion5x_crypto_res), | |
366 | .resource = orion5x_crypto_res, | |
367 | }; | |
368 | ||
3fade49b | 369 | static int __init orion5x_crypto_init(void) |
3a8f7441 SAS |
370 | { |
371 | int ret; | |
372 | ||
373 | ret = orion5x_setup_sram_win(); | |
374 | if (ret) | |
375 | return ret; | |
376 | ||
377 | return platform_device_register(&orion5x_crypto_device); | |
378 | } | |
1d5a1a6e | 379 | |
9e058d4f TR |
380 | /***************************************************************************** |
381 | * Watchdog | |
382 | ****************************************************************************/ | |
3b937a7d | 383 | static struct orion_wdt_platform_data orion5x_wdt_data = { |
9e058d4f TR |
384 | .tclk = 0, |
385 | }; | |
386 | ||
387 | static struct platform_device orion5x_wdt_device = { | |
3b937a7d | 388 | .name = "orion_wdt", |
9e058d4f TR |
389 | .id = -1, |
390 | .dev = { | |
391 | .platform_data = &orion5x_wdt_data, | |
392 | }, | |
393 | .num_resources = 0, | |
394 | }; | |
395 | ||
396 | void __init orion5x_wdt_init(void) | |
397 | { | |
398 | orion5x_wdt_data.tclk = orion5x_tclk; | |
399 | platform_device_register(&orion5x_wdt_device); | |
400 | } | |
401 | ||
402 | ||
044f6c7c LB |
403 | /***************************************************************************** |
404 | * Time handling | |
405 | ****************************************************************************/ | |
4ee1f6b5 LB |
406 | void __init orion5x_init_early(void) |
407 | { | |
408 | orion_time_set_base(TIMER_VIRT_BASE); | |
409 | } | |
410 | ||
ebe35aff LB |
411 | int orion5x_tclk; |
412 | ||
413 | int __init orion5x_find_tclk(void) | |
414 | { | |
d323ade1 LB |
415 | u32 dev, rev; |
416 | ||
417 | orion5x_pcie_id(&dev, &rev); | |
418 | if (dev == MV88F6183_DEV_ID && | |
419 | (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) | |
420 | return 133333333; | |
421 | ||
ebe35aff LB |
422 | return 166666667; |
423 | } | |
424 | ||
9dd0b194 | 425 | static void orion5x_timer_init(void) |
2bac1de2 | 426 | { |
ebe35aff | 427 | orion5x_tclk = orion5x_find_tclk(); |
4ee1f6b5 LB |
428 | |
429 | orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
430 | IRQ_ORION5X_BRIDGE, orion5x_tclk); | |
2bac1de2 LB |
431 | } |
432 | ||
9dd0b194 | 433 | struct sys_timer orion5x_timer = { |
e7068ad3 | 434 | .init = orion5x_timer_init, |
2bac1de2 LB |
435 | }; |
436 | ||
044f6c7c | 437 | |
c67de5b3 TP |
438 | /***************************************************************************** |
439 | * General | |
440 | ****************************************************************************/ | |
c67de5b3 | 441 | /* |
b46926bb | 442 | * Identify device ID and rev from PCIe configuration header space '0'. |
c67de5b3 | 443 | */ |
9dd0b194 | 444 | static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
c67de5b3 | 445 | { |
9dd0b194 | 446 | orion5x_pcie_id(dev, rev); |
c67de5b3 TP |
447 | |
448 | if (*dev == MV88F5281_DEV_ID) { | |
449 | if (*rev == MV88F5281_REV_D2) { | |
450 | *dev_name = "MV88F5281-D2"; | |
451 | } else if (*rev == MV88F5281_REV_D1) { | |
452 | *dev_name = "MV88F5281-D1"; | |
ce72e36e LB |
453 | } else if (*rev == MV88F5281_REV_D0) { |
454 | *dev_name = "MV88F5281-D0"; | |
c67de5b3 TP |
455 | } else { |
456 | *dev_name = "MV88F5281-Rev-Unsupported"; | |
457 | } | |
458 | } else if (*dev == MV88F5182_DEV_ID) { | |
459 | if (*rev == MV88F5182_REV_A2) { | |
460 | *dev_name = "MV88F5182-A2"; | |
461 | } else { | |
462 | *dev_name = "MV88F5182-Rev-Unsupported"; | |
463 | } | |
c9e3de94 HVR |
464 | } else if (*dev == MV88F5181_DEV_ID) { |
465 | if (*rev == MV88F5181_REV_B1) { | |
466 | *dev_name = "MV88F5181-Rev-B1"; | |
d2b2a6bb LB |
467 | } else if (*rev == MV88F5181L_REV_A1) { |
468 | *dev_name = "MV88F5181L-Rev-A1"; | |
c9e3de94 | 469 | } else { |
d2b2a6bb | 470 | *dev_name = "MV88F5181(L)-Rev-Unsupported"; |
c9e3de94 | 471 | } |
d323ade1 LB |
472 | } else if (*dev == MV88F6183_DEV_ID) { |
473 | if (*rev == MV88F6183_REV_B0) { | |
474 | *dev_name = "MV88F6183-Rev-B0"; | |
475 | } else { | |
476 | *dev_name = "MV88F6183-Rev-Unsupported"; | |
477 | } | |
c67de5b3 TP |
478 | } else { |
479 | *dev_name = "Device-Unknown"; | |
480 | } | |
481 | } | |
482 | ||
9dd0b194 | 483 | void __init orion5x_init(void) |
c67de5b3 TP |
484 | { |
485 | char *dev_name; | |
486 | u32 dev, rev; | |
487 | ||
9dd0b194 | 488 | orion5x_id(&dev, &rev, &dev_name); |
ebe35aff LB |
489 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); |
490 | ||
c67de5b3 TP |
491 | /* |
492 | * Setup Orion address map | |
493 | */ | |
9dd0b194 | 494 | orion5x_setup_cpu_mbus_bridge(); |
ce72e36e LB |
495 | |
496 | /* | |
497 | * Don't issue "Wait for Interrupt" instruction if we are | |
498 | * running on D0 5281 silicon. | |
499 | */ | |
500 | if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { | |
501 | printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); | |
502 | disable_hlt(); | |
503 | } | |
9e058d4f | 504 | |
3fade49b NP |
505 | /* |
506 | * The 5082/5181l/5182/6082/6082l/6183 have crypto | |
507 | * while 5180n/5181/5281 don't have crypto. | |
508 | */ | |
509 | if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || | |
510 | dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) | |
511 | orion5x_crypto_init(); | |
512 | ||
9e058d4f TR |
513 | /* |
514 | * Register watchdog driver | |
515 | */ | |
516 | orion5x_wdt_init(); | |
c67de5b3 | 517 | } |
be73a347 GL |
518 | |
519 | /* | |
520 | * Many orion-based systems have buggy bootloader implementations. | |
521 | * This is a common fixup for bogus memory tags. | |
522 | */ | |
523 | void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t, | |
524 | char **from, struct meminfo *meminfo) | |
525 | { | |
526 | for (; t->hdr.size; t = tag_next(t)) | |
527 | if (t->hdr.tag == ATAG_MEM && | |
528 | (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || | |
529 | t->u.mem.start & ~PAGE_MASK)) { | |
530 | printk(KERN_WARNING | |
531 | "Clearing invalid memory bank %dKB@0x%08x\n", | |
532 | t->u.mem.size / 1024, t->u.mem.start); | |
533 | t->hdr.tag = 0; | |
534 | } | |
535 | } |