Commit | Line | Data |
---|---|---|
585cf175 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/common.c |
585cf175 | 3 | * |
9dd0b194 | 4 | * Core functions for Marvell Orion 5x SoCs |
585cf175 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
585cf175 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
ca26f7d3 TP |
15 | #include <linux/platform_device.h> |
16 | #include <linux/serial_8250.h> | |
83b6d822 | 17 | #include <linux/mbus.h> |
e07c9d85 | 18 | #include <linux/mv643xx_eth.h> |
144aa3db | 19 | #include <linux/mv643xx_i2c.h> |
15a32632 | 20 | #include <linux/ata_platform.h> |
d323ade1 | 21 | #include <linux/spi/orion_spi.h> |
dcf1cece | 22 | #include <net/dsa.h> |
585cf175 | 23 | #include <asm/page.h> |
be73a347 | 24 | #include <asm/setup.h> |
c67de5b3 | 25 | #include <asm/timex.h> |
be73a347 | 26 | #include <asm/mach/arch.h> |
585cf175 | 27 | #include <asm/mach/map.h> |
2bac1de2 | 28 | #include <asm/mach/time.h> |
4ee1f6b5 | 29 | #include <mach/bridge-regs.h> |
a09e64fb RK |
30 | #include <mach/hardware.h> |
31 | #include <mach/orion5x.h> | |
6f088f1d | 32 | #include <plat/ehci-orion.h> |
1d5a1a6e | 33 | #include <plat/mv_xor.h> |
6f088f1d | 34 | #include <plat/orion_nand.h> |
3b937a7d | 35 | #include <plat/orion_wdt.h> |
6f088f1d | 36 | #include <plat/time.h> |
585cf175 TP |
37 | #include "common.h" |
38 | ||
39 | /***************************************************************************** | |
40 | * I/O Address Mapping | |
41 | ****************************************************************************/ | |
9dd0b194 | 42 | static struct map_desc orion5x_io_desc[] __initdata = { |
585cf175 | 43 | { |
9dd0b194 LB |
44 | .virtual = ORION5X_REGS_VIRT_BASE, |
45 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), | |
46 | .length = ORION5X_REGS_SIZE, | |
e7068ad3 LB |
47 | .type = MT_DEVICE, |
48 | }, { | |
9dd0b194 LB |
49 | .virtual = ORION5X_PCIE_IO_VIRT_BASE, |
50 | .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), | |
51 | .length = ORION5X_PCIE_IO_SIZE, | |
e7068ad3 LB |
52 | .type = MT_DEVICE, |
53 | }, { | |
9dd0b194 LB |
54 | .virtual = ORION5X_PCI_IO_VIRT_BASE, |
55 | .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), | |
56 | .length = ORION5X_PCI_IO_SIZE, | |
e7068ad3 LB |
57 | .type = MT_DEVICE, |
58 | }, { | |
9dd0b194 LB |
59 | .virtual = ORION5X_PCIE_WA_VIRT_BASE, |
60 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), | |
61 | .length = ORION5X_PCIE_WA_SIZE, | |
e7068ad3 | 62 | .type = MT_DEVICE, |
585cf175 TP |
63 | }, |
64 | }; | |
65 | ||
9dd0b194 | 66 | void __init orion5x_map_io(void) |
585cf175 | 67 | { |
9dd0b194 | 68 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
585cf175 | 69 | } |
c67de5b3 | 70 | |
044f6c7c | 71 | |
ca26f7d3 | 72 | /***************************************************************************** |
044f6c7c | 73 | * EHCI |
ca26f7d3 | 74 | ****************************************************************************/ |
044f6c7c LB |
75 | static struct orion_ehci_data orion5x_ehci_data = { |
76 | .dram = &orion5x_mbus_dram_info, | |
fb6f5529 | 77 | .phy_version = EHCI_PHY_ORION, |
ca26f7d3 TP |
78 | }; |
79 | ||
5c602551 | 80 | static u64 ehci_dmamask = DMA_BIT_MASK(32); |
ca26f7d3 | 81 | |
ca26f7d3 | 82 | |
044f6c7c LB |
83 | /***************************************************************************** |
84 | * EHCI0 | |
85 | ****************************************************************************/ | |
9dd0b194 | 86 | static struct resource orion5x_ehci0_resources[] = { |
ca26f7d3 | 87 | { |
9dd0b194 | 88 | .start = ORION5X_USB0_PHYS_BASE, |
994cab84 | 89 | .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1, |
ca26f7d3 | 90 | .flags = IORESOURCE_MEM, |
e7068ad3 | 91 | }, { |
9dd0b194 LB |
92 | .start = IRQ_ORION5X_USB0_CTRL, |
93 | .end = IRQ_ORION5X_USB0_CTRL, | |
ca26f7d3 TP |
94 | .flags = IORESOURCE_IRQ, |
95 | }, | |
96 | }; | |
97 | ||
9dd0b194 | 98 | static struct platform_device orion5x_ehci0 = { |
ca26f7d3 TP |
99 | .name = "orion-ehci", |
100 | .id = 0, | |
101 | .dev = { | |
102 | .dma_mask = &ehci_dmamask, | |
5c602551 | 103 | .coherent_dma_mask = DMA_BIT_MASK(32), |
9dd0b194 | 104 | .platform_data = &orion5x_ehci_data, |
ca26f7d3 | 105 | }, |
9dd0b194 LB |
106 | .resource = orion5x_ehci0_resources, |
107 | .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), | |
ca26f7d3 TP |
108 | }; |
109 | ||
044f6c7c LB |
110 | void __init orion5x_ehci0_init(void) |
111 | { | |
112 | platform_device_register(&orion5x_ehci0); | |
113 | } | |
114 | ||
115 | ||
116 | /***************************************************************************** | |
117 | * EHCI1 | |
118 | ****************************************************************************/ | |
119 | static struct resource orion5x_ehci1_resources[] = { | |
120 | { | |
121 | .start = ORION5X_USB1_PHYS_BASE, | |
122 | .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, | |
123 | .flags = IORESOURCE_MEM, | |
124 | }, { | |
125 | .start = IRQ_ORION5X_USB1_CTRL, | |
126 | .end = IRQ_ORION5X_USB1_CTRL, | |
127 | .flags = IORESOURCE_IRQ, | |
128 | }, | |
129 | }; | |
130 | ||
9dd0b194 | 131 | static struct platform_device orion5x_ehci1 = { |
ca26f7d3 TP |
132 | .name = "orion-ehci", |
133 | .id = 1, | |
134 | .dev = { | |
135 | .dma_mask = &ehci_dmamask, | |
5c602551 | 136 | .coherent_dma_mask = DMA_BIT_MASK(32), |
9dd0b194 | 137 | .platform_data = &orion5x_ehci_data, |
ca26f7d3 | 138 | }, |
9dd0b194 LB |
139 | .resource = orion5x_ehci1_resources, |
140 | .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), | |
ca26f7d3 TP |
141 | }; |
142 | ||
044f6c7c LB |
143 | void __init orion5x_ehci1_init(void) |
144 | { | |
145 | platform_device_register(&orion5x_ehci1); | |
146 | } | |
147 | ||
148 | ||
e07c9d85 | 149 | /***************************************************************************** |
5c602551 | 150 | * GE00 |
e07c9d85 | 151 | ****************************************************************************/ |
5c602551 | 152 | struct mv643xx_eth_shared_platform_data orion5x_ge00_shared_data = { |
d236f5a5 LB |
153 | .dram = &orion5x_mbus_dram_info, |
154 | }; | |
155 | ||
5c602551 | 156 | static struct resource orion5x_ge00_shared_resources[] = { |
e07c9d85 | 157 | { |
9dd0b194 | 158 | .start = ORION5X_ETH_PHYS_BASE + 0x2000, |
5c602551 | 159 | .end = ORION5X_ETH_PHYS_BASE + SZ_16K - 1, |
e07c9d85 | 160 | .flags = IORESOURCE_MEM, |
eeff6d86 LB |
161 | }, { |
162 | .start = IRQ_ORION5X_ETH_ERR, | |
163 | .end = IRQ_ORION5X_ETH_ERR, | |
164 | .flags = IORESOURCE_IRQ, | |
e07c9d85 TP |
165 | }, |
166 | }; | |
167 | ||
5c602551 | 168 | static struct platform_device orion5x_ge00_shared = { |
e07c9d85 TP |
169 | .name = MV643XX_ETH_SHARED_NAME, |
170 | .id = 0, | |
d236f5a5 | 171 | .dev = { |
5c602551 | 172 | .platform_data = &orion5x_ge00_shared_data, |
d236f5a5 | 173 | }, |
5c602551 AL |
174 | .num_resources = ARRAY_SIZE(orion5x_ge00_shared_resources), |
175 | .resource = orion5x_ge00_shared_resources, | |
e07c9d85 TP |
176 | }; |
177 | ||
5c602551 | 178 | static struct resource orion5x_ge00_resources[] = { |
e07c9d85 TP |
179 | { |
180 | .name = "eth irq", | |
9dd0b194 LB |
181 | .start = IRQ_ORION5X_ETH_SUM, |
182 | .end = IRQ_ORION5X_ETH_SUM, | |
e07c9d85 | 183 | .flags = IORESOURCE_IRQ, |
e7068ad3 | 184 | }, |
e07c9d85 TP |
185 | }; |
186 | ||
9dd0b194 | 187 | static struct platform_device orion5x_eth = { |
e07c9d85 TP |
188 | .name = MV643XX_ETH_NAME, |
189 | .id = 0, | |
190 | .num_resources = 1, | |
5c602551 | 191 | .resource = orion5x_ge00_resources, |
a49a018a | 192 | .dev = { |
5c602551 | 193 | .coherent_dma_mask = DMA_BIT_MASK(32), |
a49a018a | 194 | }, |
e07c9d85 TP |
195 | }; |
196 | ||
9dd0b194 | 197 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
e07c9d85 | 198 | { |
5c602551 | 199 | eth_data->shared = &orion5x_ge00_shared; |
9dd0b194 | 200 | orion5x_eth.dev.platform_data = eth_data; |
fa3959f4 | 201 | |
5c602551 | 202 | platform_device_register(&orion5x_ge00_shared); |
9dd0b194 | 203 | platform_device_register(&orion5x_eth); |
e07c9d85 TP |
204 | } |
205 | ||
044f6c7c | 206 | |
dcf1cece LB |
207 | /***************************************************************************** |
208 | * Ethernet switch | |
209 | ****************************************************************************/ | |
210 | static struct resource orion5x_switch_resources[] = { | |
211 | { | |
212 | .start = 0, | |
213 | .end = 0, | |
214 | .flags = IORESOURCE_IRQ, | |
215 | }, | |
216 | }; | |
217 | ||
218 | static struct platform_device orion5x_switch_device = { | |
219 | .name = "dsa", | |
220 | .id = 0, | |
221 | .num_resources = 0, | |
222 | .resource = orion5x_switch_resources, | |
223 | }; | |
224 | ||
225 | void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) | |
226 | { | |
e84665c9 LB |
227 | int i; |
228 | ||
dcf1cece LB |
229 | if (irq != NO_IRQ) { |
230 | orion5x_switch_resources[0].start = irq; | |
231 | orion5x_switch_resources[0].end = irq; | |
232 | orion5x_switch_device.num_resources = 1; | |
233 | } | |
234 | ||
dcf1cece | 235 | d->netdev = &orion5x_eth.dev; |
e84665c9 | 236 | for (i = 0; i < d->nr_chips; i++) |
5c602551 | 237 | d->chip[i].mii_bus = &orion5x_ge00_shared.dev; |
dcf1cece LB |
238 | orion5x_switch_device.dev.platform_data = d; |
239 | ||
240 | platform_device_register(&orion5x_switch_device); | |
241 | } | |
242 | ||
243 | ||
144aa3db | 244 | /***************************************************************************** |
044f6c7c | 245 | * I2C |
144aa3db | 246 | ****************************************************************************/ |
9dd0b194 | 247 | static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { |
144aa3db HVR |
248 | .freq_m = 8, /* assumes 166 MHz TCLK */ |
249 | .freq_n = 3, | |
250 | .timeout = 1000, /* Default timeout of 1 second */ | |
251 | }; | |
252 | ||
9dd0b194 | 253 | static struct resource orion5x_i2c_resources[] = { |
144aa3db | 254 | { |
e7068ad3 | 255 | .start = I2C_PHYS_BASE, |
044f6c7c | 256 | .end = I2C_PHYS_BASE + 0x1f, |
e7068ad3 LB |
257 | .flags = IORESOURCE_MEM, |
258 | }, { | |
e7068ad3 LB |
259 | .start = IRQ_ORION5X_I2C, |
260 | .end = IRQ_ORION5X_I2C, | |
261 | .flags = IORESOURCE_IRQ, | |
144aa3db HVR |
262 | }, |
263 | }; | |
264 | ||
9dd0b194 | 265 | static struct platform_device orion5x_i2c = { |
144aa3db HVR |
266 | .name = MV64XXX_I2C_CTLR_NAME, |
267 | .id = 0, | |
9dd0b194 LB |
268 | .num_resources = ARRAY_SIZE(orion5x_i2c_resources), |
269 | .resource = orion5x_i2c_resources, | |
144aa3db | 270 | .dev = { |
e7068ad3 | 271 | .platform_data = &orion5x_i2c_pdata, |
144aa3db HVR |
272 | }, |
273 | }; | |
274 | ||
044f6c7c LB |
275 | void __init orion5x_i2c_init(void) |
276 | { | |
277 | platform_device_register(&orion5x_i2c); | |
278 | } | |
279 | ||
280 | ||
f244baa3 | 281 | /***************************************************************************** |
044f6c7c | 282 | * SATA |
f244baa3 | 283 | ****************************************************************************/ |
9dd0b194 | 284 | static struct resource orion5x_sata_resources[] = { |
f244baa3 | 285 | { |
e7068ad3 LB |
286 | .name = "sata base", |
287 | .start = ORION5X_SATA_PHYS_BASE, | |
288 | .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, | |
289 | .flags = IORESOURCE_MEM, | |
290 | }, { | |
291 | .name = "sata irq", | |
292 | .start = IRQ_ORION5X_SATA, | |
293 | .end = IRQ_ORION5X_SATA, | |
294 | .flags = IORESOURCE_IRQ, | |
295 | }, | |
f244baa3 SB |
296 | }; |
297 | ||
9dd0b194 | 298 | static struct platform_device orion5x_sata = { |
e7068ad3 LB |
299 | .name = "sata_mv", |
300 | .id = 0, | |
f244baa3 | 301 | .dev = { |
5c602551 | 302 | .coherent_dma_mask = DMA_BIT_MASK(32), |
f244baa3 | 303 | }, |
e7068ad3 LB |
304 | .num_resources = ARRAY_SIZE(orion5x_sata_resources), |
305 | .resource = orion5x_sata_resources, | |
f244baa3 SB |
306 | }; |
307 | ||
9dd0b194 | 308 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
f244baa3 | 309 | { |
9dd0b194 LB |
310 | sata_data->dram = &orion5x_mbus_dram_info; |
311 | orion5x_sata.dev.platform_data = sata_data; | |
312 | platform_device_register(&orion5x_sata); | |
f244baa3 SB |
313 | } |
314 | ||
044f6c7c | 315 | |
d323ade1 LB |
316 | /***************************************************************************** |
317 | * SPI | |
318 | ****************************************************************************/ | |
319 | static struct orion_spi_info orion5x_spi_plat_data = { | |
c0e19363 NP |
320 | .tclk = 0, |
321 | .enable_clock_fix = 1, | |
d323ade1 LB |
322 | }; |
323 | ||
324 | static struct resource orion5x_spi_resources[] = { | |
325 | { | |
326 | .name = "spi base", | |
327 | .start = SPI_PHYS_BASE, | |
328 | .end = SPI_PHYS_BASE + 0x1f, | |
329 | .flags = IORESOURCE_MEM, | |
330 | }, | |
331 | }; | |
332 | ||
333 | static struct platform_device orion5x_spi = { | |
334 | .name = "orion_spi", | |
335 | .id = 0, | |
336 | .dev = { | |
337 | .platform_data = &orion5x_spi_plat_data, | |
338 | }, | |
339 | .num_resources = ARRAY_SIZE(orion5x_spi_resources), | |
340 | .resource = orion5x_spi_resources, | |
341 | }; | |
342 | ||
343 | void __init orion5x_spi_init() | |
344 | { | |
345 | platform_device_register(&orion5x_spi); | |
346 | } | |
347 | ||
348 | ||
2bac1de2 | 349 | /***************************************************************************** |
044f6c7c LB |
350 | * UART0 |
351 | ****************************************************************************/ | |
352 | static struct plat_serial8250_port orion5x_uart0_data[] = { | |
353 | { | |
354 | .mapbase = UART0_PHYS_BASE, | |
355 | .membase = (char *)UART0_VIRT_BASE, | |
356 | .irq = IRQ_ORION5X_UART0, | |
357 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | |
358 | .iotype = UPIO_MEM, | |
359 | .regshift = 2, | |
ebe35aff | 360 | .uartclk = 0, |
044f6c7c LB |
361 | }, { |
362 | }, | |
363 | }; | |
364 | ||
365 | static struct resource orion5x_uart0_resources[] = { | |
366 | { | |
367 | .start = UART0_PHYS_BASE, | |
368 | .end = UART0_PHYS_BASE + 0xff, | |
369 | .flags = IORESOURCE_MEM, | |
370 | }, { | |
371 | .start = IRQ_ORION5X_UART0, | |
372 | .end = IRQ_ORION5X_UART0, | |
373 | .flags = IORESOURCE_IRQ, | |
374 | }, | |
375 | }; | |
376 | ||
377 | static struct platform_device orion5x_uart0 = { | |
378 | .name = "serial8250", | |
379 | .id = PLAT8250_DEV_PLATFORM, | |
380 | .dev = { | |
381 | .platform_data = orion5x_uart0_data, | |
382 | }, | |
383 | .resource = orion5x_uart0_resources, | |
384 | .num_resources = ARRAY_SIZE(orion5x_uart0_resources), | |
385 | }; | |
386 | ||
387 | void __init orion5x_uart0_init(void) | |
388 | { | |
389 | platform_device_register(&orion5x_uart0); | |
390 | } | |
391 | ||
392 | ||
393 | /***************************************************************************** | |
394 | * UART1 | |
2bac1de2 | 395 | ****************************************************************************/ |
044f6c7c LB |
396 | static struct plat_serial8250_port orion5x_uart1_data[] = { |
397 | { | |
398 | .mapbase = UART1_PHYS_BASE, | |
399 | .membase = (char *)UART1_VIRT_BASE, | |
400 | .irq = IRQ_ORION5X_UART1, | |
401 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | |
402 | .iotype = UPIO_MEM, | |
403 | .regshift = 2, | |
ebe35aff | 404 | .uartclk = 0, |
044f6c7c LB |
405 | }, { |
406 | }, | |
407 | }; | |
408 | ||
409 | static struct resource orion5x_uart1_resources[] = { | |
410 | { | |
411 | .start = UART1_PHYS_BASE, | |
412 | .end = UART1_PHYS_BASE + 0xff, | |
413 | .flags = IORESOURCE_MEM, | |
414 | }, { | |
415 | .start = IRQ_ORION5X_UART1, | |
416 | .end = IRQ_ORION5X_UART1, | |
417 | .flags = IORESOURCE_IRQ, | |
418 | }, | |
419 | }; | |
420 | ||
421 | static struct platform_device orion5x_uart1 = { | |
422 | .name = "serial8250", | |
423 | .id = PLAT8250_DEV_PLATFORM1, | |
424 | .dev = { | |
425 | .platform_data = orion5x_uart1_data, | |
426 | }, | |
427 | .resource = orion5x_uart1_resources, | |
428 | .num_resources = ARRAY_SIZE(orion5x_uart1_resources), | |
429 | }; | |
430 | ||
431 | void __init orion5x_uart1_init(void) | |
432 | { | |
433 | platform_device_register(&orion5x_uart1); | |
434 | } | |
2bac1de2 | 435 | |
044f6c7c | 436 | |
1d5a1a6e SB |
437 | /***************************************************************************** |
438 | * XOR engine | |
439 | ****************************************************************************/ | |
f45964ed SB |
440 | struct mv_xor_platform_shared_data orion5x_xor_shared_data = { |
441 | .dram = &orion5x_mbus_dram_info, | |
442 | }; | |
443 | ||
1d5a1a6e SB |
444 | static struct resource orion5x_xor_shared_resources[] = { |
445 | { | |
446 | .name = "xor low", | |
447 | .start = ORION5X_XOR_PHYS_BASE, | |
448 | .end = ORION5X_XOR_PHYS_BASE + 0xff, | |
449 | .flags = IORESOURCE_MEM, | |
450 | }, { | |
451 | .name = "xor high", | |
452 | .start = ORION5X_XOR_PHYS_BASE + 0x200, | |
453 | .end = ORION5X_XOR_PHYS_BASE + 0x2ff, | |
454 | .flags = IORESOURCE_MEM, | |
455 | }, | |
456 | }; | |
457 | ||
458 | static struct platform_device orion5x_xor_shared = { | |
459 | .name = MV_XOR_SHARED_NAME, | |
460 | .id = 0, | |
f45964ed SB |
461 | .dev = { |
462 | .platform_data = &orion5x_xor_shared_data, | |
463 | }, | |
1d5a1a6e SB |
464 | .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources), |
465 | .resource = orion5x_xor_shared_resources, | |
466 | }; | |
467 | ||
284901a9 | 468 | static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32); |
1d5a1a6e SB |
469 | |
470 | static struct resource orion5x_xor0_resources[] = { | |
471 | [0] = { | |
472 | .start = IRQ_ORION5X_XOR0, | |
473 | .end = IRQ_ORION5X_XOR0, | |
474 | .flags = IORESOURCE_IRQ, | |
475 | }, | |
476 | }; | |
477 | ||
478 | static struct mv_xor_platform_data orion5x_xor0_data = { | |
479 | .shared = &orion5x_xor_shared, | |
480 | .hw_id = 0, | |
481 | .pool_size = PAGE_SIZE, | |
482 | }; | |
483 | ||
484 | static struct platform_device orion5x_xor0_channel = { | |
485 | .name = MV_XOR_NAME, | |
486 | .id = 0, | |
487 | .num_resources = ARRAY_SIZE(orion5x_xor0_resources), | |
488 | .resource = orion5x_xor0_resources, | |
489 | .dev = { | |
490 | .dma_mask = &orion5x_xor_dmamask, | |
6a35528a | 491 | .coherent_dma_mask = DMA_BIT_MASK(64), |
ef4a6777 | 492 | .platform_data = &orion5x_xor0_data, |
1d5a1a6e SB |
493 | }, |
494 | }; | |
495 | ||
496 | static struct resource orion5x_xor1_resources[] = { | |
497 | [0] = { | |
498 | .start = IRQ_ORION5X_XOR1, | |
499 | .end = IRQ_ORION5X_XOR1, | |
500 | .flags = IORESOURCE_IRQ, | |
501 | }, | |
502 | }; | |
503 | ||
504 | static struct mv_xor_platform_data orion5x_xor1_data = { | |
505 | .shared = &orion5x_xor_shared, | |
506 | .hw_id = 1, | |
507 | .pool_size = PAGE_SIZE, | |
508 | }; | |
509 | ||
510 | static struct platform_device orion5x_xor1_channel = { | |
511 | .name = MV_XOR_NAME, | |
512 | .id = 1, | |
513 | .num_resources = ARRAY_SIZE(orion5x_xor1_resources), | |
514 | .resource = orion5x_xor1_resources, | |
515 | .dev = { | |
516 | .dma_mask = &orion5x_xor_dmamask, | |
6a35528a | 517 | .coherent_dma_mask = DMA_BIT_MASK(64), |
ef4a6777 | 518 | .platform_data = &orion5x_xor1_data, |
1d5a1a6e SB |
519 | }, |
520 | }; | |
521 | ||
522 | void __init orion5x_xor_init(void) | |
523 | { | |
524 | platform_device_register(&orion5x_xor_shared); | |
525 | ||
526 | /* | |
527 | * two engines can't do memset simultaneously, this limitation | |
528 | * satisfied by removing memset support from one of the engines. | |
529 | */ | |
530 | dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask); | |
531 | dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask); | |
532 | platform_device_register(&orion5x_xor0_channel); | |
533 | ||
534 | dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask); | |
535 | dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask); | |
536 | dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask); | |
537 | platform_device_register(&orion5x_xor1_channel); | |
538 | } | |
539 | ||
3a8f7441 SAS |
540 | static struct resource orion5x_crypto_res[] = { |
541 | { | |
542 | .name = "regs", | |
543 | .start = ORION5X_CRYPTO_PHYS_BASE, | |
544 | .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff, | |
545 | .flags = IORESOURCE_MEM, | |
546 | }, { | |
547 | .name = "sram", | |
548 | .start = ORION5X_SRAM_PHYS_BASE, | |
549 | .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1, | |
550 | .flags = IORESOURCE_MEM, | |
551 | }, { | |
552 | .name = "crypto interrupt", | |
553 | .start = IRQ_ORION5X_CESA, | |
554 | .end = IRQ_ORION5X_CESA, | |
555 | .flags = IORESOURCE_IRQ, | |
556 | }, | |
557 | }; | |
558 | ||
559 | static struct platform_device orion5x_crypto_device = { | |
560 | .name = "mv_crypto", | |
561 | .id = -1, | |
562 | .num_resources = ARRAY_SIZE(orion5x_crypto_res), | |
563 | .resource = orion5x_crypto_res, | |
564 | }; | |
565 | ||
3fade49b | 566 | static int __init orion5x_crypto_init(void) |
3a8f7441 SAS |
567 | { |
568 | int ret; | |
569 | ||
570 | ret = orion5x_setup_sram_win(); | |
571 | if (ret) | |
572 | return ret; | |
573 | ||
574 | return platform_device_register(&orion5x_crypto_device); | |
575 | } | |
1d5a1a6e | 576 | |
9e058d4f TR |
577 | /***************************************************************************** |
578 | * Watchdog | |
579 | ****************************************************************************/ | |
3b937a7d | 580 | static struct orion_wdt_platform_data orion5x_wdt_data = { |
9e058d4f TR |
581 | .tclk = 0, |
582 | }; | |
583 | ||
584 | static struct platform_device orion5x_wdt_device = { | |
3b937a7d | 585 | .name = "orion_wdt", |
9e058d4f TR |
586 | .id = -1, |
587 | .dev = { | |
588 | .platform_data = &orion5x_wdt_data, | |
589 | }, | |
590 | .num_resources = 0, | |
591 | }; | |
592 | ||
593 | void __init orion5x_wdt_init(void) | |
594 | { | |
595 | orion5x_wdt_data.tclk = orion5x_tclk; | |
596 | platform_device_register(&orion5x_wdt_device); | |
597 | } | |
598 | ||
599 | ||
044f6c7c LB |
600 | /***************************************************************************** |
601 | * Time handling | |
602 | ****************************************************************************/ | |
4ee1f6b5 LB |
603 | void __init orion5x_init_early(void) |
604 | { | |
605 | orion_time_set_base(TIMER_VIRT_BASE); | |
606 | } | |
607 | ||
ebe35aff LB |
608 | int orion5x_tclk; |
609 | ||
610 | int __init orion5x_find_tclk(void) | |
611 | { | |
d323ade1 LB |
612 | u32 dev, rev; |
613 | ||
614 | orion5x_pcie_id(&dev, &rev); | |
615 | if (dev == MV88F6183_DEV_ID && | |
616 | (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) | |
617 | return 133333333; | |
618 | ||
ebe35aff LB |
619 | return 166666667; |
620 | } | |
621 | ||
9dd0b194 | 622 | static void orion5x_timer_init(void) |
2bac1de2 | 623 | { |
ebe35aff | 624 | orion5x_tclk = orion5x_find_tclk(); |
4ee1f6b5 LB |
625 | |
626 | orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, | |
627 | IRQ_ORION5X_BRIDGE, orion5x_tclk); | |
2bac1de2 LB |
628 | } |
629 | ||
9dd0b194 | 630 | struct sys_timer orion5x_timer = { |
e7068ad3 | 631 | .init = orion5x_timer_init, |
2bac1de2 LB |
632 | }; |
633 | ||
044f6c7c | 634 | |
c67de5b3 TP |
635 | /***************************************************************************** |
636 | * General | |
637 | ****************************************************************************/ | |
c67de5b3 | 638 | /* |
b46926bb | 639 | * Identify device ID and rev from PCIe configuration header space '0'. |
c67de5b3 | 640 | */ |
9dd0b194 | 641 | static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
c67de5b3 | 642 | { |
9dd0b194 | 643 | orion5x_pcie_id(dev, rev); |
c67de5b3 TP |
644 | |
645 | if (*dev == MV88F5281_DEV_ID) { | |
646 | if (*rev == MV88F5281_REV_D2) { | |
647 | *dev_name = "MV88F5281-D2"; | |
648 | } else if (*rev == MV88F5281_REV_D1) { | |
649 | *dev_name = "MV88F5281-D1"; | |
ce72e36e LB |
650 | } else if (*rev == MV88F5281_REV_D0) { |
651 | *dev_name = "MV88F5281-D0"; | |
c67de5b3 TP |
652 | } else { |
653 | *dev_name = "MV88F5281-Rev-Unsupported"; | |
654 | } | |
655 | } else if (*dev == MV88F5182_DEV_ID) { | |
656 | if (*rev == MV88F5182_REV_A2) { | |
657 | *dev_name = "MV88F5182-A2"; | |
658 | } else { | |
659 | *dev_name = "MV88F5182-Rev-Unsupported"; | |
660 | } | |
c9e3de94 HVR |
661 | } else if (*dev == MV88F5181_DEV_ID) { |
662 | if (*rev == MV88F5181_REV_B1) { | |
663 | *dev_name = "MV88F5181-Rev-B1"; | |
d2b2a6bb LB |
664 | } else if (*rev == MV88F5181L_REV_A1) { |
665 | *dev_name = "MV88F5181L-Rev-A1"; | |
c9e3de94 | 666 | } else { |
d2b2a6bb | 667 | *dev_name = "MV88F5181(L)-Rev-Unsupported"; |
c9e3de94 | 668 | } |
d323ade1 LB |
669 | } else if (*dev == MV88F6183_DEV_ID) { |
670 | if (*rev == MV88F6183_REV_B0) { | |
671 | *dev_name = "MV88F6183-Rev-B0"; | |
672 | } else { | |
673 | *dev_name = "MV88F6183-Rev-Unsupported"; | |
674 | } | |
c67de5b3 TP |
675 | } else { |
676 | *dev_name = "Device-Unknown"; | |
677 | } | |
678 | } | |
679 | ||
9dd0b194 | 680 | void __init orion5x_init(void) |
c67de5b3 TP |
681 | { |
682 | char *dev_name; | |
683 | u32 dev, rev; | |
684 | ||
9dd0b194 | 685 | orion5x_id(&dev, &rev, &dev_name); |
ebe35aff LB |
686 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); |
687 | ||
5c602551 | 688 | orion5x_ge00_shared_data.t_clk = orion5x_tclk; |
d323ade1 | 689 | orion5x_spi_plat_data.tclk = orion5x_tclk; |
ebe35aff LB |
690 | orion5x_uart0_data[0].uartclk = orion5x_tclk; |
691 | orion5x_uart1_data[0].uartclk = orion5x_tclk; | |
c67de5b3 TP |
692 | |
693 | /* | |
694 | * Setup Orion address map | |
695 | */ | |
9dd0b194 | 696 | orion5x_setup_cpu_mbus_bridge(); |
ce72e36e LB |
697 | |
698 | /* | |
699 | * Don't issue "Wait for Interrupt" instruction if we are | |
700 | * running on D0 5281 silicon. | |
701 | */ | |
702 | if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { | |
703 | printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); | |
704 | disable_hlt(); | |
705 | } | |
9e058d4f | 706 | |
3fade49b NP |
707 | /* |
708 | * The 5082/5181l/5182/6082/6082l/6183 have crypto | |
709 | * while 5180n/5181/5281 don't have crypto. | |
710 | */ | |
711 | if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || | |
712 | dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) | |
713 | orion5x_crypto_init(); | |
714 | ||
9e058d4f TR |
715 | /* |
716 | * Register watchdog driver | |
717 | */ | |
718 | orion5x_wdt_init(); | |
c67de5b3 | 719 | } |
be73a347 GL |
720 | |
721 | /* | |
722 | * Many orion-based systems have buggy bootloader implementations. | |
723 | * This is a common fixup for bogus memory tags. | |
724 | */ | |
725 | void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t, | |
726 | char **from, struct meminfo *meminfo) | |
727 | { | |
728 | for (; t->hdr.size; t = tag_next(t)) | |
729 | if (t->hdr.tag == ATAG_MEM && | |
730 | (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || | |
731 | t->u.mem.start & ~PAGE_MASK)) { | |
732 | printk(KERN_WARNING | |
733 | "Clearing invalid memory bank %dKB@0x%08x\n", | |
734 | t->u.mem.size / 1024, t->u.mem.start); | |
735 | t->hdr.tag = 0; | |
736 | } | |
737 | } |