[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-orion5x / common.c

/*
 * arch/arm/mach-orion5x/common.c
 *
 * Core functions for Marvell Orion 5x SoCs
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/orion5x.h>
#include <plat/ehci-orion.h>
#include <plat/mv_xor.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
#include "common.h"

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc orion5x_io_desc[] __initdata = {
	{
		.virtual	= ORION5X_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
		.length		= ORION5X_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCIE_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
		.length		= ORION5X_PCIE_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCI_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
		.length		= ORION5X_PCI_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCIE_WA_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
		.length		= ORION5X_PCIE_WA_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init orion5x_map_io(void)
{
	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
}


/*****************************************************************************
 * EHCI
 ****************************************************************************/
static struct orion_ehci_data orion5x_ehci_data = {
	.dram		= &orion5x_mbus_dram_info,
};

static u64 ehci_dmamask = 0xffffffffUL;


/*****************************************************************************
 * EHCI0
 ****************************************************************************/
static struct resource orion5x_ehci0_resources[] = {
	{
		.start	= ORION5X_USB0_PHYS_BASE,
		.end	= ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_USB0_CTRL,
		.end	= IRQ_ORION5X_USB0_CTRL,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_ehci0 = {
	.name		= "orion-ehci",
	.id		= 0,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &orion5x_ehci_data,
	},
	.resource	= orion5x_ehci0_resources,
	.num_resources	= ARRAY_SIZE(orion5x_ehci0_resources),
};

void __init orion5x_ehci0_init(void)
{
	platform_device_register(&orion5x_ehci0);
}


/*****************************************************************************
 * EHCI1
 ****************************************************************************/
static struct resource orion5x_ehci1_resources[] = {
	{
		.start	= ORION5X_USB1_PHYS_BASE,
		.end	= ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_USB1_CTRL,
		.end	= IRQ_ORION5X_USB1_CTRL,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_ehci1 = {
	.name		= "orion-ehci",
	.id		= 1,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &orion5x_ehci_data,
	},
	.resource	= orion5x_ehci1_resources,
	.num_resources	= ARRAY_SIZE(orion5x_ehci1_resources),
};

void __init orion5x_ehci1_init(void)
{
	platform_device_register(&orion5x_ehci1);
}


/*****************************************************************************
 * GigE
 ****************************************************************************/
struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
	.dram		= &orion5x_mbus_dram_info,
	.t_clk		= ORION5X_TCLK,
};

static struct resource orion5x_eth_shared_resources[] = {
	{
		.start	= ORION5X_ETH_PHYS_BASE + 0x2000,
		.end	= ORION5X_ETH_PHYS_BASE + 0x3fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_ETH_ERR,
		.end	= IRQ_ORION5X_ETH_ERR,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_eth_shared = {
	.name		= MV643XX_ETH_SHARED_NAME,
	.id		= 0,
	.dev		= {
		.platform_data	= &orion5x_eth_shared_data,
	},
	.num_resources	= ARRAY_SIZE(orion5x_eth_shared_resources),
	.resource	= orion5x_eth_shared_resources,
};

static struct resource orion5x_eth_resources[] = {
	{
		.name	= "eth irq",
		.start	= IRQ_ORION5X_ETH_SUM,
		.end	= IRQ_ORION5X_ETH_SUM,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_eth = {
	.name		= MV643XX_ETH_NAME,
	.id		= 0,
	.num_resources	= 1,
	.resource	= orion5x_eth_resources,
};

void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
{
	eth_data->shared = &orion5x_eth_shared;
	orion5x_eth.dev.platform_data = eth_data;

	platform_device_register(&orion5x_eth_shared);
	platform_device_register(&orion5x_eth);
}


/*****************************************************************************
 * I2C
 ****************************************************************************/
static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
	.freq_m		= 8, /* assumes 166 MHz TCLK */
	.freq_n		= 3,
	.timeout	= 1000, /* Default timeout of 1 second */
};

static struct resource orion5x_i2c_resources[] = {
	{
		.name	= "i2c base",
		.start	= I2C_PHYS_BASE,
		.end	= I2C_PHYS_BASE + 0x1f,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "i2c irq",
		.start	= IRQ_ORION5X_I2C,
		.end	= IRQ_ORION5X_I2C,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_i2c = {
	.name		= MV64XXX_I2C_CTLR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_i2c_resources),
	.resource	= orion5x_i2c_resources,
	.dev		= {
		.platform_data	= &orion5x_i2c_pdata,
	},
};

void __init orion5x_i2c_init(void)
{
	platform_device_register(&orion5x_i2c);
}


/*****************************************************************************
 * SATA
 ****************************************************************************/
static struct resource orion5x_sata_resources[] = {
	{
		.name	= "sata base",
		.start	= ORION5X_SATA_PHYS_BASE,
		.end	= ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "sata irq",
		.start	= IRQ_ORION5X_SATA,
		.end	= IRQ_ORION5X_SATA,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_sata = {
	.name		= "sata_mv",
	.id		= 0,
	.dev		= {
		.coherent_dma_mask	= 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(orion5x_sata_resources),
	.resource	= orion5x_sata_resources,
};

void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
{
	sata_data->dram = &orion5x_mbus_dram_info;
	orion5x_sata.dev.platform_data = sata_data;
	platform_device_register(&orion5x_sata);
}


/*****************************************************************************
 * UART0
 ****************************************************************************/
static struct plat_serial8250_port orion5x_uart0_data[] = {
	{
		.mapbase	= UART0_PHYS_BASE,
		.membase	= (char *)UART0_VIRT_BASE,
		.irq		= IRQ_ORION5X_UART0,
		.flags		= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= ORION5X_TCLK,
	}, {
	},
};

static struct resource orion5x_uart0_resources[] = {
	{
		.start		= UART0_PHYS_BASE,
		.end		= UART0_PHYS_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IRQ_ORION5X_UART0,
		.end		= IRQ_ORION5X_UART0,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_uart0 = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= orion5x_uart0_data,
	},
	.resource		= orion5x_uart0_resources,
	.num_resources		= ARRAY_SIZE(orion5x_uart0_resources),
};

void __init orion5x_uart0_init(void)
{
	platform_device_register(&orion5x_uart0);
}


/*****************************************************************************
 * UART1
 ****************************************************************************/
static struct plat_serial8250_port orion5x_uart1_data[] = {
	{
		.mapbase	= UART1_PHYS_BASE,
		.membase	= (char *)UART1_VIRT_BASE,
		.irq		= IRQ_ORION5X_UART1,
		.flags		= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= ORION5X_TCLK,
	}, {
	},
};

static struct resource orion5x_uart1_resources[] = {
	{
		.start		= UART1_PHYS_BASE,
		.end		= UART1_PHYS_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IRQ_ORION5X_UART1,
		.end		= IRQ_ORION5X_UART1,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_uart1 = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM1,
	.dev			= {
		.platform_data	= orion5x_uart1_data,
	},
	.resource		= orion5x_uart1_resources,
	.num_resources		= ARRAY_SIZE(orion5x_uart1_resources),
};

void __init orion5x_uart1_init(void)
{
	platform_device_register(&orion5x_uart1);
}


/*****************************************************************************
 * XOR engine
 ****************************************************************************/
static struct resource orion5x_xor_shared_resources[] = {
	{
		.name	= "xor low",
		.start	= ORION5X_XOR_PHYS_BASE,
		.end	= ORION5X_XOR_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "xor high",
		.start	= ORION5X_XOR_PHYS_BASE + 0x200,
		.end	= ORION5X_XOR_PHYS_BASE + 0x2ff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device orion5x_xor_shared = {
	.name		= MV_XOR_SHARED_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_xor_shared_resources),
	.resource	= orion5x_xor_shared_resources,
};

static u64 orion5x_xor_dmamask = DMA_32BIT_MASK;

static struct resource orion5x_xor0_resources[] = {
	[0] = {
		.start	= IRQ_ORION5X_XOR0,
		.end	= IRQ_ORION5X_XOR0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data orion5x_xor0_data = {
	.shared		= &orion5x_xor_shared,
	.hw_id		= 0,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device orion5x_xor0_channel = {
	.name		= MV_XOR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_xor0_resources),
	.resource	= orion5x_xor0_resources,
	.dev		= {
		.dma_mask		= &orion5x_xor_dmamask,
		.coherent_dma_mask	= DMA_64BIT_MASK,
		.platform_data		= (void *)&orion5x_xor0_data,
	},
};

static struct resource orion5x_xor1_resources[] = {
	[0] = {
		.start	= IRQ_ORION5X_XOR1,
		.end	= IRQ_ORION5X_XOR1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data orion5x_xor1_data = {
	.shared		= &orion5x_xor_shared,
	.hw_id		= 1,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device orion5x_xor1_channel = {
	.name		= MV_XOR_NAME,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(orion5x_xor1_resources),
	.resource	= orion5x_xor1_resources,
	.dev		= {
		.dma_mask		= &orion5x_xor_dmamask,
		.coherent_dma_mask	= DMA_64BIT_MASK,
		.platform_data		= (void *)&orion5x_xor1_data,
	},
};

void __init orion5x_xor_init(void)
{
	platform_device_register(&orion5x_xor_shared);

	/*
	 * two engines can't do memset simultaneously, this limitation
	 * satisfied by removing memset support from one of the engines.
	 */
	dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
	dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
	platform_device_register(&orion5x_xor0_channel);

	dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
	dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
	dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
	platform_device_register(&orion5x_xor1_channel);
}


/*****************************************************************************
 * Time handling
 ****************************************************************************/
static void orion5x_timer_init(void)
{
	orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
}

struct sys_timer orion5x_timer = {
	.init = orion5x_timer_init,
};


/*****************************************************************************
 * General
 ****************************************************************************/
/*
 * Identify device ID and rev from PCIe configuration header space '0'.
 */
static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
{
	orion5x_pcie_id(dev, rev);

	if (*dev == MV88F5281_DEV_ID) {
		if (*rev == MV88F5281_REV_D2) {
			*dev_name = "MV88F5281-D2";
		} else if (*rev == MV88F5281_REV_D1) {
			*dev_name = "MV88F5281-D1";
		} else if (*rev == MV88F5281_REV_D0) {
			*dev_name = "MV88F5281-D0";
		} else {
			*dev_name = "MV88F5281-Rev-Unsupported";
		}
	} else if (*dev == MV88F5182_DEV_ID) {
		if (*rev == MV88F5182_REV_A2) {
			*dev_name = "MV88F5182-A2";
		} else {
			*dev_name = "MV88F5182-Rev-Unsupported";
		}
	} else if (*dev == MV88F5181_DEV_ID) {
		if (*rev == MV88F5181_REV_B1) {
			*dev_name = "MV88F5181-Rev-B1";
		} else if (*rev == MV88F5181L_REV_A1) {
			*dev_name = "MV88F5181L-Rev-A1";
		} else {
			*dev_name = "MV88F5181(L)-Rev-Unsupported";
		}
	} else {
		*dev_name = "Device-Unknown";
	}
}

void __init orion5x_init(void)
{
	char *dev_name;
	u32 dev, rev;

	orion5x_id(&dev, &rev, &dev_name);
	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK);

	/*
	 * Setup Orion address map
	 */
	orion5x_setup_cpu_mbus_bridge();

	/*
	 * Don't issue "Wait for Interrupt" instruction if we are
	 * running on D0 5281 silicon.
	 */
	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
		printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
		disable_hlt();
	}
}

/*
 * Many orion-based systems have buggy bootloader implementations.
 * This is a common fixup for bogus memory tags.
 */
void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
			    char **from, struct meminfo *meminfo)
{
	for (; t->hdr.size; t = tag_next(t))
		if (t->hdr.tag == ATAG_MEM &&
		    (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
		     t->u.mem.start & ~PAGE_MASK)) {
			printk(KERN_WARNING
			       "Clearing invalid memory bank %dKB@0x%08x\n",
			       t->u.mem.size / 1024, t->u.mem.start);
			t->hdr.tag = 0;
		}
}
Commit	Line	Data
585cf175	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/common.c
585cf175	3	*
9dd0b194	4	* Core functions for Marvell Orion 5x SoCs
585cf175 TP	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
585cf175 TP	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
ca26f7d3 TP	15	#include <linux/platform_device.h>
ca26f7d3 TP	16	#include <linux/serial_8250.h>
83b6d822	17	#include <linux/mbus.h>
e07c9d85	18	#include <linux/mv643xx_eth.h>
144aa3db	19	#include <linux/mv643xx_i2c.h>
15a32632	20	#include <linux/ata_platform.h>
585cf175	21	#include <asm/page.h>
be73a347	22	#include <asm/setup.h>
c67de5b3	23	#include <asm/timex.h>
be73a347	24	#include <asm/mach/arch.h>
585cf175	25	#include <asm/mach/map.h>
2bac1de2	26	#include <asm/mach/time.h>
a09e64fb RK	27	#include <mach/hardware.h>
a09e64fb RK	28	#include <mach/orion5x.h>
6f088f1d	29	#include <plat/ehci-orion.h>
1d5a1a6e	30	#include <plat/mv_xor.h>
6f088f1d LB	31	#include <plat/orion_nand.h>
6f088f1d LB	32	#include <plat/time.h>
585cf175 TP	33	#include "common.h"
	34
	35	/*****************************************************************************
	36	* I/O Address Mapping
	37	****************************************************************************/
9dd0b194	38	static struct map_desc orion5x_io_desc[] __initdata = {
585cf175	39	{
9dd0b194 LB	40	.virtual = ORION5X_REGS_VIRT_BASE,
	41	.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
	42	.length = ORION5X_REGS_SIZE,
e7068ad3 LB	43	.type = MT_DEVICE,
e7068ad3 LB	44	}, {
9dd0b194 LB	45	.virtual = ORION5X_PCIE_IO_VIRT_BASE,
	46	.pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
	47	.length = ORION5X_PCIE_IO_SIZE,
e7068ad3 LB	48	.type = MT_DEVICE,
e7068ad3 LB	49	}, {
9dd0b194 LB	50	.virtual = ORION5X_PCI_IO_VIRT_BASE,
	51	.pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
	52	.length = ORION5X_PCI_IO_SIZE,
e7068ad3 LB	53	.type = MT_DEVICE,
e7068ad3 LB	54	}, {
9dd0b194 LB	55	.virtual = ORION5X_PCIE_WA_VIRT_BASE,
	56	.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
	57	.length = ORION5X_PCIE_WA_SIZE,
e7068ad3	58	.type = MT_DEVICE,
585cf175 TP	59	},
	60	};
	61
9dd0b194	62	void __init orion5x_map_io(void)
585cf175	63	{
9dd0b194	64	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
585cf175	65	}
c67de5b3	66
044f6c7c	67
ca26f7d3	68	/*****************************************************************************
044f6c7c	69	* EHCI
ca26f7d3	70	****************************************************************************/
044f6c7c LB	71	static struct orion_ehci_data orion5x_ehci_data = {
044f6c7c LB	72	.dram = &orion5x_mbus_dram_info,
ca26f7d3 TP	73	};
ca26f7d3 TP	74
044f6c7c	75	static u64 ehci_dmamask = 0xffffffffUL;
ca26f7d3	76
ca26f7d3	77
044f6c7c LB	78	/*****************************************************************************
	79	* EHCI0
	80	****************************************************************************/
9dd0b194	81	static struct resource orion5x_ehci0_resources[] = {
ca26f7d3	82	{
9dd0b194	83	.start = ORION5X_USB0_PHYS_BASE,
994cab84	84	.end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
ca26f7d3	85	.flags = IORESOURCE_MEM,
e7068ad3	86	}, {
9dd0b194 LB	87	.start = IRQ_ORION5X_USB0_CTRL,
9dd0b194 LB	88	.end = IRQ_ORION5X_USB0_CTRL,
ca26f7d3 TP	89	.flags = IORESOURCE_IRQ,
	90	},
	91	};
	92
9dd0b194	93	static struct platform_device orion5x_ehci0 = {
ca26f7d3 TP	94	.name = "orion-ehci",
	95	.id = 0,
	96	.dev = {
	97	.dma_mask = &ehci_dmamask,
	98	.coherent_dma_mask = 0xffffffff,
9dd0b194	99	.platform_data = &orion5x_ehci_data,
ca26f7d3	100	},
9dd0b194 LB	101	.resource = orion5x_ehci0_resources,
9dd0b194 LB	102	.num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
ca26f7d3 TP	103	};
ca26f7d3 TP	104
044f6c7c LB	105	void __init orion5x_ehci0_init(void)
	106	{
	107	platform_device_register(&orion5x_ehci0);
	108	}
	109
	110
	111	/*****************************************************************************
	112	* EHCI1
	113	****************************************************************************/
	114	static struct resource orion5x_ehci1_resources[] = {
	115	{
	116	.start = ORION5X_USB1_PHYS_BASE,
	117	.end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
	118	.flags = IORESOURCE_MEM,
	119	}, {
	120	.start = IRQ_ORION5X_USB1_CTRL,
	121	.end = IRQ_ORION5X_USB1_CTRL,
	122	.flags = IORESOURCE_IRQ,
	123	},
	124	};
	125
9dd0b194	126	static struct platform_device orion5x_ehci1 = {
ca26f7d3 TP	127	.name = "orion-ehci",
	128	.id = 1,
	129	.dev = {
	130	.dma_mask = &ehci_dmamask,
	131	.coherent_dma_mask = 0xffffffff,
9dd0b194	132	.platform_data = &orion5x_ehci_data,
ca26f7d3	133	},
9dd0b194 LB	134	.resource = orion5x_ehci1_resources,
9dd0b194 LB	135	.num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
ca26f7d3 TP	136	};
ca26f7d3 TP	137
044f6c7c LB	138	void __init orion5x_ehci1_init(void)
	139	{
	140	platform_device_register(&orion5x_ehci1);
	141	}
	142
	143
e07c9d85	144	/*****************************************************************************
044f6c7c	145	* GigE
e07c9d85	146	****************************************************************************/
d236f5a5 LB	147	struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
d236f5a5 LB	148	.dram = &orion5x_mbus_dram_info,
b8c15a60	149	.t_clk = ORION5X_TCLK,
d236f5a5 LB	150	};
d236f5a5 LB	151
9dd0b194	152	static struct resource orion5x_eth_shared_resources[] = {
e07c9d85	153	{
9dd0b194 LB	154	.start = ORION5X_ETH_PHYS_BASE + 0x2000,
9dd0b194 LB	155	.end = ORION5X_ETH_PHYS_BASE + 0x3fff,
e07c9d85	156	.flags = IORESOURCE_MEM,
eeff6d86 LB	157	}, {
	158	.start = IRQ_ORION5X_ETH_ERR,
	159	.end = IRQ_ORION5X_ETH_ERR,
	160	.flags = IORESOURCE_IRQ,
e07c9d85 TP	161	},
	162	};
	163
9dd0b194	164	static struct platform_device orion5x_eth_shared = {
e07c9d85 TP	165	.name = MV643XX_ETH_SHARED_NAME,
e07c9d85 TP	166	.id = 0,
d236f5a5 LB	167	.dev = {
	168	.platform_data = &orion5x_eth_shared_data,
	169	},
eeff6d86	170	.num_resources = ARRAY_SIZE(orion5x_eth_shared_resources),
9dd0b194	171	.resource = orion5x_eth_shared_resources,
e07c9d85 TP	172	};
e07c9d85 TP	173
9dd0b194	174	static struct resource orion5x_eth_resources[] = {
e07c9d85 TP	175	{
e07c9d85 TP	176	.name = "eth irq",
9dd0b194 LB	177	.start = IRQ_ORION5X_ETH_SUM,
9dd0b194 LB	178	.end = IRQ_ORION5X_ETH_SUM,
e07c9d85	179	.flags = IORESOURCE_IRQ,
e7068ad3	180	},
e07c9d85 TP	181	};
e07c9d85 TP	182
9dd0b194	183	static struct platform_device orion5x_eth = {
e07c9d85 TP	184	.name = MV643XX_ETH_NAME,
	185	.id = 0,
	186	.num_resources = 1,
9dd0b194	187	.resource = orion5x_eth_resources,
e07c9d85 TP	188	};
e07c9d85 TP	189
9dd0b194	190	void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
e07c9d85	191	{
fa3959f4	192	eth_data->shared = &orion5x_eth_shared;
9dd0b194	193	orion5x_eth.dev.platform_data = eth_data;
fa3959f4	194
9dd0b194 LB	195	platform_device_register(&orion5x_eth_shared);
9dd0b194 LB	196	platform_device_register(&orion5x_eth);
e07c9d85 TP	197	}
e07c9d85 TP	198
044f6c7c	199
144aa3db	200	/*****************************************************************************
044f6c7c	201	* I2C
144aa3db	202	****************************************************************************/
9dd0b194	203	static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
144aa3db HVR	204	.freq_m = 8, /* assumes 166 MHz TCLK */
	205	.freq_n = 3,
	206	.timeout = 1000, /* Default timeout of 1 second */
	207	};
	208
9dd0b194	209	static struct resource orion5x_i2c_resources[] = {
144aa3db	210	{
e7068ad3 LB	211	.name = "i2c base",
e7068ad3 LB	212	.start = I2C_PHYS_BASE,
044f6c7c	213	.end = I2C_PHYS_BASE + 0x1f,
e7068ad3 LB	214	.flags = IORESOURCE_MEM,
	215	}, {
	216	.name = "i2c irq",
	217	.start = IRQ_ORION5X_I2C,
	218	.end = IRQ_ORION5X_I2C,
	219	.flags = IORESOURCE_IRQ,
144aa3db HVR	220	},
	221	};
	222
9dd0b194	223	static struct platform_device orion5x_i2c = {
144aa3db HVR	224	.name = MV64XXX_I2C_CTLR_NAME,
144aa3db HVR	225	.id = 0,
9dd0b194 LB	226	.num_resources = ARRAY_SIZE(orion5x_i2c_resources),
9dd0b194 LB	227	.resource = orion5x_i2c_resources,
144aa3db	228	.dev = {
e7068ad3	229	.platform_data = &orion5x_i2c_pdata,
144aa3db HVR	230	},
	231	};
	232
044f6c7c LB	233	void __init orion5x_i2c_init(void)
	234	{
	235	platform_device_register(&orion5x_i2c);
	236	}
	237
	238
f244baa3	239	/*****************************************************************************
044f6c7c	240	* SATA
f244baa3	241	****************************************************************************/
9dd0b194	242	static struct resource orion5x_sata_resources[] = {
f244baa3	243	{
e7068ad3 LB	244	.name = "sata base",
	245	.start = ORION5X_SATA_PHYS_BASE,
	246	.end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
	247	.flags = IORESOURCE_MEM,
	248	}, {
	249	.name = "sata irq",
	250	.start = IRQ_ORION5X_SATA,
	251	.end = IRQ_ORION5X_SATA,
	252	.flags = IORESOURCE_IRQ,
	253	},
f244baa3 SB	254	};
f244baa3 SB	255
9dd0b194	256	static struct platform_device orion5x_sata = {
e7068ad3 LB	257	.name = "sata_mv",
e7068ad3 LB	258	.id = 0,
f244baa3 SB	259	.dev = {
	260	.coherent_dma_mask = 0xffffffff,
	261	},
e7068ad3 LB	262	.num_resources = ARRAY_SIZE(orion5x_sata_resources),
e7068ad3 LB	263	.resource = orion5x_sata_resources,
f244baa3 SB	264	};
f244baa3 SB	265
9dd0b194	266	void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
f244baa3	267	{
9dd0b194 LB	268	sata_data->dram = &orion5x_mbus_dram_info;
	269	orion5x_sata.dev.platform_data = sata_data;
	270	platform_device_register(&orion5x_sata);
f244baa3 SB	271	}
f244baa3 SB	272
044f6c7c	273
2bac1de2	274	/*****************************************************************************
044f6c7c LB	275	* UART0
	276	****************************************************************************/
	277	static struct plat_serial8250_port orion5x_uart0_data[] = {
	278	{
	279	.mapbase = UART0_PHYS_BASE,
	280	.membase = (char *)UART0_VIRT_BASE,
	281	.irq = IRQ_ORION5X_UART0,
	282	.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
	283	.iotype = UPIO_MEM,
	284	.regshift = 2,
	285	.uartclk = ORION5X_TCLK,
	286	}, {
	287	},
	288	};
	289
	290	static struct resource orion5x_uart0_resources[] = {
	291	{
	292	.start = UART0_PHYS_BASE,
	293	.end = UART0_PHYS_BASE + 0xff,
	294	.flags = IORESOURCE_MEM,
	295	}, {
	296	.start = IRQ_ORION5X_UART0,
	297	.end = IRQ_ORION5X_UART0,
	298	.flags = IORESOURCE_IRQ,
	299	},
	300	};
	301
	302	static struct platform_device orion5x_uart0 = {
	303	.name = "serial8250",
	304	.id = PLAT8250_DEV_PLATFORM,
	305	.dev = {
	306	.platform_data = orion5x_uart0_data,
	307	},
	308	.resource = orion5x_uart0_resources,
	309	.num_resources = ARRAY_SIZE(orion5x_uart0_resources),
	310	};
	311
	312	void __init orion5x_uart0_init(void)
	313	{
	314	platform_device_register(&orion5x_uart0);
	315	}
	316
	317
	318	/*****************************************************************************
	319	* UART1
2bac1de2	320	****************************************************************************/
044f6c7c LB	321	static struct plat_serial8250_port orion5x_uart1_data[] = {
	322	{
	323	.mapbase = UART1_PHYS_BASE,
	324	.membase = (char *)UART1_VIRT_BASE,
	325	.irq = IRQ_ORION5X_UART1,
	326	.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
	327	.iotype = UPIO_MEM,
	328	.regshift = 2,
	329	.uartclk = ORION5X_TCLK,
	330	}, {
	331	},
	332	};
	333
	334	static struct resource orion5x_uart1_resources[] = {
	335	{
	336	.start = UART1_PHYS_BASE,
	337	.end = UART1_PHYS_BASE + 0xff,
	338	.flags = IORESOURCE_MEM,
	339	}, {
	340	.start = IRQ_ORION5X_UART1,
	341	.end = IRQ_ORION5X_UART1,
	342	.flags = IORESOURCE_IRQ,
	343	},
	344	};
	345
	346	static struct platform_device orion5x_uart1 = {
	347	.name = "serial8250",
	348	.id = PLAT8250_DEV_PLATFORM1,
	349	.dev = {
	350	.platform_data = orion5x_uart1_data,
	351	},
	352	.resource = orion5x_uart1_resources,
	353	.num_resources = ARRAY_SIZE(orion5x_uart1_resources),
	354	};
	355
	356	void __init orion5x_uart1_init(void)
	357	{
	358	platform_device_register(&orion5x_uart1);
	359	}
2bac1de2	360
044f6c7c	361
1d5a1a6e SB	362	/*****************************************************************************
	363	* XOR engine
	364	****************************************************************************/
	365	static struct resource orion5x_xor_shared_resources[] = {
	366	{
	367	.name = "xor low",
	368	.start = ORION5X_XOR_PHYS_BASE,
	369	.end = ORION5X_XOR_PHYS_BASE + 0xff,
	370	.flags = IORESOURCE_MEM,
	371	}, {
	372	.name = "xor high",
	373	.start = ORION5X_XOR_PHYS_BASE + 0x200,
	374	.end = ORION5X_XOR_PHYS_BASE + 0x2ff,
	375	.flags = IORESOURCE_MEM,
	376	},
	377	};
	378
	379	static struct platform_device orion5x_xor_shared = {
	380	.name = MV_XOR_SHARED_NAME,
	381	.id = 0,
	382	.num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
	383	.resource = orion5x_xor_shared_resources,
	384	};
	385
	386	static u64 orion5x_xor_dmamask = DMA_32BIT_MASK;
	387
	388	static struct resource orion5x_xor0_resources[] = {
	389	[0] = {
	390	.start = IRQ_ORION5X_XOR0,
	391	.end = IRQ_ORION5X_XOR0,
	392	.flags = IORESOURCE_IRQ,
	393	},
	394	};
	395
	396	static struct mv_xor_platform_data orion5x_xor0_data = {
	397	.shared = &orion5x_xor_shared,
	398	.hw_id = 0,
	399	.pool_size = PAGE_SIZE,
	400	};
	401
	402	static struct platform_device orion5x_xor0_channel = {
	403	.name = MV_XOR_NAME,
	404	.id = 0,
	405	.num_resources = ARRAY_SIZE(orion5x_xor0_resources),
	406	.resource = orion5x_xor0_resources,
	407	.dev = {
	408	.dma_mask = &orion5x_xor_dmamask,
	409	.coherent_dma_mask = DMA_64BIT_MASK,
	410	.platform_data = (void *)&orion5x_xor0_data,
	411	},
	412	};
	413
	414	static struct resource orion5x_xor1_resources[] = {
	415	[0] = {
	416	.start = IRQ_ORION5X_XOR1,
	417	.end = IRQ_ORION5X_XOR1,
	418	.flags = IORESOURCE_IRQ,
	419	},
	420	};
	421
	422	static struct mv_xor_platform_data orion5x_xor1_data = {
	423	.shared = &orion5x_xor_shared,
	424	.hw_id = 1,
	425	.pool_size = PAGE_SIZE,
426	};
427
428	static struct platform_device orion5x_xor1_channel = {
429	.name = MV_XOR_NAME,
430	.id = 1,
431	.num_resources = ARRAY_SIZE(orion5x_xor1_resources),
432	.resource = orion5x_xor1_resources,
433	.dev = {
434	.dma_mask = &orion5x_xor_dmamask,
435	.coherent_dma_mask = DMA_64BIT_MASK,
436	.platform_data = (void *)&orion5x_xor1_data,
437	},
438	};
439
440	void __init orion5x_xor_init(void)
441	{
442	platform_device_register(&orion5x_xor_shared);
443
444	/*
445	* two engines can't do memset simultaneously, this limitation
446	* satisfied by removing memset support from one of the engines.
447	*/
448	dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
449	dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
450	platform_device_register(&orion5x_xor0_channel);
451
452	dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
453	dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
454	dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
455	platform_device_register(&orion5x_xor1_channel);
456	}
457
458
044f6c7c LB	459	/*****************************************************************************
	460	* Time handling
	461	****************************************************************************/
9dd0b194	462	static void orion5x_timer_init(void)
2bac1de2	463	{
9dd0b194	464	orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
2bac1de2 LB	465	}
2bac1de2 LB	466
9dd0b194	467	struct sys_timer orion5x_timer = {
e7068ad3	468	.init = orion5x_timer_init,
2bac1de2 LB	469	};
2bac1de2 LB	470
044f6c7c	471
c67de5b3 TP	472	/*****************************************************************************
	473	* General
	474	****************************************************************************/
c67de5b3	475	/*
b46926bb	476	* Identify device ID and rev from PCIe configuration header space '0'.
c67de5b3	477	*/
9dd0b194	478	static void __init orion5x_id(u32 dev, u32 rev, char **dev_name)
c67de5b3	479	{
9dd0b194	480	orion5x_pcie_id(dev, rev);
c67de5b3 TP	481
	482	if (*dev == MV88F5281_DEV_ID) {
	483	if (*rev == MV88F5281_REV_D2) {
	484	*dev_name = "MV88F5281-D2";
	485	} else if (*rev == MV88F5281_REV_D1) {
	486	*dev_name = "MV88F5281-D1";
ce72e36e LB	487	} else if (*rev == MV88F5281_REV_D0) {
ce72e36e LB	488	*dev_name = "MV88F5281-D0";
c67de5b3 TP	489	} else {
	490	*dev_name = "MV88F5281-Rev-Unsupported";
	491	}
	492	} else if (*dev == MV88F5182_DEV_ID) {
	493	if (*rev == MV88F5182_REV_A2) {
	494	*dev_name = "MV88F5182-A2";
	495	} else {
	496	*dev_name = "MV88F5182-Rev-Unsupported";
	497	}
c9e3de94 HVR	498	} else if (*dev == MV88F5181_DEV_ID) {
	499	if (*rev == MV88F5181_REV_B1) {
	500	*dev_name = "MV88F5181-Rev-B1";
d2b2a6bb LB	501	} else if (*rev == MV88F5181L_REV_A1) {
d2b2a6bb LB	502	*dev_name = "MV88F5181L-Rev-A1";
c9e3de94	503	} else {
d2b2a6bb	504	*dev_name = "MV88F5181(L)-Rev-Unsupported";
c9e3de94	505	}
c67de5b3 TP	506	} else {
	507	*dev_name = "Device-Unknown";
	508	}
	509	}
	510
9dd0b194	511	void __init orion5x_init(void)
c67de5b3 TP	512	{
	513	char *dev_name;
	514	u32 dev, rev;
	515
9dd0b194 LB	516	orion5x_id(&dev, &rev, &dev_name);
9dd0b194 LB	517	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK);
c67de5b3 TP	518
	519	/*
	520	* Setup Orion address map
	521	*/
9dd0b194	522	orion5x_setup_cpu_mbus_bridge();
ce72e36e LB	523
	524	/*
	525	* Don't issue "Wait for Interrupt" instruction if we are
	526	* running on D0 5281 silicon.
	527	*/
	528	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
	529	printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
	530	disable_hlt();
	531	}
c67de5b3	532	}
be73a347 GL	533
	534	/*
	535	* Many orion-based systems have buggy bootloader implementations.
	536	* This is a common fixup for bogus memory tags.
	537	*/
	538	void __init tag_fixup_mem32(struct machine_desc mdesc, struct tag t,
	539	char *from, struct meminfo meminfo)
	540	{
	541	for (; t->hdr.size; t = tag_next(t))
	542	if (t->hdr.tag == ATAG_MEM &&
	543	(!t->u.mem.size \|\| t->u.mem.size & ~PAGE_MASK \|\|
	544	t->u.mem.start & ~PAGE_MASK)) {
	545	printk(KERN_WARNING
	546	"Clearing invalid memory bank %dKB@0x%08x\n",
	547	t->u.mem.size / 1024, t->u.mem.start);
	548	t->hdr.tag = 0;
	549	}
	550	}