Commit | Line | Data |
---|---|---|
038ee083 TP |
1 | /* |
2 | * arch/arm/mach-orion/pci.c | |
3 | * | |
4 | * PCI and PCIE functions for Marvell Orion System On Chip | |
5 | * | |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
1f2223b1 | 15 | #include <linux/mbus.h> |
038ee083 | 16 | #include <asm/mach/pci.h> |
abc0197d | 17 | #include <asm/plat-orion/pcie.h> |
038ee083 TP |
18 | #include "common.h" |
19 | ||
20 | /***************************************************************************** | |
21 | * Orion has one PCIE controller and one PCI controller. | |
22 | * | |
23 | * Note1: The local PCIE bus number is '0'. The local PCI bus number | |
24 | * follows the scanned PCIE bridged busses, if any. | |
25 | * | |
26 | * Note2: It is possible for PCI/PCIE agents to access many subsystem's | |
27 | * space, by configuring BARs and Address Decode Windows, e.g. flashes on | |
28 | * device bus, Orion registers, etc. However this code only enable the | |
29 | * access to DDR banks. | |
30 | ****************************************************************************/ | |
31 | ||
32 | ||
33 | /***************************************************************************** | |
34 | * PCIE controller | |
35 | ****************************************************************************/ | |
abc0197d | 36 | #define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) |
038ee083 | 37 | |
a9984270 | 38 | void __init orion_pcie_id(u32 *dev, u32 *rev) |
038ee083 | 39 | { |
abc0197d LB |
40 | *dev = orion_pcie_dev_id(PCIE_BASE); |
41 | *rev = orion_pcie_rev(PCIE_BASE); | |
038ee083 TP |
42 | } |
43 | ||
abc0197d | 44 | int orion_pcie_local_bus_nr(void) |
1f2223b1 | 45 | { |
abc0197d | 46 | return orion_pcie_get_local_bus_nr(PCIE_BASE); |
1f2223b1 LB |
47 | } |
48 | ||
abc0197d | 49 | static int pcie_valid_config(int bus, int dev) |
038ee083 TP |
50 | { |
51 | /* | |
52 | * Don't go out when trying to access -- | |
abc0197d | 53 | * 1. our own device / nonexisting device on local bus |
038ee083 | 54 | * 2. where there's no device connected (no link) |
038ee083 | 55 | */ |
abc0197d | 56 | if (bus == 0 && dev != 1) |
038ee083 TP |
57 | return 0; |
58 | ||
abc0197d | 59 | if (!orion_pcie_link_up(PCIE_BASE)) |
038ee083 TP |
60 | return 0; |
61 | ||
62 | return 1; | |
63 | } | |
64 | ||
abc0197d LB |
65 | |
66 | /* | |
67 | * PCIE config cycles are done by programming the PCIE_CONF_ADDR register | |
68 | * and then reading the PCIE_CONF_DATA register. Need to make sure these | |
69 | * transactions are atomic. | |
70 | */ | |
71 | static DEFINE_SPINLOCK(orion_pcie_lock); | |
72 | ||
73 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | |
74 | int size, u32 *val) | |
038ee083 TP |
75 | { |
76 | unsigned long flags; | |
abc0197d | 77 | int ret; |
038ee083 | 78 | |
abc0197d | 79 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
038ee083 TP |
80 | *val = 0xffffffff; |
81 | return PCIBIOS_DEVICE_NOT_FOUND; | |
82 | } | |
83 | ||
84 | spin_lock_irqsave(&orion_pcie_lock, flags); | |
abc0197d LB |
85 | ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); |
86 | spin_unlock_irqrestore(&orion_pcie_lock, flags); | |
038ee083 | 87 | |
abc0197d LB |
88 | return ret; |
89 | } | |
038ee083 | 90 | |
abc0197d LB |
91 | static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, |
92 | int where, int size, u32 *val) | |
93 | { | |
94 | int ret; | |
038ee083 | 95 | |
abc0197d LB |
96 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
97 | *val = 0xffffffff; | |
98 | return PCIBIOS_DEVICE_NOT_FOUND; | |
99 | } | |
038ee083 | 100 | |
abc0197d LB |
101 | /* |
102 | * We only support access to the non-extended configuration | |
103 | * space when using the WA access method (or we would have to | |
104 | * sacrifice 256M of CPU virtual address space.) | |
105 | */ | |
106 | if (where >= 0x100) { | |
107 | *val = 0xffffffff; | |
108 | return PCIBIOS_DEVICE_NOT_FOUND; | |
109 | } | |
038ee083 | 110 | |
abc0197d LB |
111 | ret = orion_pcie_rd_conf_wa((void __iomem *)ORION_PCIE_WA_VIRT_BASE, |
112 | bus, devfn, where, size, val); | |
038ee083 | 113 | |
abc0197d LB |
114 | return ret; |
115 | } | |
038ee083 | 116 | |
abc0197d LB |
117 | static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
118 | int where, int size, u32 val) | |
038ee083 TP |
119 | { |
120 | unsigned long flags; | |
121 | int ret; | |
122 | ||
abc0197d | 123 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) |
038ee083 TP |
124 | return PCIBIOS_DEVICE_NOT_FOUND; |
125 | ||
126 | spin_lock_irqsave(&orion_pcie_lock, flags); | |
abc0197d | 127 | ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); |
038ee083 TP |
128 | spin_unlock_irqrestore(&orion_pcie_lock, flags); |
129 | ||
130 | return ret; | |
131 | } | |
132 | ||
abc0197d LB |
133 | struct pci_ops pcie_ops = { |
134 | .read = pcie_rd_conf, | |
135 | .write = pcie_wr_conf, | |
038ee083 TP |
136 | }; |
137 | ||
138 | ||
a9984270 | 139 | static int __init pcie_setup(struct pci_sys_data *sys) |
038ee083 TP |
140 | { |
141 | struct resource *res; | |
abc0197d | 142 | int dev; |
038ee083 | 143 | |
1f2223b1 | 144 | /* |
abc0197d | 145 | * Generic PCIe unit setup. |
038ee083 | 146 | */ |
abc0197d | 147 | orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info); |
038ee083 TP |
148 | |
149 | /* | |
abc0197d LB |
150 | * Check whether to apply Orion-1/Orion-NAS PCIe config |
151 | * read transaction workaround. | |
038ee083 | 152 | */ |
abc0197d LB |
153 | dev = orion_pcie_dev_id(PCIE_BASE); |
154 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { | |
155 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " | |
156 | "read transaction workaround\n"); | |
157 | pcie_ops.read = pcie_rd_conf_wa; | |
158 | } | |
038ee083 TP |
159 | |
160 | /* | |
abc0197d | 161 | * Request resources. |
038ee083 TP |
162 | */ |
163 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | |
164 | if (!res) | |
abc0197d | 165 | panic("pcie_setup unable to alloc resources"); |
038ee083 TP |
166 | |
167 | /* | |
168 | * IORESOURCE_IO | |
169 | */ | |
170 | res[0].name = "PCI-EX I/O Space"; | |
171 | res[0].flags = IORESOURCE_IO; | |
7f74c2c7 | 172 | res[0].start = ORION_PCIE_IO_BUS_BASE; |
038ee083 TP |
173 | res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; |
174 | if (request_resource(&ioport_resource, &res[0])) | |
175 | panic("Request PCIE IO resource failed\n"); | |
176 | sys->resource[0] = &res[0]; | |
177 | ||
178 | /* | |
179 | * IORESOURCE_MEM | |
180 | */ | |
181 | res[1].name = "PCI-EX Memory Space"; | |
182 | res[1].flags = IORESOURCE_MEM; | |
7f74c2c7 | 183 | res[1].start = ORION_PCIE_MEM_PHYS_BASE; |
038ee083 TP |
184 | res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; |
185 | if (request_resource(&iomem_resource, &res[1])) | |
186 | panic("Request PCIE Memory resource failed\n"); | |
187 | sys->resource[1] = &res[1]; | |
188 | ||
189 | sys->resource[2] = NULL; | |
190 | sys->io_offset = 0; | |
191 | ||
192 | return 1; | |
193 | } | |
194 | ||
195 | /***************************************************************************** | |
196 | * PCI controller | |
197 | ****************************************************************************/ | |
198 | #define PCI_MODE ORION_PCI_REG(0xd00) | |
199 | #define PCI_CMD ORION_PCI_REG(0xc00) | |
200 | #define PCI_P2P_CONF ORION_PCI_REG(0x1d14) | |
201 | #define PCI_CONF_ADDR ORION_PCI_REG(0xc78) | |
202 | #define PCI_CONF_DATA ORION_PCI_REG(0xc7c) | |
203 | ||
204 | /* | |
205 | * PCI_MODE bits | |
206 | */ | |
207 | #define PCI_MODE_64BIT (1 << 2) | |
208 | #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) | |
209 | ||
210 | /* | |
211 | * PCI_CMD bits | |
212 | */ | |
213 | #define PCI_CMD_HOST_REORDER (1 << 29) | |
214 | ||
215 | /* | |
216 | * PCI_P2P_CONF bits | |
217 | */ | |
218 | #define PCI_P2P_BUS_OFFS 16 | |
219 | #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) | |
220 | #define PCI_P2P_DEV_OFFS 24 | |
221 | #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) | |
222 | ||
223 | /* | |
224 | * PCI_CONF_ADDR bits | |
225 | */ | |
226 | #define PCI_CONF_REG(reg) ((reg) & 0xfc) | |
227 | #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) | |
228 | #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) | |
229 | #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) | |
230 | #define PCI_CONF_ADDR_EN (1 << 31) | |
231 | ||
232 | /* | |
233 | * Internal configuration space | |
234 | */ | |
235 | #define PCI_CONF_FUNC_STAT_CMD 0 | |
236 | #define PCI_CONF_REG_STAT_CMD 4 | |
237 | #define PCIX_STAT 0x64 | |
238 | #define PCIX_STAT_BUS_OFFS 8 | |
239 | #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) | |
240 | ||
1f2223b1 LB |
241 | /* |
242 | * PCI Address Decode Windows registers | |
243 | */ | |
244 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ | |
245 | ((n) == 1) ? ORION_PCI_REG(0xd08) : \ | |
246 | ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ | |
247 | ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) | |
248 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ | |
249 | ((n) == 1) ? ORION_PCI_REG(0xd48) : \ | |
250 | ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ | |
251 | ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) | |
252 | #define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) | |
253 | #define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) | |
254 | ||
255 | /* | |
256 | * PCI configuration helpers for BAR settings | |
257 | */ | |
258 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) | |
259 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) | |
260 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) | |
261 | ||
038ee083 TP |
262 | /* |
263 | * PCI config cycles are done by programming the PCI_CONF_ADDR register | |
264 | * and then reading the PCI_CONF_DATA register. Need to make sure these | |
265 | * transactions are atomic. | |
266 | */ | |
267 | static DEFINE_SPINLOCK(orion_pci_lock); | |
268 | ||
abc0197d | 269 | int orion_pci_local_bus_nr(void) |
038ee083 TP |
270 | { |
271 | u32 conf = orion_read(PCI_P2P_CONF); | |
272 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); | |
273 | } | |
274 | ||
abc0197d | 275 | static int orion_pci_local_dev_nr(void) |
038ee083 TP |
276 | { |
277 | u32 conf = orion_read(PCI_P2P_CONF); | |
278 | return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); | |
279 | } | |
280 | ||
abc0197d | 281 | static int orion_pci_hw_rd_conf(int bus, int dev, u32 func, |
038ee083 TP |
282 | u32 where, u32 size, u32 *val) |
283 | { | |
284 | unsigned long flags; | |
285 | spin_lock_irqsave(&orion_pci_lock, flags); | |
286 | ||
287 | orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | |
288 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | |
289 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | |
290 | ||
291 | *val = orion_read(PCI_CONF_DATA); | |
292 | ||
293 | if (size == 1) | |
294 | *val = (*val >> (8*(where & 0x3))) & 0xff; | |
295 | else if (size == 2) | |
296 | *val = (*val >> (8*(where & 0x3))) & 0xffff; | |
297 | ||
298 | spin_unlock_irqrestore(&orion_pci_lock, flags); | |
299 | ||
300 | return PCIBIOS_SUCCESSFUL; | |
301 | } | |
302 | ||
abc0197d | 303 | static int orion_pci_hw_wr_conf(int bus, int dev, u32 func, |
038ee083 TP |
304 | u32 where, u32 size, u32 val) |
305 | { | |
306 | unsigned long flags; | |
307 | int ret = PCIBIOS_SUCCESSFUL; | |
308 | ||
309 | spin_lock_irqsave(&orion_pci_lock, flags); | |
310 | ||
311 | orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | |
312 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | |
313 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | |
314 | ||
315 | if (size == 4) { | |
316 | __raw_writel(val, PCI_CONF_DATA); | |
317 | } else if (size == 2) { | |
318 | __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); | |
319 | } else if (size == 1) { | |
320 | __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); | |
321 | } else { | |
322 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | |
323 | } | |
324 | ||
325 | spin_unlock_irqrestore(&orion_pci_lock, flags); | |
326 | ||
327 | return ret; | |
328 | } | |
329 | ||
330 | static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, | |
331 | int where, int size, u32 *val) | |
332 | { | |
333 | /* | |
334 | * Don't go out for local device | |
335 | */ | |
336 | if ((orion_pci_local_bus_nr() == bus->number) && | |
337 | (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) { | |
338 | *val = 0xffffffff; | |
339 | return PCIBIOS_DEVICE_NOT_FOUND; | |
340 | } | |
341 | ||
342 | return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), | |
343 | PCI_FUNC(devfn), where, size, val); | |
344 | } | |
345 | ||
346 | static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, | |
347 | int where, int size, u32 val) | |
348 | { | |
349 | /* | |
350 | * Don't go out for local device | |
351 | */ | |
352 | if ((orion_pci_local_bus_nr() == bus->number) && | |
353 | (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) | |
354 | return PCIBIOS_DEVICE_NOT_FOUND; | |
355 | ||
356 | return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), | |
357 | PCI_FUNC(devfn), where, size, val); | |
358 | } | |
359 | ||
abc0197d | 360 | struct pci_ops pci_ops = { |
038ee083 TP |
361 | .read = orion_pci_rd_conf, |
362 | .write = orion_pci_wr_conf, | |
363 | }; | |
364 | ||
a9984270 | 365 | static void __init orion_pci_set_bus_nr(int nr) |
038ee083 TP |
366 | { |
367 | u32 p2p = orion_read(PCI_P2P_CONF); | |
368 | ||
369 | if (orion_read(PCI_MODE) & PCI_MODE_PCIX) { | |
370 | /* | |
371 | * PCI-X mode | |
372 | */ | |
373 | u32 pcix_status, bus, dev; | |
374 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; | |
375 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; | |
376 | orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); | |
377 | pcix_status &= ~PCIX_STAT_BUS_MASK; | |
378 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); | |
379 | orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); | |
380 | } else { | |
381 | /* | |
382 | * PCI Conventional mode | |
383 | */ | |
384 | p2p &= ~PCI_P2P_BUS_MASK; | |
385 | p2p |= (nr << PCI_P2P_BUS_OFFS); | |
386 | orion_write(PCI_P2P_CONF, p2p); | |
387 | } | |
388 | } | |
389 | ||
a9984270 | 390 | static void __init orion_pci_master_slave_enable(void) |
038ee083 | 391 | { |
abc0197d LB |
392 | int bus_nr, dev_nr, func, reg; |
393 | u32 val; | |
038ee083 TP |
394 | |
395 | bus_nr = orion_pci_local_bus_nr(); | |
396 | dev_nr = orion_pci_local_dev_nr(); | |
397 | func = PCI_CONF_FUNC_STAT_CMD; | |
398 | reg = PCI_CONF_REG_STAT_CMD; | |
399 | orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val); | |
400 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
401 | orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7); | |
402 | } | |
403 | ||
a9984270 | 404 | static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) |
1f2223b1 LB |
405 | { |
406 | u32 win_enable; | |
abc0197d LB |
407 | int bus; |
408 | int dev; | |
1f2223b1 LB |
409 | int i; |
410 | ||
411 | /* | |
412 | * First, disable windows. | |
413 | */ | |
414 | win_enable = 0xffffffff; | |
415 | orion_write(PCI_BAR_ENABLE, win_enable); | |
416 | ||
417 | /* | |
418 | * Setup windows for DDR banks. | |
419 | */ | |
420 | bus = orion_pci_local_bus_nr(); | |
421 | dev = orion_pci_local_dev_nr(); | |
422 | ||
423 | for (i = 0; i < dram->num_cs; i++) { | |
424 | struct mbus_dram_window *cs = dram->cs + i; | |
425 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); | |
426 | u32 reg; | |
427 | u32 val; | |
428 | ||
429 | /* | |
430 | * Write DRAM bank base address register. | |
431 | */ | |
432 | reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); | |
433 | orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); | |
434 | val = (cs->base & 0xfffff000) | (val & 0xfff); | |
435 | orion_pci_hw_wr_conf(bus, dev, func, reg, 4, val); | |
436 | ||
437 | /* | |
438 | * Write DRAM bank size register. | |
439 | */ | |
440 | reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); | |
441 | orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); | |
442 | orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), | |
443 | (cs->size - 1) & 0xfffff000); | |
444 | orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), | |
445 | cs->base & 0xfffff000); | |
446 | ||
447 | /* | |
448 | * Enable decode window for this chip select. | |
449 | */ | |
450 | win_enable &= ~(1 << cs->cs_index); | |
451 | } | |
452 | ||
453 | /* | |
454 | * Re-enable decode windows. | |
455 | */ | |
456 | orion_write(PCI_BAR_ENABLE, win_enable); | |
457 | ||
458 | /* | |
459 | * Disable automatic update of address remaping when writing to BARs. | |
460 | */ | |
461 | orion_setbits(PCI_ADDR_DECODE_CTRL, 1); | |
462 | } | |
463 | ||
a9984270 | 464 | static int __init pci_setup(struct pci_sys_data *sys) |
038ee083 TP |
465 | { |
466 | struct resource *res; | |
467 | ||
1f2223b1 LB |
468 | /* |
469 | * Point PCI unit MBUS decode windows to DRAM space. | |
470 | */ | |
471 | orion_setup_pci_wins(&orion_mbus_dram_info); | |
472 | ||
038ee083 TP |
473 | /* |
474 | * Master + Slave enable | |
475 | */ | |
476 | orion_pci_master_slave_enable(); | |
477 | ||
478 | /* | |
479 | * Force ordering | |
480 | */ | |
481 | orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); | |
482 | ||
483 | /* | |
484 | * Request resources | |
485 | */ | |
486 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | |
487 | if (!res) | |
abc0197d | 488 | panic("pci_setup unable to alloc resources"); |
038ee083 TP |
489 | |
490 | /* | |
491 | * IORESOURCE_IO | |
492 | */ | |
493 | res[0].name = "PCI I/O Space"; | |
494 | res[0].flags = IORESOURCE_IO; | |
7f74c2c7 | 495 | res[0].start = ORION_PCI_IO_BUS_BASE; |
038ee083 TP |
496 | res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; |
497 | if (request_resource(&ioport_resource, &res[0])) | |
498 | panic("Request PCI IO resource failed\n"); | |
499 | sys->resource[0] = &res[0]; | |
500 | ||
501 | /* | |
502 | * IORESOURCE_MEM | |
503 | */ | |
504 | res[1].name = "PCI Memory Space"; | |
505 | res[1].flags = IORESOURCE_MEM; | |
7f74c2c7 | 506 | res[1].start = ORION_PCI_MEM_PHYS_BASE; |
038ee083 TP |
507 | res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; |
508 | if (request_resource(&iomem_resource, &res[1])) | |
509 | panic("Request PCI Memory resource failed\n"); | |
510 | sys->resource[1] = &res[1]; | |
511 | ||
512 | sys->resource[2] = NULL; | |
513 | sys->io_offset = 0; | |
514 | ||
515 | return 1; | |
516 | } | |
517 | ||
518 | ||
519 | /***************************************************************************** | |
520 | * General PCIE + PCI | |
521 | ****************************************************************************/ | |
a9984270 | 522 | int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) |
038ee083 TP |
523 | { |
524 | int ret = 0; | |
525 | ||
526 | if (nr == 0) { | |
abc0197d LB |
527 | orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); |
528 | ret = pcie_setup(sys); | |
038ee083 | 529 | } else if (nr == 1) { |
abc0197d LB |
530 | orion_pci_set_bus_nr(sys->busnr); |
531 | ret = pci_setup(sys); | |
038ee083 TP |
532 | } |
533 | ||
534 | return ret; | |
535 | } | |
536 | ||
a9984270 | 537 | struct pci_bus __init *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) |
038ee083 | 538 | { |
038ee083 TP |
539 | struct pci_bus *bus; |
540 | ||
038ee083 | 541 | if (nr == 0) { |
abc0197d | 542 | bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); |
038ee083 | 543 | } else if (nr == 1) { |
abc0197d | 544 | bus = pci_scan_bus(sys->busnr, &pci_ops, sys); |
038ee083 | 545 | } else { |
038ee083 | 546 | bus = NULL; |
abc0197d | 547 | BUG(); |
038ee083 TP |
548 | } |
549 | ||
550 | return bus; | |
551 | } |