[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-orion / pci.c

/*
 * arch/arm/mach-orion/pci.c
 *
 * PCI and PCIE functions for Marvell Orion System On Chip
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under  the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
#include <asm/mach/pci.h>
#include "common.h"

/*****************************************************************************
 * Orion has one PCIE controller and one PCI controller.
 *
 * Note1: The local PCIE bus number is '0'. The local PCI bus number
 * follows the scanned PCIE bridged busses, if any.
 *
 * Note2: It is possible for PCI/PCIE agents to access many subsystem's
 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
 * device bus, Orion registers, etc. However this code only enable the
 * access to DDR banks.
 ****************************************************************************/


/*****************************************************************************
 * PCIE controller
 ****************************************************************************/
#define PCIE_CTRL		ORION_PCIE_REG(0x1a00)
#define PCIE_STAT		ORION_PCIE_REG(0x1a04)
#define PCIE_DEV_ID		ORION_PCIE_REG(0x0000)
#define PCIE_CMD_STAT		ORION_PCIE_REG(0x0004)
#define PCIE_DEV_REV		ORION_PCIE_REG(0x0008)
#define PCIE_MASK		ORION_PCIE_REG(0x1910)
#define PCIE_CONF_ADDR		ORION_PCIE_REG(0x18f8)
#define PCIE_CONF_DATA		ORION_PCIE_REG(0x18fc)

/*
 * PCIE_STAT bits
 */
#define PCIE_STAT_LINK_DOWN		1
#define PCIE_STAT_BUS_OFFS		8
#define PCIE_STAT_BUS_MASK		(0xff << PCIE_STAT_BUS_OFFS)
#define PCIE_STAT_DEV_OFFS		20
#define PCIE_STAT_DEV_MASK		(0x1f << PCIE_STAT_DEV_OFFS)

/*
 * PCIE_CONF_ADDR bits
 */
#define PCIE_CONF_REG(r)		((((r) & 0xf00) << 24) | ((r) & 0xfc))
#define PCIE_CONF_FUNC(f)		(((f) & 0x3) << 8)
#define PCIE_CONF_DEV(d)		(((d) & 0x1f) << 11)
#define PCIE_CONF_BUS(b)		(((b) & 0xff) << 16)
#define PCIE_CONF_ADDR_EN		(1 << 31)

/*
 * PCIE Address Decode Windows registers
 */
#define PCIE_BAR_CTRL(n)	ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
#define PCIE_BAR_LO(n)		ORION_PCIE_REG(0x0010 + ((n) * 8))
#define PCIE_BAR_HI(n)		ORION_PCIE_REG(0x0014 + ((n) * 8))
#define PCIE_WIN_CTRL(n)	(((n) < 5) ? \
					ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
					ORION_PCIE_REG(0x1880))
#define PCIE_WIN_BASE(n)	(((n) < 5) ? \
					ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
					ORION_PCIE_REG(0x1884))
#define PCIE_WIN_REMAP(n)	(((n) < 5) ? \
					ORION_PCIE_REG(0x182c + ((n) << 4)) : \
					ORION_PCIE_REG(0x188c))
#define PCIE_MAX_BARS		3
#define PCIE_MAX_WINS		6

/*
 * Use PCIE BAR '1' for all DDR banks
 */
#define PCIE_DRAM_BAR		1

/*
 * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion_pcie_lock);

void orion_pcie_id(u32 *dev, u32 *rev)
{
	*dev = orion_read(PCIE_DEV_ID) >> 16;
	*rev = orion_read(PCIE_DEV_REV) & 0xff;
}

u32 orion_pcie_local_bus_nr(void)
{
	u32 stat = orion_read(PCIE_STAT);
	return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS);
}

static u32 orion_pcie_local_dev_nr(void)
{
	u32 stat = orion_read(PCIE_STAT);
	return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS);
}

static u32 orion_pcie_no_link(void)
{
	u32 stat = orion_read(PCIE_STAT);
	return(stat & PCIE_STAT_LINK_DOWN);
}

static void orion_pcie_set_bus_nr(int nr)
{
	orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK);
	orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
}

/*
 * Setup PCIE BARs and Address Decode Wins:
 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
 * WIN[0-3] -> DRAM bank[0-3]
 */
static void orion_setup_pcie_wins(struct mbus_dram_target_info *dram)
{
	u32 size;
	int i;

	/*
	 * First, disable and clear BARs and windows
	 */
	for (i = 1; i < PCIE_MAX_BARS; i++) {
		writel(0, PCIE_BAR_CTRL(i));
		writel(0, PCIE_BAR_LO(i));
		writel(0, PCIE_BAR_HI(i));
	}

	for (i = 0; i < PCIE_MAX_WINS; i++) {
		writel(0, PCIE_WIN_CTRL(i));
		writel(0, PCIE_WIN_BASE(i));
		writel(0, PCIE_WIN_REMAP(i));
	}

	/*
	 * Setup windows for DDR banks. Count total DDR size on the fly.
	 */
	size = 0;
	for (i = 0; i < dram->num_cs; i++) {
		struct mbus_dram_window *cs = dram->cs + i;

		writel(cs->base & 0xffff0000, PCIE_WIN_BASE(i));
		writel(0, PCIE_WIN_REMAP(i));
		writel(((cs->size - 1) & 0xffff0000) |
			(cs->mbus_attr << 8) |
			(dram->mbus_dram_target_id << 4) |
			(PCIE_DRAM_BAR << 1) | 1, PCIE_WIN_CTRL(i));

		size += cs->size;
	}

	/*
	 * Setup BAR[1] to all DRAM banks
	 */
	writel(dram->cs[0].base, PCIE_BAR_LO(PCIE_DRAM_BAR));
	writel(0, PCIE_BAR_HI(PCIE_DRAM_BAR));
	writel(((size - 1) & 0xffff0000) | 1, PCIE_BAR_CTRL(PCIE_DRAM_BAR));
}

static void orion_pcie_master_slave_enable(void)
{
	orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER |
					  PCI_COMMAND_IO |
					  PCI_COMMAND_MEMORY);
}

static void orion_pcie_enable_interrupts(void)
{
	/*
	 * Enable interrupts lines
	 * INTA[24] INTB[25] INTC[26] INTD[27]
	 */
	orion_setbits(PCIE_MASK, 0xf<<24);
}

static int orion_pcie_valid_config(u32 bus, u32 dev)
{
	/*
	 * Don't go out when trying to access --
	 * 1. our own device
	 * 2. where there's no device connected (no link)
	 * 3. nonexisting devices on local bus
	 */

	if ((orion_pcie_local_bus_nr() == bus) &&
	   (orion_pcie_local_dev_nr() == dev))
		return 0;

	if (orion_pcie_no_link())
		return 0;

	if (bus == orion_pcie_local_bus_nr())
		if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) ||
		   ((orion_pcie_local_dev_nr() != 0) && (dev != 0)))
		return 0;

	return 1;
}

static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
						int size, u32 *val)
{
	unsigned long flags;
	unsigned int dev, rev, pcie_addr;

	if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&orion_pcie_lock, flags);

	orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
			PCIE_CONF_DEV(PCI_SLOT(devfn)) |
			PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
			PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);

	orion_pcie_id(&dev, &rev);
	if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
		/* extended register space */
		pcie_addr = ORION_PCIE_WA_VIRT_BASE;
		pcie_addr |= PCIE_CONF_BUS(bus->number) |
			PCIE_CONF_DEV(PCI_SLOT(devfn)) |
			PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
			PCIE_CONF_REG(where);
		*val = orion_read(pcie_addr);
	} else
		*val = orion_read(PCIE_CONF_DATA);

	if (size == 1)
		*val = (*val >> (8*(where & 0x3))) & 0xff;
	else if (size == 2)
		*val = (*val >> (8*(where & 0x3))) & 0xffff;

	spin_unlock_irqrestore(&orion_pcie_lock, flags);

	return PCIBIOS_SUCCESSFUL;
}


static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where,
						int size, u32 val)
{
	unsigned long flags;
	int ret;

	if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&orion_pcie_lock, flags);

	ret = PCIBIOS_SUCCESSFUL;

	orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
			PCIE_CONF_DEV(PCI_SLOT(devfn)) |
			PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
			PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);

	if (size == 4) {
		__raw_writel(val, PCIE_CONF_DATA);
	} else if (size == 2) {
		__raw_writew(val, PCIE_CONF_DATA + (where & 0x3));
	} else if (size == 1) {
		__raw_writeb(val, PCIE_CONF_DATA + (where & 0x3));
	} else {
		ret = PCIBIOS_BAD_REGISTER_NUMBER;
	}

	spin_unlock_irqrestore(&orion_pcie_lock, flags);

	return ret;
}

struct pci_ops orion_pcie_ops = {
	.read = orion_pcie_rd_conf,
	.write = orion_pcie_wr_conf,
};


static int orion_pcie_setup(struct pci_sys_data *sys)
{
	struct resource *res;

	/*
	 * Point PCIe unit MBUS decode windows to DRAM space.
	 */
	orion_setup_pcie_wins(&orion_mbus_dram_info);

	/*
	 * Master + Slave enable
	 */
	orion_pcie_master_slave_enable();

	/*
	 * Enable interrupts lines A-D
	 */
	orion_pcie_enable_interrupts();

	/*
	 * Request resource
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
		panic("orion_pci_setup unable to alloc resources");

	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCI-EX I/O Space";
	res[0].flags = IORESOURCE_IO;
	res[0].start = ORION_PCIE_IO_BUS_BASE;
	res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCIE IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCI-EX Memory Space";
	res[1].flags = IORESOURCE_MEM;
	res[1].start = ORION_PCIE_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCIE Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}

/*****************************************************************************
 * PCI controller
 ****************************************************************************/
#define PCI_MODE		ORION_PCI_REG(0xd00)
#define PCI_CMD			ORION_PCI_REG(0xc00)
#define PCI_P2P_CONF		ORION_PCI_REG(0x1d14)
#define PCI_CONF_ADDR		ORION_PCI_REG(0xc78)
#define PCI_CONF_DATA		ORION_PCI_REG(0xc7c)

/*
 * PCI_MODE bits
 */
#define PCI_MODE_64BIT			(1 << 2)
#define PCI_MODE_PCIX			((1 << 4) | (1 << 5))

/*
 * PCI_CMD bits
 */
#define PCI_CMD_HOST_REORDER		(1 << 29)

/*
 * PCI_P2P_CONF bits
 */
#define PCI_P2P_BUS_OFFS		16
#define PCI_P2P_BUS_MASK		(0xff << PCI_P2P_BUS_OFFS)
#define PCI_P2P_DEV_OFFS		24
#define PCI_P2P_DEV_MASK		(0x1f << PCI_P2P_DEV_OFFS)

/*
 * PCI_CONF_ADDR bits
 */
#define PCI_CONF_REG(reg)		((reg) & 0xfc)
#define PCI_CONF_FUNC(func)		(((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev)		(((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus)		(((bus) & 0xff) << 16)
#define PCI_CONF_ADDR_EN		(1 << 31)

/*
 * Internal configuration space
 */
#define PCI_CONF_FUNC_STAT_CMD		0
#define PCI_CONF_REG_STAT_CMD		4
#define PCIX_STAT			0x64
#define PCIX_STAT_BUS_OFFS		8
#define PCIX_STAT_BUS_MASK		(0xff << PCIX_STAT_BUS_OFFS)

/*
 * PCI Address Decode Windows registers
 */
#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION_PCI_REG(0xc08) : \
				((n) == 1) ? ORION_PCI_REG(0xd08) :  \
				((n) == 2) ? ORION_PCI_REG(0xc0c) :  \
				((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
#define PCI_BAR_REMAP_DDR_CS(n)	(((n) ==0) ? ORION_PCI_REG(0xc48) :  \
				((n) == 1) ? ORION_PCI_REG(0xd48) :  \
				((n) == 2) ? ORION_PCI_REG(0xc4c) :  \
				((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
#define PCI_BAR_ENABLE		ORION_PCI_REG(0xc3c)
#define PCI_ADDR_DECODE_CTRL	ORION_PCI_REG(0xd3c)

/*
 * PCI configuration helpers for BAR settings
 */
#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)

/*
 * PCI config cycles are done by programming the PCI_CONF_ADDR register
 * and then reading the PCI_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
static DEFINE_SPINLOCK(orion_pci_lock);

u32 orion_pci_local_bus_nr(void)
{
	u32 conf = orion_read(PCI_P2P_CONF);
	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
}

static u32 orion_pci_local_dev_nr(void)
{
	u32 conf = orion_read(PCI_P2P_CONF);
	return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
}

static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
					u32 where, u32 size, u32 *val)
{
	unsigned long flags;
	spin_lock_irqsave(&orion_pci_lock, flags);

	orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
			PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
			PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);

	*val = orion_read(PCI_CONF_DATA);

	if (size == 1)
		*val = (*val >> (8*(where & 0x3))) & 0xff;
	else if (size == 2)
		*val = (*val >> (8*(where & 0x3))) & 0xffff;

	spin_unlock_irqrestore(&orion_pci_lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
					u32 where, u32 size, u32 val)
{
	unsigned long flags;
	int ret = PCIBIOS_SUCCESSFUL;

	spin_lock_irqsave(&orion_pci_lock, flags);

	orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
			PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
			PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);

	if (size == 4) {
		__raw_writel(val, PCI_CONF_DATA);
	} else if (size == 2) {
		__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	} else if (size == 1) {
		__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	} else {
		ret = PCIBIOS_BAD_REGISTER_NUMBER;
	}

	spin_unlock_irqrestore(&orion_pci_lock, flags);

	return ret;
}

static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 *val)
{
	/*
	 * Don't go out for local device
	 */
	if ((orion_pci_local_bus_nr() == bus->number) &&
	   (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
				int where, int size, u32 val)
{
	/*
	 * Don't go out for local device
	 */
	if ((orion_pci_local_bus_nr() == bus->number) &&
	   (orion_pci_local_dev_nr() == PCI_SLOT(devfn)))
		return PCIBIOS_DEVICE_NOT_FOUND;

	return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
					PCI_FUNC(devfn), where, size, val);
}

struct pci_ops orion_pci_ops = {
	.read = orion_pci_rd_conf,
	.write = orion_pci_wr_conf,
};

static void orion_pci_set_bus_nr(int nr)
{
	u32 p2p = orion_read(PCI_P2P_CONF);

	if (orion_read(PCI_MODE) & PCI_MODE_PCIX) {
		/*
		 * PCI-X mode
		 */
		u32 pcix_status, bus, dev;
		bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
		dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
		orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
		pcix_status &= ~PCIX_STAT_BUS_MASK;
		pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
		orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
	} else {
		/*
		 * PCI Conventional mode
		 */
		p2p &= ~PCI_P2P_BUS_MASK;
		p2p |= (nr << PCI_P2P_BUS_OFFS);
		orion_write(PCI_P2P_CONF, p2p);
	}
}

static void orion_pci_master_slave_enable(void)
{
	u32 bus_nr, dev_nr, func, reg, val;

	bus_nr = orion_pci_local_bus_nr();
	dev_nr = orion_pci_local_dev_nr();
	func = PCI_CONF_FUNC_STAT_CMD;
	reg = PCI_CONF_REG_STAT_CMD;
	orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val);
	val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
	orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7);
}

static void orion_setup_pci_wins(struct mbus_dram_target_info *dram)
{
	u32 win_enable;
	u32 bus;
	u32 dev;
	int i;

	/*
	 * First, disable windows.
	 */
	win_enable = 0xffffffff;
	orion_write(PCI_BAR_ENABLE, win_enable);

	/*
	 * Setup windows for DDR banks.
	 */
	bus = orion_pci_local_bus_nr();
	dev = orion_pci_local_dev_nr();

	for (i = 0; i < dram->num_cs; i++) {
		struct mbus_dram_window *cs = dram->cs + i;
		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
		u32 reg;
		u32 val;

		/*
		 * Write DRAM bank base address register.
		 */
		reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
		orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
		val = (cs->base & 0xfffff000) | (val & 0xfff);
		orion_pci_hw_wr_conf(bus, dev, func, reg, 4, val);

		/*
		 * Write DRAM bank size register.
		 */
		reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
		orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
		orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
				(cs->size - 1) & 0xfffff000);
		orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
				cs->base & 0xfffff000);

		/*
		 * Enable decode window for this chip select.
		 */
		win_enable &= ~(1 << cs->cs_index);
	}

	/*
	 * Re-enable decode windows.
	 */
	orion_write(PCI_BAR_ENABLE, win_enable);

	/*
	 * Disable automatic update of address remaping when writing to BARs.
	 */
	orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
}

static int orion_pci_setup(struct pci_sys_data *sys)
{
	struct resource *res;

	/*
	 * Point PCI unit MBUS decode windows to DRAM space.
	 */
	orion_setup_pci_wins(&orion_mbus_dram_info);

	/*
	 * Master + Slave enable
	 */
	orion_pci_master_slave_enable();

	/*
	 * Force ordering
	 */
	orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);

	/*
	 * Request resources
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
		panic("orion_pci_setup unable to alloc resources");

	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCI I/O Space";
	res[0].flags = IORESOURCE_IO;
	res[0].start = ORION_PCI_IO_BUS_BASE;
	res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCI IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCI Memory Space";
	res[1].flags = IORESOURCE_MEM;
	res[1].start = ORION_PCI_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCI Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}


/*****************************************************************************
 * General PCIE + PCI
 ****************************************************************************/
int orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
{
	int ret = 0;

	if (nr == 0) {
		/*
		 * PCIE setup
		 */
		orion_pcie_set_bus_nr(0);
		ret = orion_pcie_setup(sys);
	} else if (nr == 1) {
		/*
		 * PCI setup
		 */
		ret = orion_pci_setup(sys);
	}

	return ret;
}

struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
{
	struct pci_ops *ops;
	struct pci_bus *bus;


	if (nr == 0) {
		u32 pci_bus;
		/*
		 * PCIE scan
		 */
		ops = &orion_pcie_ops;
		bus = pci_scan_bus(sys->busnr, ops, sys);
		/*
		 * Set local PCI bus number to follow PCIE bridges (if any)
		 */
		pci_bus	= bus->number + bus->subordinate - bus->secondary + 1;
		orion_pci_set_bus_nr(pci_bus);
	} else if (nr == 1) {
		/*
		 * PCI scan
		 */
		ops = &orion_pci_ops;
		bus = pci_scan_bus(sys->busnr, ops, sys);
	} else {
		BUG();
		bus = NULL;
	}

	return bus;
}
Commit	Line	Data
038ee083 TP	1	/*
	2	* arch/arm/mach-orion/pci.c
	3	*
	4	* PCI and PCIE functions for Marvell Orion System On Chip
	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
1f2223b1	15	#include <linux/mbus.h>
038ee083 TP	16	#include <asm/mach/pci.h>
	17	#include "common.h"
	18
	19	/*****************************************************************************
	20	* Orion has one PCIE controller and one PCI controller.
	21	*
	22	* Note1: The local PCIE bus number is '0'. The local PCI bus number
	23	* follows the scanned PCIE bridged busses, if any.
	24	*
	25	* Note2: It is possible for PCI/PCIE agents to access many subsystem's
	26	* space, by configuring BARs and Address Decode Windows, e.g. flashes on
	27	* device bus, Orion registers, etc. However this code only enable the
	28	* access to DDR banks.
	29	****************************************************************************/
	30
	31
	32	/*****************************************************************************
	33	* PCIE controller
	34	****************************************************************************/
	35	#define PCIE_CTRL ORION_PCIE_REG(0x1a00)
	36	#define PCIE_STAT ORION_PCIE_REG(0x1a04)
	37	#define PCIE_DEV_ID ORION_PCIE_REG(0x0000)
	38	#define PCIE_CMD_STAT ORION_PCIE_REG(0x0004)
	39	#define PCIE_DEV_REV ORION_PCIE_REG(0x0008)
	40	#define PCIE_MASK ORION_PCIE_REG(0x1910)
	41	#define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8)
	42	#define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc)
	43
	44	/*
	45	* PCIE_STAT bits
	46	*/
	47	#define PCIE_STAT_LINK_DOWN 1
	48	#define PCIE_STAT_BUS_OFFS 8
	49	#define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS)
	50	#define PCIE_STAT_DEV_OFFS 20
	51	#define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS)
	52
	53	/*
	54	* PCIE_CONF_ADDR bits
	55	*/
	56	#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) \| ((r) & 0xfc))
	57	#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8)
	58	#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
	59	#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
	60	#define PCIE_CONF_ADDR_EN (1 << 31)
	61
1f2223b1 LB	62	/*
	63	* PCIE Address Decode Windows registers
	64	*/
	65	#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
	66	#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8))
	67	#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8))
	68	#define PCIE_WIN_CTRL(n) (((n) < 5) ? \
	69	ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
	70	ORION_PCIE_REG(0x1880))
	71	#define PCIE_WIN_BASE(n) (((n) < 5) ? \
	72	ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
	73	ORION_PCIE_REG(0x1884))
	74	#define PCIE_WIN_REMAP(n) (((n) < 5) ? \
	75	ORION_PCIE_REG(0x182c + ((n) << 4)) : \
	76	ORION_PCIE_REG(0x188c))
	77	#define PCIE_MAX_BARS 3
	78	#define PCIE_MAX_WINS 6
	79
	80	/*
	81	* Use PCIE BAR '1' for all DDR banks
	82	*/
	83	#define PCIE_DRAM_BAR 1
	84
038ee083 TP	85	/*
	86	* PCIE config cycles are done by programming the PCIE_CONF_ADDR register
	87	* and then reading the PCIE_CONF_DATA register. Need to make sure these
	88	* transactions are atomic.
	89	*/
	90	static DEFINE_SPINLOCK(orion_pcie_lock);
	91
	92	void orion_pcie_id(u32 dev, u32 rev)
	93	{
	94	*dev = orion_read(PCIE_DEV_ID) >> 16;
	95	*rev = orion_read(PCIE_DEV_REV) & 0xff;
	96	}
	97
	98	u32 orion_pcie_local_bus_nr(void)
	99	{
	100	u32 stat = orion_read(PCIE_STAT);
	101	return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS);
	102	}
	103
	104	static u32 orion_pcie_local_dev_nr(void)
	105	{
	106	u32 stat = orion_read(PCIE_STAT);
	107	return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS);
	108	}
	109
	110	static u32 orion_pcie_no_link(void)
	111	{
	112	u32 stat = orion_read(PCIE_STAT);
	113	return(stat & PCIE_STAT_LINK_DOWN);
	114	}
	115
	116	static void orion_pcie_set_bus_nr(int nr)
	117	{
	118	orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK);
	119	orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
	120	}
	121
1f2223b1 LB	122	/*
	123	* Setup PCIE BARs and Address Decode Wins:
	124	* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
	125	* WIN[0-3] -> DRAM bank[0-3]
	126	*/
	127	static void orion_setup_pcie_wins(struct mbus_dram_target_info *dram)
	128	{
	129	u32 size;
	130	int i;
	131
	132	/*
	133	* First, disable and clear BARs and windows
	134	*/
	135	for (i = 1; i < PCIE_MAX_BARS; i++) {
	136	writel(0, PCIE_BAR_CTRL(i));
	137	writel(0, PCIE_BAR_LO(i));
	138	writel(0, PCIE_BAR_HI(i));
	139	}
	140
	141	for (i = 0; i < PCIE_MAX_WINS; i++) {
	142	writel(0, PCIE_WIN_CTRL(i));
	143	writel(0, PCIE_WIN_BASE(i));
	144	writel(0, PCIE_WIN_REMAP(i));
	145	}
	146
	147	/*
	148	* Setup windows for DDR banks. Count total DDR size on the fly.
	149	*/
	150	size = 0;
	151	for (i = 0; i < dram->num_cs; i++) {
	152	struct mbus_dram_window *cs = dram->cs + i;
	153
	154	writel(cs->base & 0xffff0000, PCIE_WIN_BASE(i));
	155	writel(0, PCIE_WIN_REMAP(i));
	156	writel(((cs->size - 1) & 0xffff0000) \|
	157	(cs->mbus_attr << 8) \|
	158	(dram->mbus_dram_target_id << 4) \|
	159	(PCIE_DRAM_BAR << 1) \| 1, PCIE_WIN_CTRL(i));
	160
	161	size += cs->size;
	162	}
	163
	164	/*
	165	* Setup BAR[1] to all DRAM banks
	166	*/
	167	writel(dram->cs[0].base, PCIE_BAR_LO(PCIE_DRAM_BAR));
	168	writel(0, PCIE_BAR_HI(PCIE_DRAM_BAR));
	169	writel(((size - 1) & 0xffff0000) \| 1, PCIE_BAR_CTRL(PCIE_DRAM_BAR));
	170	}
	171
038ee083 TP	172	static void orion_pcie_master_slave_enable(void)
	173	{
	174	orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER \|
	175	PCI_COMMAND_IO \|
	176	PCI_COMMAND_MEMORY);
	177	}
	178
	179	static void orion_pcie_enable_interrupts(void)
	180	{
	181	/*
	182	* Enable interrupts lines
	183	* INTA[24] INTB[25] INTC[26] INTD[27]
	184	*/
	185	orion_setbits(PCIE_MASK, 0xf<<24);
	186	}
	187
	188	static int orion_pcie_valid_config(u32 bus, u32 dev)
	189	{
	190	/*
	191	* Don't go out when trying to access --
	192	* 1. our own device
	193	* 2. where there's no device connected (no link)
	194	* 3. nonexisting devices on local bus
	195	*/
	196
	197	if ((orion_pcie_local_bus_nr() == bus) &&
	198	(orion_pcie_local_dev_nr() == dev))
	199	return 0;
	200
	201	if (orion_pcie_no_link())
	202	return 0;
	203
	204	if (bus == orion_pcie_local_bus_nr())
	205	if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) \|\|
	206	((orion_pcie_local_dev_nr() != 0) && (dev != 0)))
	207	return 0;
	208
	209	return 1;
	210	}
	211
	212	static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	213	int size, u32 *val)
	214	{
	215	unsigned long flags;
	216	unsigned int dev, rev, pcie_addr;
	217
	218	if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
	219	*val = 0xffffffff;
	220	return PCIBIOS_DEVICE_NOT_FOUND;
	221	}
	222
	223	spin_lock_irqsave(&orion_pcie_lock, flags);
	224
	225	orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) \|
	226	PCIE_CONF_DEV(PCI_SLOT(devfn)) \|
	227	PCIE_CONF_FUNC(PCI_FUNC(devfn)) \|
	228	PCIE_CONF_REG(where) \| PCIE_CONF_ADDR_EN);
	229
	230	orion_pcie_id(&dev, &rev);
c9e3de94	231	if (dev == MV88F5181_DEV_ID \|\| dev == MV88F5182_DEV_ID) {
038ee083	232	/* extended register space */
7f74c2c7	233	pcie_addr = ORION_PCIE_WA_VIRT_BASE;
038ee083 TP	234	pcie_addr \|= PCIE_CONF_BUS(bus->number) \|
	235	PCIE_CONF_DEV(PCI_SLOT(devfn)) \|
	236	PCIE_CONF_FUNC(PCI_FUNC(devfn)) \|
	237	PCIE_CONF_REG(where);
	238	*val = orion_read(pcie_addr);
	239	} else
	240	*val = orion_read(PCIE_CONF_DATA);
	241
	242	if (size == 1)
	243	val = (val >> (8*(where & 0x3))) & 0xff;
	244	else if (size == 2)
	245	val = (val >> (8*(where & 0x3))) & 0xffff;
	246
	247	spin_unlock_irqrestore(&orion_pcie_lock, flags);
	248
	249	return PCIBIOS_SUCCESSFUL;
	250	}
	251
	252
	253	static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where,
	254	int size, u32 val)
	255	{
	256	unsigned long flags;
	257	int ret;
	258
	259	if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
	260	return PCIBIOS_DEVICE_NOT_FOUND;
	261
	262	spin_lock_irqsave(&orion_pcie_lock, flags);
	263
	264	ret = PCIBIOS_SUCCESSFUL;
	265
	266	orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) \|
	267	PCIE_CONF_DEV(PCI_SLOT(devfn)) \|
	268	PCIE_CONF_FUNC(PCI_FUNC(devfn)) \|
	269	PCIE_CONF_REG(where) \| PCIE_CONF_ADDR_EN);
	270
	271	if (size == 4) {
	272	__raw_writel(val, PCIE_CONF_DATA);
	273	} else if (size == 2) {
	274	__raw_writew(val, PCIE_CONF_DATA + (where & 0x3));
	275	} else if (size == 1) {
	276	__raw_writeb(val, PCIE_CONF_DATA + (where & 0x3));
	277	} else {
	278	ret = PCIBIOS_BAD_REGISTER_NUMBER;
	279	}
	280
	281	spin_unlock_irqrestore(&orion_pcie_lock, flags);
	282
	283	return ret;
	284	}
	285
	286	struct pci_ops orion_pcie_ops = {
	287	.read = orion_pcie_rd_conf,
	288	.write = orion_pcie_wr_conf,
	289	};
	290
	291
	292	static int orion_pcie_setup(struct pci_sys_data *sys)
	293	{
	294	struct resource *res;
	295
1f2223b1 LB	296	/*
	297	* Point PCIe unit MBUS decode windows to DRAM space.
	298	*/
	299	orion_setup_pcie_wins(&orion_mbus_dram_info);
	300
038ee083 TP	301	/*
	302	* Master + Slave enable
	303	*/
	304	orion_pcie_master_slave_enable();
	305
	306	/*
	307	* Enable interrupts lines A-D
	308	*/
	309	orion_pcie_enable_interrupts();
	310
	311	/*
	312	* Request resource
	313	*/
	314	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	315	if (!res)
	316	panic("orion_pci_setup unable to alloc resources");
	317
	318	/*
	319	* IORESOURCE_IO
	320	*/
	321	res[0].name = "PCI-EX I/O Space";
	322	res[0].flags = IORESOURCE_IO;
7f74c2c7	323	res[0].start = ORION_PCIE_IO_BUS_BASE;
038ee083 TP	324	res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
	325	if (request_resource(&ioport_resource, &res[0]))
	326	panic("Request PCIE IO resource failed\n");
	327	sys->resource[0] = &res[0];
	328
	329	/*
	330	* IORESOURCE_MEM
	331	*/
	332	res[1].name = "PCI-EX Memory Space";
	333	res[1].flags = IORESOURCE_MEM;
7f74c2c7	334	res[1].start = ORION_PCIE_MEM_PHYS_BASE;
038ee083 TP	335	res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
	336	if (request_resource(&iomem_resource, &res[1]))
	337	panic("Request PCIE Memory resource failed\n");
	338	sys->resource[1] = &res[1];
	339
	340	sys->resource[2] = NULL;
	341	sys->io_offset = 0;
	342
	343	return 1;
	344	}
	345
	346	/*****************************************************************************
	347	* PCI controller
	348	****************************************************************************/
	349	#define PCI_MODE ORION_PCI_REG(0xd00)
	350	#define PCI_CMD ORION_PCI_REG(0xc00)
	351	#define PCI_P2P_CONF ORION_PCI_REG(0x1d14)
	352	#define PCI_CONF_ADDR ORION_PCI_REG(0xc78)
	353	#define PCI_CONF_DATA ORION_PCI_REG(0xc7c)
	354
	355	/*
	356	* PCI_MODE bits
	357	*/
	358	#define PCI_MODE_64BIT (1 << 2)
	359	#define PCI_MODE_PCIX ((1 << 4) \| (1 << 5))
	360
	361	/*
	362	* PCI_CMD bits
	363	*/
	364	#define PCI_CMD_HOST_REORDER (1 << 29)
	365
	366	/*
	367	* PCI_P2P_CONF bits
	368	*/
	369	#define PCI_P2P_BUS_OFFS 16
	370	#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
	371	#define PCI_P2P_DEV_OFFS 24
	372	#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
	373
	374	/*
	375	* PCI_CONF_ADDR bits
	376	*/
	377	#define PCI_CONF_REG(reg) ((reg) & 0xfc)
	378	#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
	379	#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
	380	#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
	381	#define PCI_CONF_ADDR_EN (1 << 31)
	382
	383	/*
	384	* Internal configuration space
	385	*/
	386	#define PCI_CONF_FUNC_STAT_CMD 0
	387	#define PCI_CONF_REG_STAT_CMD 4
	388	#define PCIX_STAT 0x64
	389	#define PCIX_STAT_BUS_OFFS 8
	390	#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
	391
1f2223b1 LB	392	/*
	393	* PCI Address Decode Windows registers
	394	*/
	395	#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \
	396	((n) == 1) ? ORION_PCI_REG(0xd08) : \
	397	((n) == 2) ? ORION_PCI_REG(0xc0c) : \
	398	((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
	399	#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \
	400	((n) == 1) ? ORION_PCI_REG(0xd48) : \
	401	((n) == 2) ? ORION_PCI_REG(0xc4c) : \
	402	((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
	403	#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c)
	404	#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c)
	405
	406	/*
	407	* PCI configuration helpers for BAR settings
	408	*/
	409	#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
	410	#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
	411	#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
	412
038ee083 TP	413	/*
	414	* PCI config cycles are done by programming the PCI_CONF_ADDR register
	415	* and then reading the PCI_CONF_DATA register. Need to make sure these
	416	* transactions are atomic.
	417	*/
	418	static DEFINE_SPINLOCK(orion_pci_lock);
	419
	420	u32 orion_pci_local_bus_nr(void)
	421	{
	422	u32 conf = orion_read(PCI_P2P_CONF);
	423	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
	424	}
	425
1f2223b1	426	static u32 orion_pci_local_dev_nr(void)
038ee083 TP	427	{
	428	u32 conf = orion_read(PCI_P2P_CONF);
	429	return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
	430	}
	431
1f2223b1	432	static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
038ee083 TP	433	u32 where, u32 size, u32 *val)
	434	{
	435	unsigned long flags;
	436	spin_lock_irqsave(&orion_pci_lock, flags);
	437
	438	orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) \|
	439	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	440	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN);
	441
	442	*val = orion_read(PCI_CONF_DATA);
	443
	444	if (size == 1)
	445	val = (val >> (8*(where & 0x3))) & 0xff;
	446	else if (size == 2)
	447	val = (val >> (8*(where & 0x3))) & 0xffff;
	448
	449	spin_unlock_irqrestore(&orion_pci_lock, flags);
	450
	451	return PCIBIOS_SUCCESSFUL;
	452	}
	453
1f2223b1	454	static int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
038ee083 TP	455	u32 where, u32 size, u32 val)
	456	{
	457	unsigned long flags;
	458	int ret = PCIBIOS_SUCCESSFUL;
	459
	460	spin_lock_irqsave(&orion_pci_lock, flags);
	461
	462	orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) \|
	463	PCI_CONF_DEV(dev) \| PCI_CONF_REG(where) \|
	464	PCI_CONF_FUNC(func) \| PCI_CONF_ADDR_EN);
	465
	466	if (size == 4) {
	467	__raw_writel(val, PCI_CONF_DATA);
	468	} else if (size == 2) {
	469	__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	470	} else if (size == 1) {
	471	__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	472	} else {
	473	ret = PCIBIOS_BAD_REGISTER_NUMBER;
	474	}
	475
	476	spin_unlock_irqrestore(&orion_pci_lock, flags);
	477
	478	return ret;
	479	}
	480
	481	static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn,
	482	int where, int size, u32 *val)
	483	{
	484	/*
	485	* Don't go out for local device
	486	*/
	487	if ((orion_pci_local_bus_nr() == bus->number) &&
	488	(orion_pci_local_dev_nr() == PCI_SLOT(devfn))) {
	489	*val = 0xffffffff;
	490	return PCIBIOS_DEVICE_NOT_FOUND;
	491	}
	492
	493	return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
	494	PCI_FUNC(devfn), where, size, val);
	495	}
	496
	497	static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
	498	int where, int size, u32 val)
	499	{
	500	/*
	501	* Don't go out for local device
	502	*/
	503	if ((orion_pci_local_bus_nr() == bus->number) &&
	504	(orion_pci_local_dev_nr() == PCI_SLOT(devfn)))
	505	return PCIBIOS_DEVICE_NOT_FOUND;
	506
	507	return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
	508	PCI_FUNC(devfn), where, size, val);
	509	}
	510
	511	struct pci_ops orion_pci_ops = {
	512	.read = orion_pci_rd_conf,
	513	.write = orion_pci_wr_conf,
	514	};
	515
	516	static void orion_pci_set_bus_nr(int nr)
	517	{
	518	u32 p2p = orion_read(PCI_P2P_CONF);
519
520	if (orion_read(PCI_MODE) & PCI_MODE_PCIX) {
521	/*
522	* PCI-X mode
523	*/
524	u32 pcix_status, bus, dev;
525	bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
526	dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
527	orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
528	pcix_status &= ~PCIX_STAT_BUS_MASK;
529	pcix_status \|= (nr << PCIX_STAT_BUS_OFFS);
530	orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
531	} else {
532	/*
533	* PCI Conventional mode
534	*/
535	p2p &= ~PCI_P2P_BUS_MASK;
536	p2p \|= (nr << PCI_P2P_BUS_OFFS);
537	orion_write(PCI_P2P_CONF, p2p);
538	}
539	}
540
541	static void orion_pci_master_slave_enable(void)
542	{
543	u32 bus_nr, dev_nr, func, reg, val;
544
545	bus_nr = orion_pci_local_bus_nr();
546	dev_nr = orion_pci_local_dev_nr();
547	func = PCI_CONF_FUNC_STAT_CMD;
548	reg = PCI_CONF_REG_STAT_CMD;
549	orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val);
550	val \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
551	orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val \| 0x7);
552	}
553
1f2223b1 LB	554	static void orion_setup_pci_wins(struct mbus_dram_target_info *dram)
	555	{
	556	u32 win_enable;
	557	u32 bus;
	558	u32 dev;
	559	int i;
	560
	561	/*
	562	* First, disable windows.
	563	*/
	564	win_enable = 0xffffffff;
	565	orion_write(PCI_BAR_ENABLE, win_enable);
	566
	567	/*
	568	* Setup windows for DDR banks.
	569	*/
	570	bus = orion_pci_local_bus_nr();
	571	dev = orion_pci_local_dev_nr();
	572
	573	for (i = 0; i < dram->num_cs; i++) {
	574	struct mbus_dram_window *cs = dram->cs + i;
	575	u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
	576	u32 reg;
	577	u32 val;
	578
	579	/*
	580	* Write DRAM bank base address register.
	581	*/
	582	reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
	583	orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
	584	val = (cs->base & 0xfffff000) \| (val & 0xfff);
	585	orion_pci_hw_wr_conf(bus, dev, func, reg, 4, val);
	586
	587	/*
	588	* Write DRAM bank size register.
	589	*/
	590	reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
	591	orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
	592	orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
	593	(cs->size - 1) & 0xfffff000);
	594	orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
	595	cs->base & 0xfffff000);
	596
	597	/*
	598	* Enable decode window for this chip select.
	599	*/
	600	win_enable &= ~(1 << cs->cs_index);
	601	}
	602
	603	/*
	604	* Re-enable decode windows.
	605	*/
	606	orion_write(PCI_BAR_ENABLE, win_enable);
	607
	608	/*
	609	* Disable automatic update of address remaping when writing to BARs.
	610	*/
	611	orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
	612	}
	613
038ee083 TP	614	static int orion_pci_setup(struct pci_sys_data *sys)
	615	{
	616	struct resource *res;
	617
1f2223b1 LB	618	/*
	619	* Point PCI unit MBUS decode windows to DRAM space.
	620	*/
	621	orion_setup_pci_wins(&orion_mbus_dram_info);
	622
038ee083 TP	623	/*
	624	* Master + Slave enable
	625	*/
	626	orion_pci_master_slave_enable();
	627
	628	/*
	629	* Force ordering
	630	*/
	631	orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
	632
	633	/*
	634	* Request resources
	635	*/
	636	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	637	if (!res)
	638	panic("orion_pci_setup unable to alloc resources");
	639
	640	/*
	641	* IORESOURCE_IO
	642	*/
	643	res[0].name = "PCI I/O Space";
	644	res[0].flags = IORESOURCE_IO;
7f74c2c7	645	res[0].start = ORION_PCI_IO_BUS_BASE;
038ee083 TP	646	res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
	647	if (request_resource(&ioport_resource, &res[0]))
	648	panic("Request PCI IO resource failed\n");
	649	sys->resource[0] = &res[0];
	650
	651	/*
	652	* IORESOURCE_MEM
	653	*/
	654	res[1].name = "PCI Memory Space";
	655	res[1].flags = IORESOURCE_MEM;
7f74c2c7	656	res[1].start = ORION_PCI_MEM_PHYS_BASE;
038ee083 TP	657	res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
	658	if (request_resource(&iomem_resource, &res[1]))
	659	panic("Request PCI Memory resource failed\n");
	660	sys->resource[1] = &res[1];
	661
	662	sys->resource[2] = NULL;
	663	sys->io_offset = 0;
	664
	665	return 1;
	666	}
	667
	668
	669	/*****************************************************************************
	670	* General PCIE + PCI
	671	****************************************************************************/
	672	int orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
	673	{
	674	int ret = 0;
	675
	676	if (nr == 0) {
	677	/*
	678	* PCIE setup
	679	*/
	680	orion_pcie_set_bus_nr(0);
	681	ret = orion_pcie_setup(sys);
	682	} else if (nr == 1) {
	683	/*
	684	* PCI setup
	685	*/
	686	ret = orion_pci_setup(sys);
	687	}
	688
	689	return ret;
	690	}
	691
	692	struct pci_bus orion_pci_sys_scan_bus(int nr, struct pci_sys_data sys)
	693	{
	694	struct pci_ops *ops;
	695	struct pci_bus *bus;
	696
	697
	698	if (nr == 0) {
	699	u32 pci_bus;
	700	/*
	701	* PCIE scan
	702	*/
	703	ops = &orion_pcie_ops;
	704	bus = pci_scan_bus(sys->busnr, ops, sys);
	705	/*
	706	* Set local PCI bus number to follow PCIE bridges (if any)
	707	*/
	708	pci_bus = bus->number + bus->subordinate - bus->secondary + 1;
	709	orion_pci_set_bus_nr(pci_bus);
	710	} else if (nr == 1) {
	711	/*
	712	* PCI scan
	713	*/
	714	ops = &orion_pci_ops;
	715	bus = pci_scan_bus(sys->busnr, ops, sys);
	716	} else {
	717	BUG();
	718	bus = NULL;
	719	}
	720
721	return bus;
722	}