projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 234f0c4c RN |
1 | /* |
| 2 | * OMAP44xx Power Management register bits | |
| 3 | * | |
| 568997cf RN |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009-2010 Nokia Corporation | |
| 234f0c4c RN |
6 | * |
| 7 | * Paul Walmsley (paul@pwsan.com) | |
| 8 | * Rajendra Nayak (rnayak@ti.com) | |
| 9 | * Benoit Cousson (b-cousson@ti.com) | |
| 10 | * | |
| 11 | * This file is automatically generated from the OMAP hardware databases. | |
| 12 | * We respectfully ask that any modifications to this file be coordinated | |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
| 14 | * authors above to ensure that the autogeneration scripts are kept | |
| 15 | * up-to-date with the file contents. | |
| 16 | * | |
| 17 | * This program is free software; you can redistribute it and/or modify | |
| 18 | * it under the terms of the GNU General Public License version 2 as | |
| 19 | * published by the Free Software Foundation. | |
| 20 | */ | |
| 21 | ||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | |
| 23 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | |
| 24 | ||
| 234f0c4c RN |
25 | |
| 26 | /* | |
| 27 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | |
| 28 | * PRM_LDO_SRAM_MPU_SETUP | |
| 29 | */ | |
| 56ef28ac | 30 | #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 |
| 568997cf | 31 | #define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) |
| 234f0c4c RN |
32 | |
| 33 | /* | |
| 34 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | |
| 35 | * PRM_LDO_SRAM_MPU_SETUP | |
| 36 | */ | |
| 56ef28ac | 37 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 |
| 568997cf | 38 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) |
| 234f0c4c RN |
39 | |
| 40 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 41 | #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 |
| 568997cf | 42 | #define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) |
| 234f0c4c RN |
43 | |
| 44 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 45 | #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 |
| 568997cf | 46 | #define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) |
| 234f0c4c RN |
47 | |
| 48 | /* Used by PRM_IRQENABLE_MPU_2 */ | |
| 56ef28ac | 49 | #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 |
| 568997cf | 50 | #define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) |
| 234f0c4c RN |
51 | |
| 52 | /* Used by PRM_IRQSTATUS_MPU_2 */ | |
| 56ef28ac | 53 | #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 |
| 568997cf | 54 | #define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) |
| 234f0c4c RN |
55 | |
| 56 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | |
| 56ef28ac | 57 | #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 |
| 568997cf | 58 | #define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) |
| 234f0c4c RN |
59 | |
| 60 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | |
| 56ef28ac | 61 | #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 |
| 568997cf | 62 | #define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) |
| 234f0c4c RN |
63 | |
| 64 | /* Used by PM_ABE_PWRSTCTRL */ | |
| 56ef28ac | 65 | #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 |
| 568997cf | 66 | #define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) |
| 234f0c4c RN |
67 | |
| 68 | /* Used by PM_ABE_PWRSTCTRL */ | |
| 56ef28ac | 69 | #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 |
| 568997cf | 70 | #define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) |
| 234f0c4c RN |
71 | |
| 72 | /* Used by PM_ABE_PWRSTST */ | |
| 56ef28ac | 73 | #define OMAP4430_AESSMEM_STATEST_SHIFT 4 |
| 568997cf | 74 | #define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) |
| 234f0c4c RN |
75 | |
| 76 | /* | |
| 77 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | |
| 78 | * PRM_LDO_SRAM_MPU_SETUP | |
| 79 | */ | |
| 56ef28ac | 80 | #define OMAP4430_AIPOFF_SHIFT 8 |
| 568997cf | 81 | #define OMAP4430_AIPOFF_MASK (1 << 8) |
| 234f0c4c RN |
82 | |
| 83 | /* Used by PRM_VOLTCTRL */ | |
| 56ef28ac | 84 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 |
| 568997cf | 85 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) |
| 234f0c4c RN |
86 | |
| 87 | /* Used by PRM_VOLTCTRL */ | |
| 56ef28ac | 88 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 |
| 568997cf | 89 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) |
| 234f0c4c RN |
90 | |
| 91 | /* Used by PRM_VOLTCTRL */ | |
| 56ef28ac | 92 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 |
| 568997cf RN |
93 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) |
| 94 | ||
| 95 | /* Used by PRM_VC_ERRST */ | |
| 96 | #define OMAP4430_BYPS_RA_ERR_SHIFT 25 | |
| 97 | #define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) | |
| 98 | ||
| 99 | /* Used by PRM_VC_ERRST */ | |
| 100 | #define OMAP4430_BYPS_SA_ERR_SHIFT 24 | |
| 101 | #define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) | |
| 102 | ||
| 103 | /* Used by PRM_VC_ERRST */ | |
| 104 | #define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 | |
| 105 | #define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) | |
| 106 | ||
| 107 | /* Used by PRM_RSTST */ | |
| 108 | #define OMAP4430_C2C_RST_SHIFT 10 | |
| 109 | #define OMAP4430_C2C_RST_MASK (1 << 10) | |
| 234f0c4c RN |
110 | |
| 111 | /* Used by PM_CAM_PWRSTCTRL */ | |
| 56ef28ac | 112 | #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 |
| 568997cf | 113 | #define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) |
| 234f0c4c RN |
114 | |
| 115 | /* Used by PM_CAM_PWRSTST */ | |
| 56ef28ac | 116 | #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 |
| 568997cf | 117 | #define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) |
| 234f0c4c RN |
118 | |
| 119 | /* Used by PRM_CLKREQCTRL */ | |
| 56ef28ac | 120 | #define OMAP4430_CLKREQ_COND_SHIFT 0 |
| 568997cf | 121 | #define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) |
| 234f0c4c RN |
122 | |
| 123 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | |
| 56ef28ac | 124 | #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 |
| 568997cf | 125 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) |
| 234f0c4c RN |
126 | |
| 127 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | |
| 56ef28ac | 128 | #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 |
| 568997cf | 129 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) |
| 234f0c4c RN |
130 | |
| 131 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | |
| 56ef28ac | 132 | #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 |
| 568997cf | 133 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) |
| 234f0c4c RN |
134 | |
| 135 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 136 | #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 |
| 568997cf | 137 | #define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) |
| 234f0c4c RN |
138 | |
| 139 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 140 | #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 |
| 568997cf | 141 | #define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) |
| 234f0c4c RN |
142 | |
| 143 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 144 | #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 |
| 568997cf | 145 | #define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) |
| 234f0c4c RN |
146 | |
| 147 | /* Used by PM_CORE_PWRSTCTRL */ | |
| 56ef28ac | 148 | #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 |
| 568997cf | 149 | #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) |
| 234f0c4c RN |
150 | |
| 151 | /* Used by PM_CORE_PWRSTCTRL */ | |
| 56ef28ac | 152 | #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 |
| 568997cf | 153 | #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) |
| 234f0c4c RN |
154 | |
| 155 | /* Used by PM_CORE_PWRSTST */ | |
| 56ef28ac | 156 | #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 |
| 568997cf | 157 | #define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) |
| 234f0c4c RN |
158 | |
| 159 | /* Used by PM_CORE_PWRSTCTRL */ | |
| 56ef28ac | 160 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 |
| 568997cf | 161 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) |
| 234f0c4c RN |
162 | |
| 163 | /* Used by PM_CORE_PWRSTCTRL */ | |
| 56ef28ac | 164 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 |
| 568997cf | 165 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) |
| 234f0c4c RN |
166 | |
| 167 | /* Used by PM_CORE_PWRSTST */ | |
| 56ef28ac | 168 | #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 |
| 568997cf RN |
169 | #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) |
| 170 | ||
| 171 | /* Used by REVISION_PRM */ | |
| 172 | #define OMAP4430_CUSTOM_SHIFT 6 | |
| 173 | #define OMAP4430_CUSTOM_MASK (0x3 << 6) | |
| 234f0c4c RN |
174 | |
| 175 | /* Used by PRM_VC_VAL_BYPASS */ | |
| 56ef28ac | 176 | #define OMAP4430_DATA_SHIFT 16 |
| 568997cf | 177 | #define OMAP4430_DATA_MASK (0xff << 16) |
| 234f0c4c RN |
178 | |
| 179 | /* Used by PRM_DEVICE_OFF_CTRL */ | |
| 56ef28ac | 180 | #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 |
| 568997cf | 181 | #define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) |
| 234f0c4c RN |
182 | |
| 183 | /* Used by PRM_VC_CFG_I2C_MODE */ | |
| 56ef28ac | 184 | #define OMAP4430_DFILTEREN_SHIFT 6 |
| 568997cf | 185 | #define OMAP4430_DFILTEREN_MASK (1 << 6) |
| 234f0c4c | 186 | |
| 568997cf RN |
187 | /* |
| 188 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | |
| 189 | * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP | |
| 190 | */ | |
| 191 | #define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 | |
| 192 | #define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) | |
| 193 | ||
| 194 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | |
| 56ef28ac | 195 | #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 |
| 568997cf | 196 | #define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) |
| 234f0c4c | 197 | |
| 568997cf | 198 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ |
| 56ef28ac | 199 | #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 |
| 568997cf | 200 | #define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) |
| 234f0c4c RN |
201 | |
| 202 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 203 | #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 |
| 568997cf | 204 | #define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) |
| 234f0c4c RN |
205 | |
| 206 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 207 | #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 |
| 568997cf | 208 | #define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) |
| 234f0c4c RN |
209 | |
| 210 | /* Used by PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 211 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 |
| 568997cf | 212 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) |
| 234f0c4c RN |
213 | |
| 214 | /* Used by PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 215 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 |
| 568997cf | 216 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) |
| 234f0c4c RN |
217 | |
| 218 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | |
| 56ef28ac | 219 | #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 |
| 568997cf | 220 | #define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) |
| 234f0c4c RN |
221 | |
| 222 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ | |
| 56ef28ac | 223 | #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 |
| 568997cf | 224 | #define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) |
| 234f0c4c RN |
225 | |
| 226 | /* Used by PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 227 | #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 |
| 568997cf | 228 | #define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) |
| 234f0c4c RN |
229 | |
| 230 | /* Used by PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 231 | #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 |
| 568997cf | 232 | #define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) |
| 234f0c4c RN |
233 | |
| 234 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 235 | #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 |
| 568997cf | 236 | #define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) |
| 234f0c4c RN |
237 | |
| 238 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 239 | #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 |
| 568997cf | 240 | #define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) |
| 234f0c4c RN |
241 | |
| 242 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 243 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 |
| 568997cf | 244 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) |
| 234f0c4c RN |
245 | |
| 246 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 247 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 |
| 568997cf | 248 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) |
| 234f0c4c RN |
249 | |
| 250 | /* Used by PM_DSS_PWRSTCTRL */ | |
| 56ef28ac | 251 | #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 |
| 568997cf | 252 | #define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) |
| 234f0c4c RN |
253 | |
| 254 | /* Used by PM_DSS_PWRSTCTRL */ | |
| 56ef28ac | 255 | #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 |
| 568997cf | 256 | #define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) |
| 234f0c4c RN |
257 | |
| 258 | /* Used by PM_DSS_PWRSTST */ | |
| 56ef28ac | 259 | #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 |
| 568997cf | 260 | #define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) |
| 234f0c4c RN |
261 | |
| 262 | /* Used by PM_CORE_PWRSTCTRL */ | |
| 56ef28ac | 263 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 |
| 568997cf | 264 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) |
| 234f0c4c RN |
265 | |
| 266 | /* Used by PM_CORE_PWRSTCTRL */ | |
| 56ef28ac | 267 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 |
| 568997cf | 268 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) |
| 234f0c4c RN |
269 | |
| 270 | /* Used by PM_CORE_PWRSTST */ | |
| 56ef28ac | 271 | #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 |
| 568997cf | 272 | #define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) |
| 234f0c4c RN |
273 | |
| 274 | /* Used by PM_CORE_PWRSTCTRL */ | |
| 56ef28ac | 275 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 |
| 568997cf | 276 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) |
| 234f0c4c RN |
277 | |
| 278 | /* Used by PM_CORE_PWRSTCTRL */ | |
| 56ef28ac | 279 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 |
| 568997cf | 280 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) |
| 234f0c4c RN |
281 | |
| 282 | /* Used by PM_CORE_PWRSTST */ | |
| 56ef28ac | 283 | #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 |
| 568997cf | 284 | #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) |
| 234f0c4c | 285 | |
| 6b54b499 RN |
286 | /* Used by PRM_DEVICE_OFF_CTRL */ |
| 287 | #define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8 | |
| 288 | #define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) | |
| 289 | ||
| 290 | /* Used by PRM_DEVICE_OFF_CTRL */ | |
| 291 | #define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9 | |
| 292 | #define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) | |
| 293 | ||
| 234f0c4c | 294 | /* Used by RM_MPU_RSTST */ |
| 56ef28ac | 295 | #define OMAP4430_EMULATION_RST_SHIFT 0 |
| 568997cf | 296 | #define OMAP4430_EMULATION_RST_MASK (1 << 0) |
| 234f0c4c RN |
297 | |
| 298 | /* Used by RM_DUCATI_RSTST */ | |
| 56ef28ac | 299 | #define OMAP4430_EMULATION_RST1ST_SHIFT 3 |
| 568997cf | 300 | #define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) |
| 234f0c4c RN |
301 | |
| 302 | /* Used by RM_DUCATI_RSTST */ | |
| 56ef28ac | 303 | #define OMAP4430_EMULATION_RST2ST_SHIFT 4 |
| 568997cf | 304 | #define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) |
| 234f0c4c RN |
305 | |
| 306 | /* Used by RM_IVAHD_RSTST */ | |
| 56ef28ac | 307 | #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 |
| 568997cf | 308 | #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) |
| 234f0c4c RN |
309 | |
| 310 | /* Used by RM_IVAHD_RSTST */ | |
| 56ef28ac | 311 | #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 |
| 568997cf | 312 | #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) |
| 234f0c4c RN |
313 | |
| 314 | /* Used by PM_EMU_PWRSTCTRL */ | |
| 56ef28ac | 315 | #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 |
| 568997cf | 316 | #define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) |
| 234f0c4c RN |
317 | |
| 318 | /* Used by PM_EMU_PWRSTST */ | |
| 56ef28ac | 319 | #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 |
| 568997cf | 320 | #define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) |
| 234f0c4c RN |
321 | |
| 322 | /* | |
| 323 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | |
| 324 | * PRM_LDO_SRAM_MPU_SETUP | |
| 325 | */ | |
| 568997cf RN |
326 | #define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 |
| 327 | #define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) | |
| 234f0c4c RN |
328 | |
| 329 | /* | |
| 330 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | |
| 331 | * PRM_LDO_SRAM_MPU_SETUP | |
| 332 | */ | |
| 568997cf RN |
333 | #define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 |
| 334 | #define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) | |
| 234f0c4c RN |
335 | |
| 336 | /* | |
| 337 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | |
| 338 | * PRM_LDO_SRAM_MPU_SETUP | |
| 339 | */ | |
| 56ef28ac | 340 | #define OMAP4430_ENFUNC4_SHIFT 6 |
| 568997cf | 341 | #define OMAP4430_ENFUNC4_MASK (1 << 6) |
| 234f0c4c RN |
342 | |
| 343 | /* | |
| 344 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | |
| 345 | * PRM_LDO_SRAM_MPU_SETUP | |
| 346 | */ | |
| 56ef28ac | 347 | #define OMAP4430_ENFUNC5_SHIFT 7 |
| 568997cf | 348 | #define OMAP4430_ENFUNC5_MASK (1 << 7) |
| 234f0c4c RN |
349 | |
| 350 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | |
| 56ef28ac | 351 | #define OMAP4430_ERRORGAIN_SHIFT 16 |
| 568997cf | 352 | #define OMAP4430_ERRORGAIN_MASK (0xff << 16) |
| 234f0c4c RN |
353 | |
| 354 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | |
| 56ef28ac | 355 | #define OMAP4430_ERROROFFSET_SHIFT 24 |
| 568997cf | 356 | #define OMAP4430_ERROROFFSET_MASK (0xff << 24) |
| 234f0c4c RN |
357 | |
| 358 | /* Used by PRM_RSTST */ | |
| 56ef28ac | 359 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 |
| 568997cf | 360 | #define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) |
| 234f0c4c RN |
361 | |
| 362 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | |
| 56ef28ac | 363 | #define OMAP4430_FORCEUPDATE_SHIFT 1 |
| 568997cf | 364 | #define OMAP4430_FORCEUPDATE_MASK (1 << 1) |
| 234f0c4c RN |
365 | |
| 366 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | |
| 56ef28ac | 367 | #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 |
| 568997cf | 368 | #define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) |
| 234f0c4c RN |
369 | |
| 370 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ | |
| 56ef28ac | 371 | #define OMAP4430_FORCEWKUP_EN_SHIFT 10 |
| 568997cf | 372 | #define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) |
| 234f0c4c RN |
373 | |
| 374 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ | |
| 56ef28ac | 375 | #define OMAP4430_FORCEWKUP_ST_SHIFT 10 |
| 568997cf RN |
376 | #define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) |
| 377 | ||
| 378 | /* Used by REVISION_PRM */ | |
| 379 | #define OMAP4430_FUNC_SHIFT 16 | |
| 380 | #define OMAP4430_FUNC_MASK (0xfff << 16) | |
| 234f0c4c RN |
381 | |
| 382 | /* Used by PM_GFX_PWRSTCTRL */ | |
| 56ef28ac | 383 | #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 |
| 568997cf | 384 | #define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) |
| 234f0c4c RN |
385 | |
| 386 | /* Used by PM_GFX_PWRSTST */ | |
| 56ef28ac | 387 | #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 |
| 568997cf | 388 | #define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) |
| 234f0c4c RN |
389 | |
| 390 | /* Used by PRM_RSTST */ | |
| 56ef28ac | 391 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 |
| 568997cf | 392 | #define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) |
| 234f0c4c RN |
393 | |
| 394 | /* Used by PRM_RSTST */ | |
| 56ef28ac | 395 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 |
| 568997cf | 396 | #define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) |
| 234f0c4c RN |
397 | |
| 398 | /* Used by PRM_IO_PMCTRL */ | |
| 56ef28ac | 399 | #define OMAP4430_GLOBAL_WUEN_SHIFT 16 |
| 568997cf | 400 | #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) |
| 234f0c4c RN |
401 | |
| 402 | /* Used by PRM_VC_CFG_I2C_MODE */ | |
| 56ef28ac | 403 | #define OMAP4430_HSMCODE_SHIFT 0 |
| 568997cf | 404 | #define OMAP4430_HSMCODE_MASK (0x7 << 0) |
| 234f0c4c RN |
405 | |
| 406 | /* Used by PRM_VC_CFG_I2C_MODE */ | |
| 56ef28ac | 407 | #define OMAP4430_HSMODEEN_SHIFT 3 |
| 568997cf | 408 | #define OMAP4430_HSMODEEN_MASK (1 << 3) |
| 234f0c4c RN |
409 | |
| 410 | /* Used by PRM_VC_CFG_I2C_CLK */ | |
| 56ef28ac | 411 | #define OMAP4430_HSSCLH_SHIFT 16 |
| 568997cf | 412 | #define OMAP4430_HSSCLH_MASK (0xff << 16) |
| 234f0c4c RN |
413 | |
| 414 | /* Used by PRM_VC_CFG_I2C_CLK */ | |
| 56ef28ac | 415 | #define OMAP4430_HSSCLL_SHIFT 24 |
| 568997cf | 416 | #define OMAP4430_HSSCLL_MASK (0xff << 24) |
| 234f0c4c RN |
417 | |
| 418 | /* Used by PM_IVAHD_PWRSTCTRL */ | |
| 56ef28ac | 419 | #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 |
| 568997cf | 420 | #define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) |
| 234f0c4c RN |
421 | |
| 422 | /* Used by PM_IVAHD_PWRSTCTRL */ | |
| 56ef28ac | 423 | #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 |
| 568997cf | 424 | #define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) |
| 234f0c4c RN |
425 | |
| 426 | /* Used by PM_IVAHD_PWRSTST */ | |
| 56ef28ac | 427 | #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 |
| 568997cf | 428 | #define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) |
| 234f0c4c RN |
429 | |
| 430 | /* Used by RM_MPU_RSTST */ | |
| 56ef28ac | 431 | #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 |
| 568997cf | 432 | #define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) |
| 234f0c4c RN |
433 | |
| 434 | /* Used by RM_DUCATI_RSTST */ | |
| 56ef28ac | 435 | #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 |
| 568997cf | 436 | #define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) |
| 234f0c4c RN |
437 | |
| 438 | /* Used by RM_DUCATI_RSTST */ | |
| 56ef28ac | 439 | #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 |
| 568997cf | 440 | #define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) |
| 234f0c4c RN |
441 | |
| 442 | /* Used by RM_IVAHD_RSTST */ | |
| 56ef28ac | 443 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 |
| 568997cf | 444 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) |
| 234f0c4c RN |
445 | |
| 446 | /* Used by RM_IVAHD_RSTST */ | |
| 56ef28ac | 447 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 |
| 568997cf | 448 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) |
| 234f0c4c RN |
449 | |
| 450 | /* Used by PRM_RSTST */ | |
| 56ef28ac | 451 | #define OMAP4430_ICEPICK_RST_SHIFT 9 |
| 568997cf | 452 | #define OMAP4430_ICEPICK_RST_MASK (1 << 9) |
| 234f0c4c RN |
453 | |
| 454 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | |
| 56ef28ac | 455 | #define OMAP4430_INITVDD_SHIFT 2 |
| 568997cf | 456 | #define OMAP4430_INITVDD_MASK (1 << 2) |
| 234f0c4c RN |
457 | |
| 458 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | |
| 56ef28ac | 459 | #define OMAP4430_INITVOLTAGE_SHIFT 8 |
| 568997cf | 460 | #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) |
| 234f0c4c RN |
461 | |
| 462 | /* | |
| 568997cf RN |
463 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, |
| 464 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, | |
| 465 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | |
| 234f0c4c | 466 | */ |
| 56ef28ac | 467 | #define OMAP4430_INTRANSITION_SHIFT 20 |
| 568997cf | 468 | #define OMAP4430_INTRANSITION_MASK (1 << 20) |
| 234f0c4c RN |
469 | |
| 470 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 471 | #define OMAP4430_IO_EN_SHIFT 9 |
| 568997cf | 472 | #define OMAP4430_IO_EN_MASK (1 << 9) |
| 234f0c4c RN |
473 | |
| 474 | /* Used by PRM_IO_PMCTRL */ | |
| 56ef28ac | 475 | #define OMAP4430_IO_ON_STATUS_SHIFT 5 |
| 568997cf | 476 | #define OMAP4430_IO_ON_STATUS_MASK (1 << 5) |
| 234f0c4c RN |
477 | |
| 478 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 479 | #define OMAP4430_IO_ST_SHIFT 9 |
| 568997cf | 480 | #define OMAP4430_IO_ST_MASK (1 << 9) |
| 234f0c4c RN |
481 | |
| 482 | /* Used by PRM_IO_PMCTRL */ | |
| 56ef28ac | 483 | #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 |
| 568997cf | 484 | #define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) |
| 234f0c4c RN |
485 | |
| 486 | /* Used by PRM_IO_PMCTRL */ | |
| 56ef28ac | 487 | #define OMAP4430_ISOCLK_STATUS_SHIFT 1 |
| 568997cf | 488 | #define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) |
| 234f0c4c RN |
489 | |
| 490 | /* Used by PRM_IO_PMCTRL */ | |
| 56ef28ac | 491 | #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 |
| 568997cf | 492 | #define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) |
| 234f0c4c RN |
493 | |
| 494 | /* Used by PRM_IO_COUNT */ | |
| 56ef28ac | 495 | #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 |
| 568997cf | 496 | #define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) |
| 234f0c4c RN |
497 | |
| 498 | /* Used by PM_L3INIT_PWRSTCTRL */ | |
| 56ef28ac | 499 | #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 |
| 568997cf | 500 | #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) |
| 234f0c4c RN |
501 | |
| 502 | /* Used by PM_L3INIT_PWRSTCTRL */ | |
| 56ef28ac | 503 | #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 |
| 568997cf | 504 | #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) |
| 234f0c4c RN |
505 | |
| 506 | /* Used by PM_L3INIT_PWRSTST */ | |
| 56ef28ac | 507 | #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 |
| 568997cf RN |
508 | #define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) |
| 509 | ||
| 510 | /* | |
| 511 | * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, | |
| 512 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | |
| 513 | */ | |
| 514 | #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 | |
| 515 | #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) | |
| 234f0c4c RN |
516 | |
| 517 | /* | |
| 568997cf RN |
518 | * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, |
| 519 | * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, | |
| 520 | * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL | |
| 234f0c4c | 521 | */ |
| 56ef28ac | 522 | #define OMAP4430_LOGICRETSTATE_SHIFT 2 |
| 568997cf | 523 | #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) |
| 234f0c4c RN |
524 | |
| 525 | /* | |
| 568997cf RN |
526 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, |
| 527 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, | |
| 528 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | |
| 234f0c4c | 529 | */ |
| 56ef28ac | 530 | #define OMAP4430_LOGICSTATEST_SHIFT 2 |
| 568997cf | 531 | #define OMAP4430_LOGICSTATEST_MASK (1 << 2) |
| 234f0c4c RN |
532 | |
| 533 | /* | |
| 568997cf | 534 | * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, |
| 234f0c4c RN |
535 | * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, |
| 536 | * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, | |
| 537 | * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, | |
| 568997cf RN |
538 | * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, |
| 539 | * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, | |
| 540 | * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, | |
| 541 | * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, | |
| 542 | * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, | |
| 543 | * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, | |
| 544 | * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, | |
| 545 | * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, | |
| 546 | * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, | |
| 547 | * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, | |
| 548 | * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, | |
| 549 | * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, | |
| 550 | * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, | |
| 551 | * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, | |
| 552 | * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, | |
| 553 | * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, | |
| 554 | * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, | |
| 555 | * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, | |
| 556 | * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, | |
| 557 | * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, | |
| 558 | * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, | |
| 559 | * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, | |
| 560 | * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, | |
| 561 | * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, | |
| 562 | * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, | |
| 563 | * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, | |
| 564 | * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, | |
| 565 | * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, | |
| 566 | * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, | |
| 567 | * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT | |
| 234f0c4c | 568 | */ |
| 56ef28ac | 569 | #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 |
| 568997cf | 570 | #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) |
| 234f0c4c RN |
571 | |
| 572 | /* | |
| 573 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, | |
| 568997cf RN |
574 | * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, |
| 575 | * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, | |
| 576 | * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, | |
| 577 | * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, | |
| 578 | * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, | |
| 234f0c4c RN |
579 | * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, |
| 580 | * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, | |
| 568997cf RN |
581 | * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, |
| 582 | * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, | |
| 583 | * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, | |
| 584 | * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, | |
| 585 | * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, | |
| 586 | * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, | |
| 587 | * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, | |
| 588 | * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, | |
| 589 | * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT | |
| 234f0c4c | 590 | */ |
| 56ef28ac | 591 | #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 |
| 568997cf | 592 | #define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) |
| 234f0c4c RN |
593 | |
| 594 | /* Used by RM_ABE_AESS_CONTEXT */ | |
| 56ef28ac | 595 | #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 |
| 568997cf | 596 | #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) |
| 234f0c4c RN |
597 | |
| 598 | /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ | |
| 56ef28ac | 599 | #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 |
| 568997cf | 600 | #define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) |
| 234f0c4c RN |
601 | |
| 602 | /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ | |
| 56ef28ac | 603 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 |
| 568997cf | 604 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) |
| 234f0c4c RN |
605 | |
| 606 | /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ | |
| 56ef28ac | 607 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 |
| 568997cf | 608 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) |
| 234f0c4c RN |
609 | |
| 610 | /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ | |
| 56ef28ac | 611 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 |
| 568997cf | 612 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) |
| 234f0c4c RN |
613 | |
| 614 | /* | |
| 615 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, | |
| 616 | * RM_SDMA_SDMA_CONTEXT | |
| 617 | */ | |
| 56ef28ac | 618 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 |
| 568997cf | 619 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) |
| 234f0c4c RN |
620 | |
| 621 | /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ | |
| 56ef28ac | 622 | #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 |
| 568997cf | 623 | #define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) |
| 234f0c4c RN |
624 | |
| 625 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | |
| 56ef28ac | 626 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 |
| 568997cf | 627 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) |
| 234f0c4c RN |
628 | |
| 629 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | |
| 56ef28ac | 630 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 |
| 568997cf | 631 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) |
| 234f0c4c RN |
632 | |
| 633 | /* Used by RM_EMU_DEBUGSS_CONTEXT */ | |
| 56ef28ac | 634 | #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 |
| 568997cf | 635 | #define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) |
| 234f0c4c RN |
636 | |
| 637 | /* Used by RM_GFX_GFX_CONTEXT */ | |
| 56ef28ac | 638 | #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 |
| 568997cf | 639 | #define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) |
| 234f0c4c RN |
640 | |
| 641 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | |
| 56ef28ac | 642 | #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 |
| 568997cf | 643 | #define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) |
| 234f0c4c RN |
644 | |
| 645 | /* | |
| 646 | * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, | |
| 647 | * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, | |
| 648 | * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT, | |
| 649 | * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, | |
| 650 | * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT | |
| 651 | */ | |
| 56ef28ac | 652 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 |
| 568997cf | 653 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) |
| 234f0c4c RN |
654 | |
| 655 | /* Used by RM_MPU_MPU_CONTEXT */ | |
| 56ef28ac | 656 | #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 |
| 568997cf | 657 | #define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) |
| 234f0c4c RN |
658 | |
| 659 | /* Used by RM_MPU_MPU_CONTEXT */ | |
| 56ef28ac | 660 | #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 |
| 568997cf | 661 | #define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) |
| 234f0c4c RN |
662 | |
| 663 | /* Used by RM_MPU_MPU_CONTEXT */ | |
| 56ef28ac | 664 | #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 |
| 568997cf | 665 | #define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) |
| 234f0c4c RN |
666 | |
| 667 | /* | |
| 668 | * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, | |
| 669 | * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, | |
| 670 | * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT | |
| 671 | */ | |
| 56ef28ac | 672 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 |
| 568997cf | 673 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) |
| 234f0c4c RN |
674 | |
| 675 | /* | |
| 676 | * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, | |
| 677 | * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT | |
| 678 | */ | |
| 56ef28ac | 679 | #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 |
| 568997cf | 680 | #define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) |
| 234f0c4c RN |
681 | |
| 682 | /* | |
| 683 | * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, | |
| 684 | * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, | |
| 685 | * RM_L4SEC_CRYPTODMA_CONTEXT | |
| 686 | */ | |
| 56ef28ac | 687 | #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 |
| 568997cf | 688 | #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) |
| 234f0c4c RN |
689 | |
| 690 | /* Used by RM_IVAHD_SL2_CONTEXT */ | |
| 56ef28ac | 691 | #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 |
| 568997cf | 692 | #define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) |
| 234f0c4c RN |
693 | |
| 694 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | |
| 56ef28ac | 695 | #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 |
| 568997cf | 696 | #define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) |
| 234f0c4c RN |
697 | |
| 698 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | |
| 56ef28ac | 699 | #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 |
| 568997cf | 700 | #define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) |
| 234f0c4c RN |
701 | |
| 702 | /* Used by RM_TESLA_TESLA_CONTEXT */ | |
| 56ef28ac | 703 | #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 |
| 568997cf | 704 | #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) |
| 234f0c4c RN |
705 | |
| 706 | /* Used by RM_TESLA_TESLA_CONTEXT */ | |
| 56ef28ac | 707 | #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 |
| 568997cf | 708 | #define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) |
| 234f0c4c RN |
709 | |
| 710 | /* Used by RM_TESLA_TESLA_CONTEXT */ | |
| 56ef28ac | 711 | #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 |
| 568997cf | 712 | #define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) |
| 234f0c4c RN |
713 | |
| 714 | /* Used by RM_WKUP_SARRAM_CONTEXT */ | |
| 56ef28ac | 715 | #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 |
| 568997cf | 716 | #define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) |
| 234f0c4c RN |
717 | |
| 718 | /* | |
| 568997cf RN |
719 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, |
| 720 | * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, | |
| 721 | * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL | |
| 234f0c4c | 722 | */ |
| 56ef28ac | 723 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 |
| 568997cf | 724 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) |
| 234f0c4c RN |
725 | |
| 726 | /* Used by PRM_MODEM_IF_CTRL */ | |
| 56ef28ac | 727 | #define OMAP4430_MODEM_READY_SHIFT 1 |
| 568997cf | 728 | #define OMAP4430_MODEM_READY_MASK (1 << 1) |
| 234f0c4c RN |
729 | |
| 730 | /* Used by PRM_MODEM_IF_CTRL */ | |
| 56ef28ac | 731 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 |
| 568997cf | 732 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) |
| 234f0c4c RN |
733 | |
| 734 | /* Used by PRM_MODEM_IF_CTRL */ | |
| 56ef28ac | 735 | #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 |
| 568997cf | 736 | #define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) |
| 234f0c4c RN |
737 | |
| 738 | /* Used by PRM_MODEM_IF_CTRL */ | |
| 56ef28ac | 739 | #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 |
| 568997cf | 740 | #define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) |
| 234f0c4c RN |
741 | |
| 742 | /* Used by PM_MPU_PWRSTCTRL */ | |
| 56ef28ac | 743 | #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 |
| 568997cf | 744 | #define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) |
| 234f0c4c RN |
745 | |
| 746 | /* Used by PM_MPU_PWRSTCTRL */ | |
| 56ef28ac | 747 | #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 |
| 568997cf | 748 | #define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) |
| 234f0c4c RN |
749 | |
| 750 | /* Used by PM_MPU_PWRSTST */ | |
| 56ef28ac | 751 | #define OMAP4430_MPU_L1_STATEST_SHIFT 4 |
| 568997cf | 752 | #define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) |
| 234f0c4c RN |
753 | |
| 754 | /* Used by PM_MPU_PWRSTCTRL */ | |
| 56ef28ac | 755 | #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 |
| 568997cf | 756 | #define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) |
| 234f0c4c RN |
757 | |
| 758 | /* Used by PM_MPU_PWRSTCTRL */ | |
| 56ef28ac | 759 | #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 |
| 568997cf | 760 | #define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) |
| 234f0c4c RN |
761 | |
| 762 | /* Used by PM_MPU_PWRSTST */ | |
| 56ef28ac | 763 | #define OMAP4430_MPU_L2_STATEST_SHIFT 6 |
| 568997cf | 764 | #define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) |
| 234f0c4c RN |
765 | |
| 766 | /* Used by PM_MPU_PWRSTCTRL */ | |
| 56ef28ac | 767 | #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 |
| 568997cf | 768 | #define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) |
| 234f0c4c RN |
769 | |
| 770 | /* Used by PM_MPU_PWRSTCTRL */ | |
| 56ef28ac | 771 | #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 |
| 568997cf | 772 | #define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) |
| 234f0c4c RN |
773 | |
| 774 | /* Used by PM_MPU_PWRSTST */ | |
| 56ef28ac | 775 | #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 |
| 568997cf | 776 | #define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) |
| 234f0c4c RN |
777 | |
| 778 | /* Used by PRM_RSTST */ | |
| 56ef28ac | 779 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 |
| 568997cf | 780 | #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) |
| 234f0c4c RN |
781 | |
| 782 | /* Used by PRM_RSTST */ | |
| 56ef28ac | 783 | #define OMAP4430_MPU_WDT_RST_SHIFT 3 |
| 568997cf | 784 | #define OMAP4430_MPU_WDT_RST_MASK (1 << 3) |
| 234f0c4c RN |
785 | |
| 786 | /* Used by PM_L4PER_PWRSTCTRL */ | |
| 56ef28ac | 787 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 |
| 568997cf | 788 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) |
| 234f0c4c RN |
789 | |
| 790 | /* Used by PM_L4PER_PWRSTCTRL */ | |
| 56ef28ac | 791 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 |
| 568997cf | 792 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) |
| 234f0c4c RN |
793 | |
| 794 | /* Used by PM_L4PER_PWRSTST */ | |
| 56ef28ac | 795 | #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 |
| 568997cf | 796 | #define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) |
| 234f0c4c RN |
797 | |
| 798 | /* Used by PM_CORE_PWRSTCTRL */ | |
| 56ef28ac | 799 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 |
| 568997cf | 800 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) |
| 234f0c4c RN |
801 | |
| 802 | /* Used by PM_CORE_PWRSTCTRL */ | |
| 56ef28ac | 803 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 |
| 568997cf | 804 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) |
| 234f0c4c RN |
805 | |
| 806 | /* Used by PM_CORE_PWRSTST */ | |
| 56ef28ac | 807 | #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 |
| 568997cf | 808 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) |
| 234f0c4c RN |
809 | |
| 810 | /* | |
| 811 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | |
| 812 | * PRM_VC_VAL_CMD_VDD_MPU_L | |
| 813 | */ | |
| 56ef28ac | 814 | #define OMAP4430_OFF_SHIFT 0 |
| 568997cf | 815 | #define OMAP4430_OFF_MASK (0xff << 0) |
| 234f0c4c RN |
816 | |
| 817 | /* | |
| 818 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | |
| 819 | * PRM_VC_VAL_CMD_VDD_MPU_L | |
| 820 | */ | |
| 56ef28ac | 821 | #define OMAP4430_ON_SHIFT 24 |
| 568997cf | 822 | #define OMAP4430_ON_MASK (0xff << 24) |
| 234f0c4c RN |
823 | |
| 824 | /* | |
| 825 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | |
| 826 | * PRM_VC_VAL_CMD_VDD_MPU_L | |
| 827 | */ | |
| 56ef28ac | 828 | #define OMAP4430_ONLP_SHIFT 16 |
| 568997cf | 829 | #define OMAP4430_ONLP_MASK (0xff << 16) |
| 234f0c4c RN |
830 | |
| 831 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | |
| 56ef28ac | 832 | #define OMAP4430_OPP_CHANGE_SHIFT 2 |
| 568997cf | 833 | #define OMAP4430_OPP_CHANGE_MASK (1 << 2) |
| 234f0c4c RN |
834 | |
| 835 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | |
| 56ef28ac | 836 | #define OMAP4430_OPP_SEL_SHIFT 0 |
| 568997cf | 837 | #define OMAP4430_OPP_SEL_MASK (0x3 << 0) |
| 234f0c4c RN |
838 | |
| 839 | /* Used by PRM_SRAM_COUNT */ | |
| 56ef28ac | 840 | #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 |
| 568997cf | 841 | #define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) |
| 234f0c4c RN |
842 | |
| 843 | /* Used by PRM_PSCON_COUNT */ | |
| 56ef28ac | 844 | #define OMAP4430_PCHARGE_TIME_SHIFT 0 |
| 568997cf | 845 | #define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) |
| 234f0c4c RN |
846 | |
| 847 | /* Used by PM_ABE_PWRSTCTRL */ | |
| 56ef28ac | 848 | #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 |
| 568997cf | 849 | #define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) |
| 234f0c4c RN |
850 | |
| 851 | /* Used by PM_ABE_PWRSTCTRL */ | |
| 56ef28ac | 852 | #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 |
| 568997cf | 853 | #define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) |
| 234f0c4c RN |
854 | |
| 855 | /* Used by PM_ABE_PWRSTST */ | |
| 56ef28ac | 856 | #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 |
| 568997cf | 857 | #define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) |
| 234f0c4c RN |
858 | |
| 859 | /* Used by PRM_PHASE1_CNDP */ | |
| 56ef28ac | 860 | #define OMAP4430_PHASE1_CNDP_SHIFT 0 |
| 568997cf | 861 | #define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) |
| 234f0c4c RN |
862 | |
| 863 | /* Used by PRM_PHASE2A_CNDP */ | |
| 56ef28ac | 864 | #define OMAP4430_PHASE2A_CNDP_SHIFT 0 |
| 568997cf | 865 | #define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) |
| 234f0c4c RN |
866 | |
| 867 | /* Used by PRM_PHASE2B_CNDP */ | |
| 56ef28ac | 868 | #define OMAP4430_PHASE2B_CNDP_SHIFT 0 |
| 568997cf | 869 | #define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) |
| 234f0c4c RN |
870 | |
| 871 | /* Used by PRM_PSCON_COUNT */ | |
| 56ef28ac | 872 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 |
| 568997cf | 873 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) |
| 234f0c4c RN |
874 | |
| 875 | /* | |
| 568997cf RN |
876 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, |
| 877 | * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, | |
| 878 | * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, | |
| 879 | * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL | |
| 234f0c4c | 880 | */ |
| 56ef28ac | 881 | #define OMAP4430_POWERSTATE_SHIFT 0 |
| 568997cf | 882 | #define OMAP4430_POWERSTATE_MASK (0x3 << 0) |
| 234f0c4c RN |
883 | |
| 884 | /* | |
| 568997cf RN |
885 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, |
| 886 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, | |
| 887 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | |
| 234f0c4c | 888 | */ |
| 56ef28ac | 889 | #define OMAP4430_POWERSTATEST_SHIFT 0 |
| 568997cf | 890 | #define OMAP4430_POWERSTATEST_MASK (0x3 << 0) |
| 234f0c4c RN |
891 | |
| 892 | /* Used by PRM_PWRREQCTRL */ | |
| 56ef28ac | 893 | #define OMAP4430_PWRREQ_COND_SHIFT 0 |
| 568997cf | 894 | #define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) |
| 234f0c4c RN |
895 | |
| 896 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 897 | #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 |
| 568997cf | 898 | #define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) |
| 234f0c4c RN |
899 | |
| 900 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 901 | #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 |
| 568997cf | 902 | #define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) |
| 234f0c4c RN |
903 | |
| 904 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 905 | #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 |
| 568997cf | 906 | #define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) |
| 234f0c4c RN |
907 | |
| 908 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 909 | #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 |
| 568997cf | 910 | #define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) |
| 234f0c4c RN |
911 | |
| 912 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 913 | #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 |
| 568997cf | 914 | #define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) |
| 234f0c4c RN |
915 | |
| 916 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 917 | #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 |
| 568997cf | 918 | #define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) |
| 234f0c4c RN |
919 | |
| 920 | /* | |
| 921 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | |
| 922 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | |
| 923 | * PRM_VOLTSETUP_MPU_RET_SLEEP | |
| 924 | */ | |
| 56ef28ac | 925 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 |
| 568997cf | 926 | #define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) |
| 234f0c4c RN |
927 | |
| 928 | /* | |
| 929 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | |
| 930 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | |
| 931 | * PRM_VOLTSETUP_MPU_RET_SLEEP | |
| 932 | */ | |
| 56ef28ac | 933 | #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 |
| 568997cf | 934 | #define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) |
| 234f0c4c RN |
935 | |
| 936 | /* | |
| 937 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | |
| 938 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | |
| 939 | * PRM_VOLTSETUP_MPU_RET_SLEEP | |
| 940 | */ | |
| 56ef28ac | 941 | #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 |
| 568997cf | 942 | #define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) |
| 234f0c4c RN |
943 | |
| 944 | /* | |
| 945 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | |
| 946 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | |
| 947 | * PRM_VOLTSETUP_MPU_RET_SLEEP | |
| 948 | */ | |
| 56ef28ac | 949 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 |
| 568997cf | 950 | #define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) |
| 234f0c4c RN |
951 | |
| 952 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 953 | #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 |
| 568997cf | 954 | #define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) |
| 234f0c4c RN |
955 | |
| 956 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 957 | #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 |
| 568997cf | 958 | #define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) |
| 234f0c4c RN |
959 | |
| 960 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 961 | #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 |
| 568997cf | 962 | #define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) |
| 234f0c4c RN |
963 | |
| 964 | /* Used by PRM_VC_VAL_BYPASS */ | |
| 56ef28ac | 965 | #define OMAP4430_REGADDR_SHIFT 8 |
| 568997cf | 966 | #define OMAP4430_REGADDR_MASK (0xff << 8) |
| 234f0c4c RN |
967 | |
| 968 | /* | |
| 969 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | |
| 970 | * PRM_VC_VAL_CMD_VDD_MPU_L | |
| 971 | */ | |
| 56ef28ac | 972 | #define OMAP4430_RET_SHIFT 8 |
| 568997cf | 973 | #define OMAP4430_RET_MASK (0xff << 8) |
| 234f0c4c RN |
974 | |
| 975 | /* Used by PM_L4PER_PWRSTCTRL */ | |
| 56ef28ac | 976 | #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 |
| 568997cf | 977 | #define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) |
| 234f0c4c RN |
978 | |
| 979 | /* Used by PM_L4PER_PWRSTCTRL */ | |
| 56ef28ac | 980 | #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 |
| 568997cf | 981 | #define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) |
| 234f0c4c RN |
982 | |
| 983 | /* Used by PM_L4PER_PWRSTST */ | |
| 56ef28ac | 984 | #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 |
| 568997cf | 985 | #define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) |
| 234f0c4c RN |
986 | |
| 987 | /* | |
| 988 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | |
| 989 | * PRM_LDO_SRAM_MPU_CTRL | |
| 990 | */ | |
| 56ef28ac | 991 | #define OMAP4430_RETMODE_ENABLE_SHIFT 0 |
| 568997cf | 992 | #define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) |
| 234f0c4c | 993 | |
| 568997cf | 994 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ |
| 56ef28ac | 995 | #define OMAP4430_RST1_SHIFT 0 |
| 568997cf | 996 | #define OMAP4430_RST1_MASK (1 << 0) |
| 234f0c4c | 997 | |
| 568997cf | 998 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ |
| 56ef28ac | 999 | #define OMAP4430_RST1ST_SHIFT 0 |
| 568997cf | 1000 | #define OMAP4430_RST1ST_MASK (1 << 0) |
| 234f0c4c | 1001 | |
| 568997cf | 1002 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ |
| 56ef28ac | 1003 | #define OMAP4430_RST2_SHIFT 1 |
| 568997cf | 1004 | #define OMAP4430_RST2_MASK (1 << 1) |
| 234f0c4c | 1005 | |
| 568997cf | 1006 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ |
| 56ef28ac | 1007 | #define OMAP4430_RST2ST_SHIFT 1 |
| 568997cf | 1008 | #define OMAP4430_RST2ST_MASK (1 << 1) |
| 234f0c4c RN |
1009 | |
| 1010 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ | |
| 56ef28ac | 1011 | #define OMAP4430_RST3_SHIFT 2 |
| 568997cf | 1012 | #define OMAP4430_RST3_MASK (1 << 2) |
| 234f0c4c RN |
1013 | |
| 1014 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ | |
| 56ef28ac | 1015 | #define OMAP4430_RST3ST_SHIFT 2 |
| 568997cf | 1016 | #define OMAP4430_RST3ST_MASK (1 << 2) |
| 234f0c4c RN |
1017 | |
| 1018 | /* Used by PRM_RSTTIME */ | |
| 56ef28ac | 1019 | #define OMAP4430_RSTTIME1_SHIFT 0 |
| 568997cf | 1020 | #define OMAP4430_RSTTIME1_MASK (0x3ff << 0) |
| 234f0c4c RN |
1021 | |
| 1022 | /* Used by PRM_RSTTIME */ | |
| 56ef28ac | 1023 | #define OMAP4430_RSTTIME2_SHIFT 10 |
| 568997cf | 1024 | #define OMAP4430_RSTTIME2_MASK (0x1f << 10) |
| 234f0c4c RN |
1025 | |
| 1026 | /* Used by PRM_RSTCTRL */ | |
| 56ef28ac | 1027 | #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 |
| 568997cf | 1028 | #define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) |
| 234f0c4c RN |
1029 | |
| 1030 | /* Used by PRM_RSTCTRL */ | |
| 56ef28ac | 1031 | #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 |
| 568997cf RN |
1032 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) |
| 1033 | ||
| 1034 | /* Used by REVISION_PRM */ | |
| 1035 | #define OMAP4430_R_RTL_SHIFT 11 | |
| 1036 | #define OMAP4430_R_RTL_MASK (0x1f << 11) | |
| 234f0c4c RN |
1037 | |
| 1038 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 1039 | #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 |
| 568997cf | 1040 | #define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) |
| 234f0c4c RN |
1041 | |
| 1042 | /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ | |
| 56ef28ac | 1043 | #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 |
| 568997cf | 1044 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) |
| 234f0c4c RN |
1045 | |
| 1046 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 1047 | #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 |
| 568997cf | 1048 | #define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) |
| 234f0c4c RN |
1049 | |
| 1050 | /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ | |
| 56ef28ac | 1051 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 |
| 568997cf | 1052 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) |
| 234f0c4c RN |
1053 | |
| 1054 | /* Used by PRM_VC_CFG_CHANNEL */ | |
| 56ef28ac | 1055 | #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 |
| 568997cf | 1056 | #define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) |
| 234f0c4c RN |
1057 | |
| 1058 | /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ | |
| 56ef28ac | 1059 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 |
| 568997cf RN |
1060 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) |
| 1061 | ||
| 1062 | /* Used by REVISION_PRM */ | |
| 1063 | #define OMAP4430_SCHEME_SHIFT 30 | |
| 1064 | #define OMAP4430_SCHEME_MASK (0x3 << 30) | |
| 234f0c4c RN |
1065 | |
| 1066 | /* Used by PRM_VC_CFG_I2C_CLK */ | |
| 56ef28ac | 1067 | #define OMAP4430_SCLH_SHIFT 0 |
| 568997cf | 1068 | #define OMAP4430_SCLH_MASK (0xff << 0) |
| 234f0c4c RN |
1069 | |
| 1070 | /* Used by PRM_VC_CFG_I2C_CLK */ | |
| 56ef28ac | 1071 | #define OMAP4430_SCLL_SHIFT 8 |
| 568997cf | 1072 | #define OMAP4430_SCLL_MASK (0xff << 8) |
| 234f0c4c RN |
1073 | |
| 1074 | /* Used by PRM_RSTST */ | |
| 56ef28ac | 1075 | #define OMAP4430_SECURE_WDT_RST_SHIFT 4 |
| 568997cf | 1076 | #define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) |
| 234f0c4c RN |
1077 | |
| 1078 | /* Used by PM_IVAHD_PWRSTCTRL */ | |
| 56ef28ac | 1079 | #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 |
| 568997cf | 1080 | #define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) |
| 234f0c4c RN |
1081 | |
| 1082 | /* Used by PM_IVAHD_PWRSTCTRL */ | |
| 56ef28ac | 1083 | #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 |
| 568997cf | 1084 | #define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) |
| 234f0c4c RN |
1085 | |
| 1086 | /* Used by PM_IVAHD_PWRSTST */ | |
| 56ef28ac | 1087 | #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 |
| 568997cf | 1088 | #define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) |
| 234f0c4c RN |
1089 | |
| 1090 | /* Used by PRM_VC_VAL_BYPASS */ | |
| 56ef28ac | 1091 | #define OMAP4430_SLAVEADDR_SHIFT 0 |
| 568997cf | 1092 | #define OMAP4430_SLAVEADDR_MASK (0x7f << 0) |
| 234f0c4c RN |
1093 | |
| 1094 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | |
| 56ef28ac | 1095 | #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 |
| 568997cf | 1096 | #define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) |
| 234f0c4c RN |
1097 | |
| 1098 | /* Used by PRM_SRAM_COUNT */ | |
| 56ef28ac | 1099 | #define OMAP4430_SLPCNT_VALUE_SHIFT 16 |
| 568997cf | 1100 | #define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) |
| 234f0c4c RN |
1101 | |
| 1102 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | |
| 56ef28ac | 1103 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 |
| 568997cf | 1104 | #define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) |
| 234f0c4c RN |
1105 | |
| 1106 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | |
| 56ef28ac | 1107 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 |
| 568997cf RN |
1108 | #define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) |
| 1109 | ||
| 1110 | /* Used by PRM_VC_ERRST */ | |
| 1111 | #define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 | |
| 1112 | #define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) | |
| 1113 | ||
| 1114 | /* Used by PRM_VC_ERRST */ | |
| 1115 | #define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 | |
| 1116 | #define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) | |
| 1117 | ||
| 1118 | /* Used by PRM_VC_ERRST */ | |
| 1119 | #define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 | |
| 1120 | #define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) | |
| 1121 | ||
| 1122 | /* Used by PRM_VC_ERRST */ | |
| 1123 | #define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 | |
| 1124 | #define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) | |
| 1125 | ||
| 1126 | /* Used by PRM_VC_ERRST */ | |
| 1127 | #define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 | |
| 1128 | #define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) | |
| 1129 | ||
| 1130 | /* Used by PRM_VC_ERRST */ | |
| 1131 | #define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 | |
| 1132 | #define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) | |
| 1133 | ||
| 1134 | /* Used by PRM_VC_ERRST */ | |
| 1135 | #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 | |
| 1136 | #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) | |
| 1137 | ||
| 1138 | /* Used by PRM_VC_ERRST */ | |
| 1139 | #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 | |
| 1140 | #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) | |
| 1141 | ||
| 1142 | /* Used by PRM_VC_ERRST */ | |
| 1143 | #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 | |
| 1144 | #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) | |
| 234f0c4c RN |
1145 | |
| 1146 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | |
| 56ef28ac | 1147 | #define OMAP4430_SR2EN_SHIFT 0 |
| 568997cf | 1148 | #define OMAP4430_SR2EN_MASK (1 << 0) |
| 234f0c4c RN |
1149 | |
| 1150 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | |
| 56ef28ac | 1151 | #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 |
| 568997cf | 1152 | #define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) |
| 234f0c4c RN |
1153 | |
| 1154 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | |
| 56ef28ac | 1155 | #define OMAP4430_SR2_STATUS_SHIFT 3 |
| 568997cf | 1156 | #define OMAP4430_SR2_STATUS_MASK (0x3 << 3) |
| 234f0c4c RN |
1157 | |
| 1158 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | |
| 56ef28ac | 1159 | #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 |
| 568997cf | 1160 | #define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) |
| 234f0c4c RN |
1161 | |
| 1162 | /* | |
| 1163 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | |
| 1164 | * PRM_LDO_SRAM_MPU_CTRL | |
| 1165 | */ | |
| 56ef28ac | 1166 | #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 |
| 568997cf | 1167 | #define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) |
| 234f0c4c RN |
1168 | |
| 1169 | /* | |
| 1170 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | |
| 1171 | * PRM_LDO_SRAM_MPU_CTRL | |
| 1172 | */ | |
| 56ef28ac | 1173 | #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 |
| 568997cf | 1174 | #define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) |
| 234f0c4c RN |
1175 | |
| 1176 | /* Used by PRM_VC_CFG_I2C_MODE */ | |
| 56ef28ac | 1177 | #define OMAP4430_SRMODEEN_SHIFT 4 |
| 568997cf | 1178 | #define OMAP4430_SRMODEEN_MASK (1 << 4) |
| 234f0c4c RN |
1179 | |
| 1180 | /* Used by PRM_VOLTSETUP_WARMRESET */ | |
| 56ef28ac | 1181 | #define OMAP4430_STABLE_COUNT_SHIFT 0 |
| 568997cf | 1182 | #define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) |
| 234f0c4c RN |
1183 | |
| 1184 | /* Used by PRM_VOLTSETUP_WARMRESET */ | |
| 56ef28ac | 1185 | #define OMAP4430_STABLE_PRESCAL_SHIFT 8 |
| 568997cf RN |
1186 | #define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) |
| 1187 | ||
| 1188 | /* Used by PRM_LDO_BANDGAP_SETUP */ | |
| 1189 | #define OMAP4430_STARTUP_COUNT_SHIFT 0 | |
| 1190 | #define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) | |
| 1191 | ||
| 1192 | /* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ | |
| 1193 | #define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 | |
| 1194 | #define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) | |
| 234f0c4c RN |
1195 | |
| 1196 | /* Used by PM_IVAHD_PWRSTCTRL */ | |
| 56ef28ac | 1197 | #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 |
| 568997cf | 1198 | #define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) |
| 234f0c4c RN |
1199 | |
| 1200 | /* Used by PM_IVAHD_PWRSTCTRL */ | |
| 56ef28ac | 1201 | #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 |
| 568997cf | 1202 | #define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) |
| 234f0c4c RN |
1203 | |
| 1204 | /* Used by PM_IVAHD_PWRSTST */ | |
| 56ef28ac | 1205 | #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 |
| 568997cf | 1206 | #define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) |
| 234f0c4c RN |
1207 | |
| 1208 | /* Used by PM_IVAHD_PWRSTCTRL */ | |
| 56ef28ac | 1209 | #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 |
| 568997cf | 1210 | #define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) |
| 234f0c4c RN |
1211 | |
| 1212 | /* Used by PM_IVAHD_PWRSTCTRL */ | |
| 56ef28ac | 1213 | #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 |
| 568997cf | 1214 | #define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) |
| 234f0c4c RN |
1215 | |
| 1216 | /* Used by PM_IVAHD_PWRSTST */ | |
| 56ef28ac | 1217 | #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 |
| 568997cf | 1218 | #define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) |
| 234f0c4c RN |
1219 | |
| 1220 | /* Used by RM_TESLA_RSTST */ | |
| 56ef28ac | 1221 | #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 |
| 568997cf | 1222 | #define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) |
| 234f0c4c RN |
1223 | |
| 1224 | /* Used by RM_TESLA_RSTST */ | |
| 56ef28ac | 1225 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 |
| 568997cf | 1226 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) |
| 234f0c4c RN |
1227 | |
| 1228 | /* Used by PM_TESLA_PWRSTCTRL */ | |
| 56ef28ac | 1229 | #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 |
| 568997cf | 1230 | #define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) |
| 234f0c4c RN |
1231 | |
| 1232 | /* Used by PM_TESLA_PWRSTCTRL */ | |
| 56ef28ac | 1233 | #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 |
| 568997cf | 1234 | #define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) |
| 234f0c4c RN |
1235 | |
| 1236 | /* Used by PM_TESLA_PWRSTST */ | |
| 56ef28ac | 1237 | #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 |
| 568997cf | 1238 | #define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) |
| 234f0c4c RN |
1239 | |
| 1240 | /* Used by PM_TESLA_PWRSTCTRL */ | |
| 56ef28ac | 1241 | #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 |
| 568997cf | 1242 | #define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) |
| 234f0c4c RN |
1243 | |
| 1244 | /* Used by PM_TESLA_PWRSTCTRL */ | |
| 56ef28ac | 1245 | #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 |
| 568997cf | 1246 | #define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) |
| 234f0c4c RN |
1247 | |
| 1248 | /* Used by PM_TESLA_PWRSTST */ | |
| 56ef28ac | 1249 | #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 |
| 568997cf | 1250 | #define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) |
| 234f0c4c RN |
1251 | |
| 1252 | /* Used by PM_TESLA_PWRSTCTRL */ | |
| 56ef28ac | 1253 | #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 |
| 568997cf | 1254 | #define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) |
| 234f0c4c RN |
1255 | |
| 1256 | /* Used by PM_TESLA_PWRSTCTRL */ | |
| 56ef28ac | 1257 | #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 |
| 568997cf | 1258 | #define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) |
| 234f0c4c RN |
1259 | |
| 1260 | /* Used by PM_TESLA_PWRSTST */ | |
| 56ef28ac | 1261 | #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 |
| 568997cf | 1262 | #define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) |
| 234f0c4c RN |
1263 | |
| 1264 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | |
| 56ef28ac | 1265 | #define OMAP4430_TIMEOUT_SHIFT 0 |
| 568997cf | 1266 | #define OMAP4430_TIMEOUT_MASK (0xffff << 0) |
| 234f0c4c RN |
1267 | |
| 1268 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | |
| 56ef28ac | 1269 | #define OMAP4430_TIMEOUTEN_SHIFT 3 |
| 568997cf | 1270 | #define OMAP4430_TIMEOUTEN_MASK (1 << 3) |
| 234f0c4c RN |
1271 | |
| 1272 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1273 | #define OMAP4430_TRANSITION_EN_SHIFT 8 |
| 568997cf | 1274 | #define OMAP4430_TRANSITION_EN_MASK (1 << 8) |
| 234f0c4c RN |
1275 | |
| 1276 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1277 | #define OMAP4430_TRANSITION_ST_SHIFT 8 |
| 568997cf | 1278 | #define OMAP4430_TRANSITION_ST_MASK (1 << 8) |
| 234f0c4c RN |
1279 | |
| 1280 | /* Used by PRM_VC_VAL_BYPASS */ | |
| 56ef28ac | 1281 | #define OMAP4430_VALID_SHIFT 24 |
| 568997cf | 1282 | #define OMAP4430_VALID_MASK (1 << 24) |
| 234f0c4c RN |
1283 | |
| 1284 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1285 | #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 |
| 568997cf | 1286 | #define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) |
| 234f0c4c RN |
1287 | |
| 1288 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1289 | #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 |
| 568997cf RN |
1290 | #define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) |
| 1291 | ||
| 1292 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 1293 | #define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 | |
| 1294 | #define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) | |
| 1295 | ||
| 1296 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 1297 | #define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 | |
| 1298 | #define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) | |
| 234f0c4c RN |
1299 | |
| 1300 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1301 | #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 |
| 568997cf | 1302 | #define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) |
| 234f0c4c RN |
1303 | |
| 1304 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1305 | #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 |
| 568997cf | 1306 | #define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) |
| 234f0c4c RN |
1307 | |
| 1308 | /* Used by PRM_IRQENABLE_MPU_2 */ | |
| 56ef28ac | 1309 | #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 |
| 568997cf | 1310 | #define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) |
| 234f0c4c RN |
1311 | |
| 1312 | /* Used by PRM_IRQSTATUS_MPU_2 */ | |
| 56ef28ac | 1313 | #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 |
| 568997cf | 1314 | #define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) |
| 234f0c4c RN |
1315 | |
| 1316 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1317 | #define OMAP4430_VC_RAERR_EN_SHIFT 12 |
| 568997cf | 1318 | #define OMAP4430_VC_RAERR_EN_MASK (1 << 12) |
| 234f0c4c RN |
1319 | |
| 1320 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1321 | #define OMAP4430_VC_RAERR_ST_SHIFT 12 |
| 568997cf | 1322 | #define OMAP4430_VC_RAERR_ST_MASK (1 << 12) |
| 234f0c4c RN |
1323 | |
| 1324 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1325 | #define OMAP4430_VC_SAERR_EN_SHIFT 11 |
| 568997cf | 1326 | #define OMAP4430_VC_SAERR_EN_MASK (1 << 11) |
| 234f0c4c RN |
1327 | |
| 1328 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1329 | #define OMAP4430_VC_SAERR_ST_SHIFT 11 |
| 568997cf | 1330 | #define OMAP4430_VC_SAERR_ST_MASK (1 << 11) |
| 234f0c4c RN |
1331 | |
| 1332 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1333 | #define OMAP4430_VC_TOERR_EN_SHIFT 13 |
| 568997cf | 1334 | #define OMAP4430_VC_TOERR_EN_MASK (1 << 13) |
| 234f0c4c RN |
1335 | |
| 1336 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1337 | #define OMAP4430_VC_TOERR_ST_SHIFT 13 |
| 568997cf | 1338 | #define OMAP4430_VC_TOERR_ST_MASK (1 << 13) |
| 234f0c4c RN |
1339 | |
| 1340 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | |
| 56ef28ac | 1341 | #define OMAP4430_VDDMAX_SHIFT 24 |
| 568997cf | 1342 | #define OMAP4430_VDDMAX_MASK (0xff << 24) |
| 234f0c4c RN |
1343 | |
| 1344 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | |
| 56ef28ac | 1345 | #define OMAP4430_VDDMIN_SHIFT 16 |
| 568997cf | 1346 | #define OMAP4430_VDDMIN_MASK (0xff << 16) |
| 234f0c4c RN |
1347 | |
| 1348 | /* Used by PRM_VOLTCTRL */ | |
| 56ef28ac | 1349 | #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 |
| 568997cf | 1350 | #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) |
| 234f0c4c RN |
1351 | |
| 1352 | /* Used by PRM_RSTST */ | |
| 56ef28ac | 1353 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 |
| 568997cf | 1354 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) |
| 234f0c4c RN |
1355 | |
| 1356 | /* Used by PRM_VOLTCTRL */ | |
| 56ef28ac | 1357 | #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 |
| 568997cf | 1358 | #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) |
| 234f0c4c RN |
1359 | |
| 1360 | /* Used by PRM_VOLTCTRL */ | |
| 56ef28ac | 1361 | #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 |
| 568997cf | 1362 | #define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) |
| 234f0c4c RN |
1363 | |
| 1364 | /* Used by PRM_RSTST */ | |
| 56ef28ac | 1365 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 |
| 568997cf | 1366 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) |
| 234f0c4c RN |
1367 | |
| 1368 | /* Used by PRM_VOLTCTRL */ | |
| 56ef28ac | 1369 | #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 |
| 568997cf | 1370 | #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) |
| 234f0c4c RN |
1371 | |
| 1372 | /* Used by PRM_VOLTCTRL */ | |
| 56ef28ac | 1373 | #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 |
| 568997cf | 1374 | #define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) |
| 234f0c4c RN |
1375 | |
| 1376 | /* Used by PRM_RSTST */ | |
| 56ef28ac | 1377 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 |
| 568997cf RN |
1378 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) |
| 1379 | ||
| 1380 | /* Used by PRM_VC_ERRST */ | |
| 1381 | #define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 | |
| 1382 | #define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) | |
| 1383 | ||
| 1384 | /* Used by PRM_VC_ERRST */ | |
| 1385 | #define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 | |
| 1386 | #define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) | |
| 1387 | ||
| 1388 | /* Used by PRM_VC_ERRST */ | |
| 1389 | #define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 | |
| 1390 | #define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) | |
| 1391 | ||
| 1392 | /* Used by PRM_VC_ERRST */ | |
| 1393 | #define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 | |
| 1394 | #define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) | |
| 1395 | ||
| 1396 | /* Used by PRM_VC_ERRST */ | |
| 1397 | #define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 | |
| 1398 | #define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) | |
| 1399 | ||
| 1400 | /* Used by PRM_VC_ERRST */ | |
| 1401 | #define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 | |
| 1402 | #define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) | |
| 1403 | ||
| 1404 | /* Used by PRM_VC_ERRST */ | |
| 1405 | #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 | |
| 1406 | #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) | |
| 1407 | ||
| 1408 | /* Used by PRM_VC_ERRST */ | |
| 1409 | #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 | |
| 1410 | #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) | |
| 1411 | ||
| 1412 | /* Used by PRM_VC_ERRST */ | |
| 1413 | #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 | |
| 1414 | #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) | |
| 234f0c4c RN |
1415 | |
| 1416 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | |
| 56ef28ac | 1417 | #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 |
| 568997cf | 1418 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) |
| 234f0c4c RN |
1419 | |
| 1420 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | |
| 56ef28ac | 1421 | #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 |
| 568997cf | 1422 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) |
| 234f0c4c RN |
1423 | |
| 1424 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | |
| 56ef28ac | 1425 | #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 |
| 568997cf | 1426 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) |
| 234f0c4c RN |
1427 | |
| 1428 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | |
| 56ef28ac | 1429 | #define OMAP4430_VPENABLE_SHIFT 0 |
| 568997cf | 1430 | #define OMAP4430_VPENABLE_MASK (1 << 0) |
| 234f0c4c RN |
1431 | |
| 1432 | /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ | |
| 56ef28ac | 1433 | #define OMAP4430_VPINIDLE_SHIFT 0 |
| 568997cf | 1434 | #define OMAP4430_VPINIDLE_MASK (1 << 0) |
| 234f0c4c RN |
1435 | |
| 1436 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | |
| 56ef28ac | 1437 | #define OMAP4430_VPVOLTAGE_SHIFT 0 |
| 568997cf | 1438 | #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) |
| 234f0c4c RN |
1439 | |
| 1440 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1441 | #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 |
| 568997cf | 1442 | #define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) |
| 234f0c4c RN |
1443 | |
| 1444 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1445 | #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 |
| 568997cf | 1446 | #define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) |
| 234f0c4c RN |
1447 | |
| 1448 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1449 | #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 |
| 568997cf | 1450 | #define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) |
| 234f0c4c RN |
1451 | |
| 1452 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1453 | #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 |
| 568997cf | 1454 | #define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) |
| 234f0c4c RN |
1455 | |
| 1456 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1457 | #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 |
| 568997cf | 1458 | #define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) |
| 234f0c4c RN |
1459 | |
| 1460 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1461 | #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 |
| 568997cf | 1462 | #define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) |
| 234f0c4c RN |
1463 | |
| 1464 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1465 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 |
| 568997cf | 1466 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) |
| 234f0c4c RN |
1467 | |
| 1468 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1469 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 |
| 568997cf | 1470 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) |
| 234f0c4c RN |
1471 | |
| 1472 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1473 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 |
| 568997cf | 1474 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) |
| 234f0c4c RN |
1475 | |
| 1476 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1477 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 |
| 568997cf | 1478 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) |
| 234f0c4c RN |
1479 | |
| 1480 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1481 | #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 |
| 568997cf | 1482 | #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) |
| 234f0c4c RN |
1483 | |
| 1484 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1485 | #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 |
| 568997cf | 1486 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) |
| 234f0c4c RN |
1487 | |
| 1488 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1489 | #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 |
| 568997cf | 1490 | #define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) |
| 234f0c4c RN |
1491 | |
| 1492 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1493 | #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 |
| 568997cf | 1494 | #define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) |
| 234f0c4c RN |
1495 | |
| 1496 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1497 | #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 |
| 568997cf | 1498 | #define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) |
| 234f0c4c RN |
1499 | |
| 1500 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1501 | #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 |
| 568997cf | 1502 | #define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) |
| 234f0c4c RN |
1503 | |
| 1504 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1505 | #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 |
| 568997cf | 1506 | #define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) |
| 234f0c4c RN |
1507 | |
| 1508 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1509 | #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 |
| 568997cf | 1510 | #define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) |
| 234f0c4c RN |
1511 | |
| 1512 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1513 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 |
| 568997cf | 1514 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) |
| 234f0c4c RN |
1515 | |
| 1516 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1517 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 |
| 568997cf | 1518 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) |
| 234f0c4c RN |
1519 | |
| 1520 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1521 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 |
| 568997cf | 1522 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) |
| 234f0c4c RN |
1523 | |
| 1524 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1525 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 |
| 568997cf | 1526 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) |
| 234f0c4c RN |
1527 | |
| 1528 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | |
| 56ef28ac | 1529 | #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 |
| 568997cf | 1530 | #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) |
| 234f0c4c RN |
1531 | |
| 1532 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | |
| 56ef28ac | 1533 | #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 |
| 568997cf | 1534 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) |
| 234f0c4c RN |
1535 | |
| 1536 | /* Used by PRM_IRQENABLE_MPU_2 */ | |
| 56ef28ac | 1537 | #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 |
| 568997cf | 1538 | #define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) |
| 234f0c4c RN |
1539 | |
| 1540 | /* Used by PRM_IRQSTATUS_MPU_2 */ | |
| 56ef28ac | 1541 | #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 |
| 568997cf | 1542 | #define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) |
| 234f0c4c RN |
1543 | |
| 1544 | /* Used by PRM_IRQENABLE_MPU_2 */ | |
| 56ef28ac | 1545 | #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 |
| 568997cf | 1546 | #define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) |
| 234f0c4c RN |
1547 | |
| 1548 | /* Used by PRM_IRQSTATUS_MPU_2 */ | |
| 56ef28ac | 1549 | #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 |
| 568997cf | 1550 | #define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) |
| 234f0c4c RN |
1551 | |
| 1552 | /* Used by PRM_IRQENABLE_MPU_2 */ | |
| 56ef28ac | 1553 | #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 |
| 568997cf | 1554 | #define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) |
| 234f0c4c RN |
1555 | |
| 1556 | /* Used by PRM_IRQSTATUS_MPU_2 */ | |
| 56ef28ac | 1557 | #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 |
| 568997cf | 1558 | #define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) |
| 234f0c4c RN |
1559 | |
| 1560 | /* Used by PRM_IRQENABLE_MPU_2 */ | |
| 56ef28ac | 1561 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 |
| 568997cf | 1562 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) |
| 234f0c4c RN |
1563 | |
| 1564 | /* Used by PRM_IRQSTATUS_MPU_2 */ | |
| 56ef28ac | 1565 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 |
| 568997cf | 1566 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) |
| 234f0c4c RN |
1567 | |
| 1568 | /* Used by PRM_IRQENABLE_MPU_2 */ | |
| 56ef28ac | 1569 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 |
| 568997cf | 1570 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) |
| 234f0c4c RN |
1571 | |
| 1572 | /* Used by PRM_IRQSTATUS_MPU_2 */ | |
| 56ef28ac | 1573 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 |
| 568997cf | 1574 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) |
| 234f0c4c RN |
1575 | |
| 1576 | /* Used by PRM_IRQENABLE_MPU_2 */ | |
| 56ef28ac | 1577 | #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 |
| 568997cf | 1578 | #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) |
| 234f0c4c RN |
1579 | |
| 1580 | /* Used by PRM_IRQSTATUS_MPU_2 */ | |
| 56ef28ac | 1581 | #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 |
| 568997cf | 1582 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) |
| 234f0c4c RN |
1583 | |
| 1584 | /* Used by PRM_SRAM_COUNT */ | |
| 56ef28ac | 1585 | #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 |
| 568997cf | 1586 | #define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) |
| 234f0c4c RN |
1587 | |
| 1588 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | |
| 56ef28ac | 1589 | #define OMAP4430_VSTEPMAX_SHIFT 0 |
| 568997cf | 1590 | #define OMAP4430_VSTEPMAX_MASK (0xff << 0) |
| 234f0c4c RN |
1591 | |
| 1592 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | |
| 56ef28ac | 1593 | #define OMAP4430_VSTEPMIN_SHIFT 0 |
| 568997cf | 1594 | #define OMAP4430_VSTEPMIN_MASK (0xff << 0) |
| 234f0c4c RN |
1595 | |
| 1596 | /* Used by PRM_MODEM_IF_CTRL */ | |
| 56ef28ac | 1597 | #define OMAP4430_WAKE_MODEM_SHIFT 0 |
| 568997cf | 1598 | #define OMAP4430_WAKE_MODEM_MASK (1 << 0) |
| 234f0c4c RN |
1599 | |
| 1600 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1601 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 |
| 568997cf | 1602 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1603 | |
| 1604 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1605 | #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 |
| 568997cf | 1606 | #define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1607 | |
| 1608 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1609 | #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 |
| 568997cf | 1610 | #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
1611 | |
| 1612 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1613 | #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 |
| 568997cf | 1614 | #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
1615 | |
| 1616 | /* Used by PM_ABE_DMIC_WKDEP */ | |
| 56ef28ac | 1617 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 |
| 568997cf | 1618 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
1619 | |
| 1620 | /* Used by PM_ABE_DMIC_WKDEP */ | |
| 56ef28ac | 1621 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 |
| 568997cf | 1622 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1623 | |
| 1624 | /* Used by PM_ABE_DMIC_WKDEP */ | |
| 56ef28ac | 1625 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 |
| 568997cf | 1626 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1627 | |
| 1628 | /* Used by PM_ABE_DMIC_WKDEP */ | |
| 56ef28ac | 1629 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 |
| 568997cf | 1630 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
1631 | |
| 1632 | /* Used by PM_L4PER_DMTIMER10_WKDEP */ | |
| 56ef28ac | 1633 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 |
| 568997cf | 1634 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1635 | |
| 1636 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | |
| 56ef28ac | 1637 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 |
| 568997cf | 1638 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1639 | |
| 1640 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | |
| 56ef28ac | 1641 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 |
| 568997cf | 1642 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1643 | |
| 1644 | /* Used by PM_L4PER_DMTIMER2_WKDEP */ | |
| 56ef28ac | 1645 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 |
| 568997cf | 1646 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1647 | |
| 1648 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | |
| 56ef28ac | 1649 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 |
| 568997cf | 1650 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1651 | |
| 1652 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | |
| 56ef28ac | 1653 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 |
| 568997cf | 1654 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1655 | |
| 1656 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | |
| 56ef28ac | 1657 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 |
| 568997cf | 1658 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1659 | |
| 1660 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | |
| 56ef28ac | 1661 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 |
| 568997cf | 1662 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1663 | |
| 1664 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | |
| 56ef28ac | 1665 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 |
| 568997cf | 1666 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1667 | |
| 1668 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | |
| 56ef28ac | 1669 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 |
| 568997cf | 1670 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1671 | |
| 1672 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1673 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 |
| 568997cf | 1674 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) |
| 234f0c4c RN |
1675 | |
| 1676 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1677 | #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 |
| 568997cf | 1678 | #define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) |
| 234f0c4c RN |
1679 | |
| 1680 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1681 | #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 |
| 568997cf | 1682 | #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
1683 | |
| 1684 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1685 | #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 |
| 568997cf | 1686 | #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1687 | |
| 1688 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1689 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 |
| 568997cf | 1690 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) |
| 234f0c4c RN |
1691 | |
| 1692 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1693 | #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 |
| 568997cf | 1694 | #define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) |
| 234f0c4c RN |
1695 | |
| 1696 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1697 | #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 |
| 568997cf | 1698 | #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) |
| 234f0c4c RN |
1699 | |
| 1700 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1701 | #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 |
| 568997cf | 1702 | #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) |
| 234f0c4c RN |
1703 | |
| 1704 | /* Used by PM_WKUP_GPIO1_WKDEP */ | |
| 56ef28ac | 1705 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 |
| 568997cf | 1706 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1707 | |
| 1708 | /* Used by PM_WKUP_GPIO1_WKDEP */ | |
| 56ef28ac | 1709 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 |
| 568997cf | 1710 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1711 | |
| 1712 | /* Used by PM_WKUP_GPIO1_WKDEP */ | |
| 56ef28ac | 1713 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 |
| 568997cf | 1714 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1715 | |
| 1716 | /* Used by PM_L4PER_GPIO2_WKDEP */ | |
| 56ef28ac | 1717 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 |
| 568997cf | 1718 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1719 | |
| 1720 | /* Used by PM_L4PER_GPIO2_WKDEP */ | |
| 56ef28ac | 1721 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 |
| 568997cf | 1722 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1723 | |
| 1724 | /* Used by PM_L4PER_GPIO2_WKDEP */ | |
| 56ef28ac | 1725 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 |
| 568997cf | 1726 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1727 | |
| 1728 | /* Used by PM_L4PER_GPIO3_WKDEP */ | |
| 56ef28ac | 1729 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 |
| 568997cf | 1730 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1731 | |
| 1732 | /* Used by PM_L4PER_GPIO3_WKDEP */ | |
| 56ef28ac | 1733 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 |
| 568997cf | 1734 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1735 | |
| 1736 | /* Used by PM_L4PER_GPIO4_WKDEP */ | |
| 56ef28ac | 1737 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 |
| 568997cf | 1738 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1739 | |
| 1740 | /* Used by PM_L4PER_GPIO4_WKDEP */ | |
| 56ef28ac | 1741 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 |
| 568997cf | 1742 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1743 | |
| 1744 | /* Used by PM_L4PER_GPIO5_WKDEP */ | |
| 56ef28ac | 1745 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 |
| 568997cf | 1746 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1747 | |
| 1748 | /* Used by PM_L4PER_GPIO5_WKDEP */ | |
| 56ef28ac | 1749 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 |
| 568997cf | 1750 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1751 | |
| 1752 | /* Used by PM_L4PER_GPIO6_WKDEP */ | |
| 56ef28ac | 1753 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 |
| 568997cf | 1754 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1755 | |
| 1756 | /* Used by PM_L4PER_GPIO6_WKDEP */ | |
| 56ef28ac | 1757 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 |
| 568997cf | 1758 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1759 | |
| 1760 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1761 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 |
| 568997cf | 1762 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) |
| 234f0c4c RN |
1763 | |
| 1764 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1765 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 |
| 568997cf | 1766 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) |
| 234f0c4c RN |
1767 | |
| 1768 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1769 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 |
| 568997cf | 1770 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) |
| 234f0c4c RN |
1771 | |
| 1772 | /* Used by PM_DSS_DSS_WKDEP */ | |
| 56ef28ac | 1773 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 |
| 568997cf | 1774 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) |
| 234f0c4c RN |
1775 | |
| 1776 | /* Used by PM_L4PER_HECC1_WKDEP */ | |
| 56ef28ac | 1777 | #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 |
| 568997cf | 1778 | #define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1779 | |
| 1780 | /* Used by PM_L4PER_HECC2_WKDEP */ | |
| 56ef28ac | 1781 | #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 |
| 568997cf | 1782 | #define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1783 | |
| 1784 | /* Used by PM_L3INIT_HSI_WKDEP */ | |
| 56ef28ac | 1785 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 |
| 568997cf | 1786 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1787 | |
| 1788 | /* Used by PM_L3INIT_HSI_WKDEP */ | |
| 56ef28ac | 1789 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 |
| 568997cf | 1790 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1791 | |
| 1792 | /* Used by PM_L3INIT_HSI_WKDEP */ | |
| 56ef28ac | 1793 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 |
| 568997cf | 1794 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1795 | |
| 1796 | /* Used by PM_L4PER_I2C1_WKDEP */ | |
| 56ef28ac | 1797 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 |
| 568997cf | 1798 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
1799 | |
| 1800 | /* Used by PM_L4PER_I2C1_WKDEP */ | |
| 56ef28ac | 1801 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 |
| 568997cf | 1802 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1803 | |
| 1804 | /* Used by PM_L4PER_I2C1_WKDEP */ | |
| 56ef28ac | 1805 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 |
| 568997cf | 1806 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1807 | |
| 1808 | /* Used by PM_L4PER_I2C2_WKDEP */ | |
| 56ef28ac | 1809 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 |
| 568997cf | 1810 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
1811 | |
| 1812 | /* Used by PM_L4PER_I2C2_WKDEP */ | |
| 56ef28ac | 1813 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 |
| 568997cf | 1814 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1815 | |
| 1816 | /* Used by PM_L4PER_I2C2_WKDEP */ | |
| 56ef28ac | 1817 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 |
| 568997cf | 1818 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1819 | |
| 1820 | /* Used by PM_L4PER_I2C3_WKDEP */ | |
| 56ef28ac | 1821 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 |
| 568997cf | 1822 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
1823 | |
| 1824 | /* Used by PM_L4PER_I2C3_WKDEP */ | |
| 56ef28ac | 1825 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 |
| 568997cf | 1826 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1827 | |
| 1828 | /* Used by PM_L4PER_I2C3_WKDEP */ | |
| 56ef28ac | 1829 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 |
| 568997cf | 1830 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1831 | |
| 1832 | /* Used by PM_L4PER_I2C4_WKDEP */ | |
| 56ef28ac | 1833 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 |
| 568997cf | 1834 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
1835 | |
| 1836 | /* Used by PM_L4PER_I2C4_WKDEP */ | |
| 56ef28ac | 1837 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 |
| 568997cf | 1838 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1839 | |
| 1840 | /* Used by PM_L4PER_I2C4_WKDEP */ | |
| 56ef28ac | 1841 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 |
| 568997cf | 1842 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1843 | |
| 1844 | /* Used by PM_L4PER_I2C5_WKDEP */ | |
| 56ef28ac | 1845 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 |
| 568997cf | 1846 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
1847 | |
| 1848 | /* Used by PM_L4PER_I2C5_WKDEP */ | |
| 56ef28ac | 1849 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 |
| 568997cf | 1850 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1851 | |
| 1852 | /* Used by PM_WKUP_KEYBOARD_WKDEP */ | |
| 56ef28ac | 1853 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 |
| 568997cf | 1854 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1855 | |
| 1856 | /* Used by PM_ABE_MCASP_WKDEP */ | |
| 56ef28ac | 1857 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 |
| 568997cf | 1858 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
1859 | |
| 1860 | /* Used by PM_ABE_MCASP_WKDEP */ | |
| 56ef28ac | 1861 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 |
| 568997cf | 1862 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1863 | |
| 1864 | /* Used by PM_ABE_MCASP_WKDEP */ | |
| 56ef28ac | 1865 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 |
| 568997cf | 1866 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1867 | |
| 1868 | /* Used by PM_ABE_MCASP_WKDEP */ | |
| 56ef28ac | 1869 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 |
| 568997cf | 1870 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
1871 | |
| 1872 | /* Used by PM_L4PER_MCASP2_WKDEP */ | |
| 56ef28ac | 1873 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 |
| 568997cf | 1874 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
1875 | |
| 1876 | /* Used by PM_L4PER_MCASP2_WKDEP */ | |
| 56ef28ac | 1877 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 |
| 568997cf | 1878 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1879 | |
| 1880 | /* Used by PM_L4PER_MCASP2_WKDEP */ | |
| 56ef28ac | 1881 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 |
| 568997cf | 1882 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1883 | |
| 1884 | /* Used by PM_L4PER_MCASP2_WKDEP */ | |
| 56ef28ac | 1885 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 |
| 568997cf | 1886 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
1887 | |
| 1888 | /* Used by PM_L4PER_MCASP3_WKDEP */ | |
| 56ef28ac | 1889 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 |
| 568997cf | 1890 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
1891 | |
| 1892 | /* Used by PM_L4PER_MCASP3_WKDEP */ | |
| 56ef28ac | 1893 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 |
| 568997cf | 1894 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
1895 | |
| 1896 | /* Used by PM_L4PER_MCASP3_WKDEP */ | |
| 56ef28ac | 1897 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 |
| 568997cf | 1898 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1899 | |
| 1900 | /* Used by PM_L4PER_MCASP3_WKDEP */ | |
| 56ef28ac | 1901 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 |
| 568997cf | 1902 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
1903 | |
| 1904 | /* Used by PM_ABE_MCBSP1_WKDEP */ | |
| 56ef28ac | 1905 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 |
| 568997cf | 1906 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1907 | |
| 1908 | /* Used by PM_ABE_MCBSP1_WKDEP */ | |
| 56ef28ac | 1909 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 |
| 568997cf | 1910 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
1911 | |
| 1912 | /* Used by PM_ABE_MCBSP1_WKDEP */ | |
| 56ef28ac | 1913 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 |
| 568997cf | 1914 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
1915 | |
| 1916 | /* Used by PM_ABE_MCBSP2_WKDEP */ | |
| 56ef28ac | 1917 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 |
| 568997cf | 1918 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1919 | |
| 1920 | /* Used by PM_ABE_MCBSP2_WKDEP */ | |
| 56ef28ac | 1921 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 |
| 568997cf | 1922 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
1923 | |
| 1924 | /* Used by PM_ABE_MCBSP2_WKDEP */ | |
| 56ef28ac | 1925 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 |
| 568997cf | 1926 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
1927 | |
| 1928 | /* Used by PM_ABE_MCBSP3_WKDEP */ | |
| 56ef28ac | 1929 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 |
| 568997cf | 1930 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1931 | |
| 1932 | /* Used by PM_ABE_MCBSP3_WKDEP */ | |
| 56ef28ac | 1933 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 |
| 568997cf | 1934 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
1935 | |
| 1936 | /* Used by PM_ABE_MCBSP3_WKDEP */ | |
| 56ef28ac | 1937 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 |
| 568997cf | 1938 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
1939 | |
| 1940 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | |
| 56ef28ac | 1941 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 |
| 568997cf | 1942 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1943 | |
| 1944 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | |
| 56ef28ac | 1945 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 |
| 568997cf | 1946 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
1947 | |
| 1948 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | |
| 56ef28ac | 1949 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 |
| 568997cf | 1950 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
1951 | |
| 1952 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | |
| 56ef28ac | 1953 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 |
| 568997cf | 1954 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1955 | |
| 1956 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | |
| 56ef28ac | 1957 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 |
| 568997cf | 1958 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1959 | |
| 1960 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | |
| 56ef28ac | 1961 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 |
| 568997cf | 1962 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
1963 | |
| 1964 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | |
| 56ef28ac | 1965 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 |
| 568997cf | 1966 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
1967 | |
| 1968 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | |
| 56ef28ac | 1969 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 |
| 568997cf | 1970 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1971 | |
| 1972 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | |
| 56ef28ac | 1973 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 |
| 568997cf | 1974 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1975 | |
| 1976 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | |
| 56ef28ac | 1977 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 |
| 568997cf | 1978 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
1979 | |
| 1980 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | |
| 56ef28ac | 1981 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 |
| 568997cf | 1982 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1983 | |
| 1984 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | |
| 56ef28ac | 1985 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 |
| 568997cf | 1986 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
1987 | |
| 1988 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | |
| 56ef28ac | 1989 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 |
| 568997cf | 1990 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) |
| 234f0c4c RN |
1991 | |
| 1992 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | |
| 56ef28ac | 1993 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 |
| 568997cf | 1994 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
1995 | |
| 1996 | /* Used by PM_L3INIT_MMC1_WKDEP */ | |
| 56ef28ac | 1997 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 |
| 568997cf | 1998 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
1999 | |
| 2000 | /* Used by PM_L3INIT_MMC1_WKDEP */ | |
| 56ef28ac | 2001 | #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 |
| 568997cf | 2002 | #define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2003 | |
| 2004 | /* Used by PM_L3INIT_MMC1_WKDEP */ | |
| 56ef28ac | 2005 | #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 |
| 568997cf | 2006 | #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
2007 | |
| 2008 | /* Used by PM_L3INIT_MMC1_WKDEP */ | |
| 56ef28ac | 2009 | #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 |
| 568997cf | 2010 | #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2011 | |
| 2012 | /* Used by PM_L3INIT_MMC2_WKDEP */ | |
| 56ef28ac | 2013 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 |
| 568997cf | 2014 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2015 | |
| 2016 | /* Used by PM_L3INIT_MMC2_WKDEP */ | |
| 56ef28ac | 2017 | #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 |
| 568997cf | 2018 | #define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2019 | |
| 2020 | /* Used by PM_L3INIT_MMC2_WKDEP */ | |
| 56ef28ac | 2021 | #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 |
| 568997cf | 2022 | #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
2023 | |
| 2024 | /* Used by PM_L3INIT_MMC2_WKDEP */ | |
| 56ef28ac | 2025 | #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 |
| 568997cf | 2026 | #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2027 | |
| 2028 | /* Used by PM_L3INIT_MMC6_WKDEP */ | |
| 56ef28ac | 2029 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 |
| 568997cf | 2030 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2031 | |
| 2032 | /* Used by PM_L3INIT_MMC6_WKDEP */ | |
| 56ef28ac | 2033 | #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 |
| 568997cf | 2034 | #define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2035 | |
| 2036 | /* Used by PM_L3INIT_MMC6_WKDEP */ | |
| 56ef28ac | 2037 | #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 |
| 568997cf | 2038 | #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2039 | |
| 2040 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | |
| 56ef28ac | 2041 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 |
| 568997cf | 2042 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2043 | |
| 2044 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | |
| 56ef28ac | 2045 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 |
| 568997cf | 2046 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2047 | |
| 2048 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | |
| 56ef28ac | 2049 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 |
| 568997cf | 2050 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
2051 | |
| 2052 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | |
| 56ef28ac | 2053 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 |
| 568997cf | 2054 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2055 | |
| 2056 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | |
| 56ef28ac | 2057 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 |
| 568997cf | 2058 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2059 | |
| 2060 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | |
| 56ef28ac | 2061 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 |
| 568997cf | 2062 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
2063 | |
| 2064 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | |
| 56ef28ac | 2065 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 |
| 568997cf | 2066 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2067 | |
| 2068 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | |
| 56ef28ac | 2069 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 |
| 568997cf | 2070 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2071 | |
| 2072 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | |
| 56ef28ac | 2073 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 |
| 568997cf | 2074 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
2075 | |
| 2076 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | |
| 56ef28ac | 2077 | #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 |
| 568997cf | 2078 | #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2079 | |
| 2080 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | |
| 56ef28ac | 2081 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 |
| 568997cf | 2082 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2083 | |
| 2084 | /* Used by PM_ABE_PDM_WKDEP */ | |
| 56ef28ac | 2085 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 |
| 568997cf | 2086 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
2087 | |
| 2088 | /* Used by PM_ABE_PDM_WKDEP */ | |
| 56ef28ac | 2089 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 |
| 568997cf | 2090 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
2091 | |
| 2092 | /* Used by PM_ABE_PDM_WKDEP */ | |
| 56ef28ac | 2093 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 |
| 568997cf | 2094 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2095 | |
| 2096 | /* Used by PM_ABE_PDM_WKDEP */ | |
| 56ef28ac | 2097 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 |
| 568997cf | 2098 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2099 | |
| 2100 | /* Used by PM_WKUP_RTC_WKDEP */ | |
| 56ef28ac | 2101 | #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 |
| 568997cf | 2102 | #define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2103 | |
| 2104 | /* Used by PM_L3INIT_SATA_WKDEP */ | |
| 56ef28ac | 2105 | #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 |
| 568997cf | 2106 | #define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2107 | |
| 2108 | /* Used by PM_L3INIT_SATA_WKDEP */ | |
| 56ef28ac | 2109 | #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 |
| 568997cf | 2110 | #define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2111 | |
| 2112 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | |
| 56ef28ac | 2113 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 |
| 568997cf | 2114 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
2115 | |
| 2116 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | |
| 56ef28ac | 2117 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 |
| 568997cf | 2118 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
2119 | |
| 2120 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | |
| 56ef28ac | 2121 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 |
| 568997cf | 2122 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2123 | |
| 2124 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | |
| 56ef28ac | 2125 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 |
| 568997cf | 2126 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2127 | |
| 2128 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | |
| 56ef28ac | 2129 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 |
| 568997cf | 2130 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) |
| 234f0c4c RN |
2131 | |
| 2132 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | |
| 56ef28ac | 2133 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 |
| 568997cf | 2134 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) |
| 234f0c4c RN |
2135 | |
| 2136 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | |
| 56ef28ac | 2137 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 |
| 568997cf | 2138 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2139 | |
| 2140 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | |
| 56ef28ac | 2141 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 |
| 568997cf | 2142 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2143 | |
| 2144 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | |
| 56ef28ac | 2145 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 |
| 568997cf | 2146 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2147 | |
| 2148 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | |
| 56ef28ac | 2149 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 |
| 568997cf | 2150 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2151 | |
| 2152 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | |
| 56ef28ac | 2153 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 |
| 568997cf | 2154 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2155 | |
| 2156 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | |
| 56ef28ac | 2157 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 |
| 568997cf | 2158 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2159 | |
| 2160 | /* Used by PM_ALWON_SR_MPU_WKDEP */ | |
| 56ef28ac | 2161 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 |
| 568997cf | 2162 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2163 | |
| 2164 | /* Used by PM_WKUP_TIMER12_WKDEP */ | |
| 56ef28ac | 2165 | #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 |
| 568997cf | 2166 | #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2167 | |
| 2168 | /* Used by PM_WKUP_TIMER1_WKDEP */ | |
| 56ef28ac | 2169 | #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 |
| 568997cf | 2170 | #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2171 | |
| 2172 | /* Used by PM_ABE_TIMER5_WKDEP */ | |
| 56ef28ac | 2173 | #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 |
| 568997cf | 2174 | #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2175 | |
| 2176 | /* Used by PM_ABE_TIMER5_WKDEP */ | |
| 56ef28ac | 2177 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 |
| 568997cf | 2178 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2179 | |
| 2180 | /* Used by PM_ABE_TIMER6_WKDEP */ | |
| 56ef28ac | 2181 | #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 |
| 568997cf | 2182 | #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2183 | |
| 2184 | /* Used by PM_ABE_TIMER6_WKDEP */ | |
| 56ef28ac | 2185 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 |
| 568997cf | 2186 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2187 | |
| 2188 | /* Used by PM_ABE_TIMER7_WKDEP */ | |
| 56ef28ac | 2189 | #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 |
| 568997cf | 2190 | #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2191 | |
| 2192 | /* Used by PM_ABE_TIMER7_WKDEP */ | |
| 56ef28ac | 2193 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 |
| 568997cf | 2194 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2195 | |
| 2196 | /* Used by PM_ABE_TIMER8_WKDEP */ | |
| 56ef28ac | 2197 | #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 |
| 568997cf | 2198 | #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2199 | |
| 2200 | /* Used by PM_ABE_TIMER8_WKDEP */ | |
| 56ef28ac | 2201 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 |
| 568997cf | 2202 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2203 | |
| 2204 | /* Used by PM_L4PER_UART1_WKDEP */ | |
| 56ef28ac | 2205 | #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 |
| 568997cf | 2206 | #define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2207 | |
| 2208 | /* Used by PM_L4PER_UART1_WKDEP */ | |
| 56ef28ac | 2209 | #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 |
| 568997cf | 2210 | #define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
2211 | |
| 2212 | /* Used by PM_L4PER_UART2_WKDEP */ | |
| 56ef28ac | 2213 | #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 |
| 568997cf | 2214 | #define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2215 | |
| 2216 | /* Used by PM_L4PER_UART2_WKDEP */ | |
| 56ef28ac | 2217 | #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 |
| 568997cf | 2218 | #define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
2219 | |
| 2220 | /* Used by PM_L4PER_UART3_WKDEP */ | |
| 56ef28ac | 2221 | #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 |
| 568997cf | 2222 | #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2223 | |
| 2224 | /* Used by PM_L4PER_UART3_WKDEP */ | |
| 56ef28ac | 2225 | #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 |
| 568997cf | 2226 | #define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2227 | |
| 2228 | /* Used by PM_L4PER_UART3_WKDEP */ | |
| 56ef28ac | 2229 | #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 |
| 568997cf | 2230 | #define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
2231 | |
| 2232 | /* Used by PM_L4PER_UART3_WKDEP */ | |
| 56ef28ac | 2233 | #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 |
| 568997cf | 2234 | #define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) |
| 234f0c4c RN |
2235 | |
| 2236 | /* Used by PM_L4PER_UART4_WKDEP */ | |
| 56ef28ac | 2237 | #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 |
| 568997cf | 2238 | #define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2239 | |
| 2240 | /* Used by PM_L4PER_UART4_WKDEP */ | |
| 56ef28ac | 2241 | #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 |
| 568997cf | 2242 | #define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
2243 | |
| 2244 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | |
| 56ef28ac | 2245 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 |
| 568997cf | 2246 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2247 | |
| 2248 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | |
| 56ef28ac | 2249 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 |
| 568997cf | 2250 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2251 | |
| 2252 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | |
| 56ef28ac | 2253 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 |
| 568997cf | 2254 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2255 | |
| 2256 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | |
| 56ef28ac | 2257 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 |
| 568997cf | 2258 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2259 | |
| 2260 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | |
| 56ef28ac | 2261 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 |
| 568997cf | 2262 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2263 | |
| 2264 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | |
| 56ef28ac | 2265 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 |
| 568997cf | 2266 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2267 | |
| 2268 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | |
| 56ef28ac | 2269 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 |
| 568997cf | 2270 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2271 | |
| 2272 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | |
| 56ef28ac | 2273 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 |
| 568997cf | 2274 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2275 | |
| 2276 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | |
| 56ef28ac | 2277 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 |
| 568997cf | 2278 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2279 | |
| 2280 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | |
| 56ef28ac | 2281 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 |
| 568997cf | 2282 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2283 | |
| 2284 | /* Used by PM_WKUP_USIM_WKDEP */ | |
| 56ef28ac | 2285 | #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 |
| 568997cf | 2286 | #define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2287 | |
| 2288 | /* Used by PM_WKUP_USIM_WKDEP */ | |
| 56ef28ac | 2289 | #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 |
| 568997cf | 2290 | #define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) |
| 234f0c4c RN |
2291 | |
| 2292 | /* Used by PM_WKUP_WDT2_WKDEP */ | |
| 56ef28ac | 2293 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 |
| 568997cf | 2294 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2295 | |
| 2296 | /* Used by PM_WKUP_WDT2_WKDEP */ | |
| 56ef28ac | 2297 | #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 |
| 568997cf | 2298 | #define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2299 | |
| 2300 | /* Used by PM_ABE_WDT3_WKDEP */ | |
| 56ef28ac | 2301 | #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 |
| 568997cf | 2302 | #define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) |
| 234f0c4c RN |
2303 | |
| 2304 | /* Used by PM_L3INIT_HSI_WKDEP */ | |
| 56ef28ac | 2305 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 |
| 568997cf | 2306 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) |
| 234f0c4c RN |
2307 | |
| 2308 | /* Used by PM_L3INIT_XHPI_WKDEP */ | |
| 56ef28ac | 2309 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 |
| 568997cf | 2310 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) |
| 234f0c4c RN |
2311 | |
| 2312 | /* Used by PRM_IO_PMCTRL */ | |
| 56ef28ac | 2313 | #define OMAP4430_WUCLK_CTRL_SHIFT 8 |
| 568997cf | 2314 | #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) |
| 234f0c4c RN |
2315 | |
| 2316 | /* Used by PRM_IO_PMCTRL */ | |
| 56ef28ac | 2317 | #define OMAP4430_WUCLK_STATUS_SHIFT 9 |
| 568997cf RN |
2318 | #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) |
| 2319 | ||
| 2320 | /* Used by REVISION_PRM */ | |
| 2321 | #define OMAP4430_X_MAJOR_SHIFT 8 | |
| 2322 | #define OMAP4430_X_MAJOR_MASK (0x7 << 8) | |
| 2323 | ||
| 2324 | /* Used by REVISION_PRM */ | |
| 2325 | #define OMAP4430_Y_MINOR_SHIFT 0 | |
| 2326 | #define OMAP4430_Y_MINOR_MASK (0x3f << 0) | |
| 234f0c4c | 2327 | #endif |