[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / powerdomains44xx_data.c

/*
 * OMAP4 Power domains framework
 *
 * Copyright (C) 2009-2011 Texas Instruments, Inc.
 * Copyright (C) 2009-2011 Nokia Corporation
 *
 * Abhijit Pagare (abhijitpagare@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 * Paul Walmsley (paul@pwsan.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>

#include "powerdomain.h"

#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm-regbits-44xx.h"
#include "prm44xx.h"
#include "prcm_mpu44xx.h"

/* core_44xx_pwrdm: CORE power domain */
static struct powerdomain core_44xx_pwrdm = {
	.name		  = "core_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_CORE_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 5,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* core_nret_bank */
		[1] = PWRSTS_RET,	/* core_ocmram */
		[2] = PWRSTS_RET,	/* core_other_bank */
		[3] = PWRSTS_OFF_RET,	/* ducati_l2ram */
		[4] = PWRSTS_OFF_RET,	/* ducati_unicache */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* core_nret_bank */
		[1] = PWRSTS_ON,	/* core_ocmram */
		[2] = PWRSTS_ON,	/* core_other_bank */
		[3] = PWRSTS_ON,	/* ducati_l2ram */
		[4] = PWRSTS_ON,	/* ducati_unicache */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* gfx_44xx_pwrdm: 3D accelerator power domain */
static struct powerdomain gfx_44xx_pwrdm = {
	.name		  = "gfx_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_GFX_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* gfx_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* gfx_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* abe_44xx_pwrdm: Audio back end power domain */
static struct powerdomain abe_44xx_pwrdm = {
	.name		  = "abe_pwrdm",
	.voltdm		  = { .name = "iva" },
	.prcm_offs	  = OMAP4430_PRM_ABE_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF,
	.banks		  = 2,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_RET,	/* aessmem */
		[1] = PWRSTS_OFF,	/* periphmem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* aessmem */
		[1] = PWRSTS_ON,	/* periphmem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* dss_44xx_pwrdm: Display subsystem power domain */
static struct powerdomain dss_44xx_pwrdm = {
	.name		  = "dss_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_DSS_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* dss_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* dss_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* tesla_44xx_pwrdm: Tesla processor power domain */
static struct powerdomain tesla_44xx_pwrdm = {
	.name		  = "tesla_pwrdm",
	.voltdm		  = { .name = "iva" },
	.prcm_offs	  = OMAP4430_PRM_TESLA_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 3,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_RET,	/* tesla_edma */
		[1] = PWRSTS_OFF_RET,	/* tesla_l1 */
		[2] = PWRSTS_OFF_RET,	/* tesla_l2 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* tesla_edma */
		[1] = PWRSTS_ON,	/* tesla_l1 */
		[2] = PWRSTS_ON,	/* tesla_l2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* wkup_44xx_pwrdm: Wake-up power domain */
static struct powerdomain wkup_44xx_pwrdm = {
	.name		  = "wkup_pwrdm",
	.voltdm		  = { .name = "wakeup" },
	.prcm_offs	  = OMAP4430_PRM_WKUP_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* wkup_bank */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* wkup_bank */
	},
};

/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
static struct powerdomain cpu0_44xx_pwrdm = {
	.name		  = "cpu0_pwrdm",
	.voltdm		  = { .name = "mpu" },
	.prcm_offs	  = OMAP4430_PRCM_MPU_CPU0_INST,
	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu0_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu0_l1 */
	},
};

/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
static struct powerdomain cpu1_44xx_pwrdm = {
	.name		  = "cpu1_pwrdm",
	.voltdm		  = { .name = "mpu" },
	.prcm_offs	  = OMAP4430_PRCM_MPU_CPU1_INST,
	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu1_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu1_l1 */
	},
};

/* emu_44xx_pwrdm: Emulation power domain */
static struct powerdomain emu_44xx_pwrdm = {
	.name		  = "emu_pwrdm",
	.voltdm		  = { .name = "wakeup" },
	.prcm_offs	  = OMAP4430_PRM_EMU_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* emu_bank */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* emu_bank */
	},
};

/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
static struct powerdomain mpu_44xx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.voltdm		  = { .name = "mpu" },
	.prcm_offs	  = OMAP4430_PRM_MPU_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 3,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* mpu_l1 */
		[1] = PWRSTS_OFF_RET,	/* mpu_l2 */
		[2] = PWRSTS_RET,	/* mpu_ram */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* mpu_l1 */
		[1] = PWRSTS_ON,	/* mpu_l2 */
		[2] = PWRSTS_ON,	/* mpu_ram */
	},
};

/* ivahd_44xx_pwrdm: IVA-HD power domain */
static struct powerdomain ivahd_44xx_pwrdm = {
	.name		  = "ivahd_pwrdm",
	.voltdm		  = { .name = "iva" },
	.prcm_offs	  = OMAP4430_PRM_IVAHD_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF,
	.banks		  = 4,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* hwa_mem */
		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* hwa_mem */
		[1] = PWRSTS_ON,	/* sl2_mem */
		[2] = PWRSTS_ON,	/* tcm1_mem */
		[3] = PWRSTS_ON,	/* tcm2_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* cam_44xx_pwrdm: Camera subsystem power domain */
static struct powerdomain cam_44xx_pwrdm = {
	.name		  = "cam_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_CAM_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* cam_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cam_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* l3init_44xx_pwrdm: L3 initators pheripherals power domain  */
static struct powerdomain l3init_44xx_pwrdm = {
	.name		  = "l3init_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_L3INIT_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* l3init_bank1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* l3init_bank1 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* l4per_44xx_pwrdm: Target peripherals power domain */
static struct powerdomain l4per_44xx_pwrdm = {
	.name		  = "l4per_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_L4PER_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* nonretained_bank */
		[1] = PWRSTS_RET,	/* retained_bank */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* nonretained_bank */
		[1] = PWRSTS_ON,	/* retained_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/*
 * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
 * domain
 */
static struct powerdomain always_on_core_44xx_pwrdm = {
	.name		  = "always_on_core_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_ALWAYS_ON_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain cefuse_44xx_pwrdm = {
	.name		  = "cefuse_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_CEFUSE_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/*
 * The following power domains are not under SW control
 *
 * always_on_iva
 * always_on_mpu
 * stdefuse
 */

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap44xx[] __initdata = {
	&core_44xx_pwrdm,
	&gfx_44xx_pwrdm,
	&abe_44xx_pwrdm,
	&dss_44xx_pwrdm,
	&tesla_44xx_pwrdm,
	&wkup_44xx_pwrdm,
	&cpu0_44xx_pwrdm,
	&cpu1_44xx_pwrdm,
	&emu_44xx_pwrdm,
	&mpu_44xx_pwrdm,
	&ivahd_44xx_pwrdm,
	&cam_44xx_pwrdm,
	&l3init_44xx_pwrdm,
	&l4per_44xx_pwrdm,
	&always_on_core_44xx_pwrdm,
	&cefuse_44xx_pwrdm,
	NULL
};

void __init omap44xx_powerdomains_init(void)
{
	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
	pwrdm_register_pwrdms(powerdomains_omap44xx);
	pwrdm_complete_init();
}
Commit	Line	Data
f37c6dfa AP	1	/*
	2	* OMAP4 Power domains framework
	3	*
9a2a3603	4	* Copyright (C) 2009-2011 Texas Instruments, Inc.
4cb49fec	5	* Copyright (C) 2009-2011 Nokia Corporation
f37c6dfa AP	6	*
	7	* Abhijit Pagare (abhijitpagare@ti.com)
	8	* Benoit Cousson (b-cousson@ti.com)
79328706	9	* Paul Walmsley (paul@pwsan.com)
f37c6dfa AP	10	*
	11	* This file is automatically generated from the OMAP hardware databases.
	12	* We respectfully ask that any modifications to this file be coordinated
	13	* with the public linux-omap@vger.kernel.org mailing list and the
	14	* authors above to ensure that the autogeneration scripts are kept
	15	* up-to-date with the file contents.
	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License version 2 as
	19	* published by the Free Software Foundation.
	20	*/
	21
6e01478a PW	22	#include <linux/kernel.h>
6e01478a PW	23	#include <linux/init.h>
f37c6dfa	24
72e06d08	25	#include "powerdomain.h"
f37c6dfa AP	26
f37c6dfa AP	27	#include "prcm-common.h"
a64bb9cd	28	#include "prcm44xx.h"
f37c6dfa	29	#include "prm-regbits-44xx.h"
d198b514 PW	30	#include "prm44xx.h"
d198b514 PW	31	#include "prcm_mpu44xx.h"
f37c6dfa	32
f37c6dfa AP	33	/* core_44xx_pwrdm: CORE power domain */
	34	static struct powerdomain core_44xx_pwrdm = {
	35	.name = "core_pwrdm",
7e1b9405	36	.voltdm = { .name = "core" },
cdb54c44	37	.prcm_offs = OMAP4430_PRM_CORE_INST,
a64bb9cd	38	.prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa AP	39	.pwrsts = PWRSTS_RET_ON,
	40	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	41	.banks = 5,
	42	.pwrsts_mem_ret = {
4cb49fec	43	[0] = PWRSTS_OFF, /* core_nret_bank */
9a2a3603	44	[1] = PWRSTS_RET, /* core_ocmram */
4cb49fec	45	[2] = PWRSTS_RET, /* core_other_bank */
f37c6dfa AP	46	[3] = PWRSTS_OFF_RET, /* ducati_l2ram */
	47	[4] = PWRSTS_OFF_RET, /* ducati_unicache */
	48	},
	49	.pwrsts_mem_on = {
4cb49fec	50	[0] = PWRSTS_ON, /* core_nret_bank */
9a2a3603	51	[1] = PWRSTS_ON, /* core_ocmram */
4cb49fec PW	52	[2] = PWRSTS_ON, /* core_other_bank */
	53	[3] = PWRSTS_ON, /* ducati_l2ram */
	54	[4] = PWRSTS_ON, /* ducati_unicache */
f37c6dfa	55	},
0fef6583	56	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa AP	57	};
	58
	59	/* gfx_44xx_pwrdm: 3D accelerator power domain */
	60	static struct powerdomain gfx_44xx_pwrdm = {
	61	.name = "gfx_pwrdm",
7e1b9405	62	.voltdm = { .name = "core" },
cdb54c44	63	.prcm_offs = OMAP4430_PRM_GFX_INST,
a64bb9cd	64	.prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa AP	65	.pwrsts = PWRSTS_OFF_ON,
	66	.banks = 1,
	67	.pwrsts_mem_ret = {
4cb49fec	68	[0] = PWRSTS_OFF, /* gfx_mem */
f37c6dfa AP	69	},
f37c6dfa AP	70	.pwrsts_mem_on = {
4cb49fec	71	[0] = PWRSTS_ON, /* gfx_mem */
f37c6dfa	72	},
0fef6583	73	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa AP	74	};
	75
	76	/* abe_44xx_pwrdm: Audio back end power domain */
	77	static struct powerdomain abe_44xx_pwrdm = {
	78	.name = "abe_pwrdm",
7e1b9405	79	.voltdm = { .name = "iva" },
cdb54c44	80	.prcm_offs = OMAP4430_PRM_ABE_INST,
a64bb9cd	81	.prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa	82	.pwrsts = PWRSTS_OFF_RET_ON,
3ed4566e	83	.pwrsts_logic_ret = PWRSTS_OFF,
f37c6dfa AP	84	.banks = 2,
f37c6dfa AP	85	.pwrsts_mem_ret = {
4cb49fec PW	86	[0] = PWRSTS_RET, /* aessmem */
4cb49fec PW	87	[1] = PWRSTS_OFF, /* periphmem */
f37c6dfa AP	88	},
f37c6dfa AP	89	.pwrsts_mem_on = {
4cb49fec PW	90	[0] = PWRSTS_ON, /* aessmem */
4cb49fec PW	91	[1] = PWRSTS_ON, /* periphmem */
f37c6dfa	92	},
0fef6583	93	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa AP	94	};
	95
	96	/* dss_44xx_pwrdm: Display subsystem power domain */
	97	static struct powerdomain dss_44xx_pwrdm = {
	98	.name = "dss_pwrdm",
7e1b9405	99	.voltdm = { .name = "core" },
cdb54c44	100	.prcm_offs = OMAP4430_PRM_DSS_INST,
a64bb9cd	101	.prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa	102	.pwrsts = PWRSTS_OFF_RET_ON,
bb722f33	103	.pwrsts_logic_ret = PWRSTS_OFF,
f37c6dfa AP	104	.banks = 1,
f37c6dfa AP	105	.pwrsts_mem_ret = {
4cb49fec	106	[0] = PWRSTS_OFF, /* dss_mem */
f37c6dfa AP	107	},
f37c6dfa AP	108	.pwrsts_mem_on = {
4cb49fec	109	[0] = PWRSTS_ON, /* dss_mem */
f37c6dfa	110	},
0fef6583	111	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa AP	112	};
	113
	114	/* tesla_44xx_pwrdm: Tesla processor power domain */
	115	static struct powerdomain tesla_44xx_pwrdm = {
	116	.name = "tesla_pwrdm",
7e1b9405	117	.voltdm = { .name = "iva" },
cdb54c44	118	.prcm_offs = OMAP4430_PRM_TESLA_INST,
a64bb9cd	119	.prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa AP	120	.pwrsts = PWRSTS_OFF_RET_ON,
	121	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	122	.banks = 3,
	123	.pwrsts_mem_ret = {
4cb49fec	124	[0] = PWRSTS_RET, /* tesla_edma */
f37c6dfa AP	125	[1] = PWRSTS_OFF_RET, /* tesla_l1 */
	126	[2] = PWRSTS_OFF_RET, /* tesla_l2 */
	127	},
	128	.pwrsts_mem_on = {
4cb49fec PW	129	[0] = PWRSTS_ON, /* tesla_edma */
	130	[1] = PWRSTS_ON, /* tesla_l1 */
	131	[2] = PWRSTS_ON, /* tesla_l2 */
f37c6dfa	132	},
0fef6583	133	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa AP	134	};
	135
	136	/* wkup_44xx_pwrdm: Wake-up power domain */
	137	static struct powerdomain wkup_44xx_pwrdm = {
	138	.name = "wkup_pwrdm",
7e1b9405	139	.voltdm = { .name = "wakeup" },
cdb54c44	140	.prcm_offs = OMAP4430_PRM_WKUP_INST,
a64bb9cd	141	.prcm_partition = OMAP4430_PRM_PARTITION,
d3353e16	142	.pwrsts = PWRSTS_ON,
f37c6dfa AP	143	.banks = 1,
f37c6dfa AP	144	.pwrsts_mem_ret = {
4cb49fec	145	[0] = PWRSTS_OFF, /* wkup_bank */
f37c6dfa AP	146	},
f37c6dfa AP	147	.pwrsts_mem_on = {
4cb49fec	148	[0] = PWRSTS_ON, /* wkup_bank */
f37c6dfa AP	149	},
	150	};
	151
	152	/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
	153	static struct powerdomain cpu0_44xx_pwrdm = {
	154	.name = "cpu0_pwrdm",
7e1b9405	155	.voltdm = { .name = "mpu" },
cdb54c44	156	.prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST,
a64bb9cd	157	.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
f37c6dfa AP	158	.pwrsts = PWRSTS_OFF_RET_ON,
	159	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	160	.banks = 1,
	161	.pwrsts_mem_ret = {
	162	[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
	163	},
	164	.pwrsts_mem_on = {
4cb49fec	165	[0] = PWRSTS_ON, /* cpu0_l1 */
f37c6dfa AP	166	},
	167	};
	168
	169	/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
	170	static struct powerdomain cpu1_44xx_pwrdm = {
	171	.name = "cpu1_pwrdm",
7e1b9405	172	.voltdm = { .name = "mpu" },
cdb54c44	173	.prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST,
a64bb9cd	174	.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
f37c6dfa AP	175	.pwrsts = PWRSTS_OFF_RET_ON,
	176	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	177	.banks = 1,
	178	.pwrsts_mem_ret = {
	179	[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
	180	},
	181	.pwrsts_mem_on = {
4cb49fec	182	[0] = PWRSTS_ON, /* cpu1_l1 */
f37c6dfa AP	183	},
	184	};
	185
	186	/* emu_44xx_pwrdm: Emulation power domain */
	187	static struct powerdomain emu_44xx_pwrdm = {
	188	.name = "emu_pwrdm",
7e1b9405	189	.voltdm = { .name = "wakeup" },
cdb54c44	190	.prcm_offs = OMAP4430_PRM_EMU_INST,
a64bb9cd	191	.prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa AP	192	.pwrsts = PWRSTS_OFF_ON,
	193	.banks = 1,
	194	.pwrsts_mem_ret = {
4cb49fec	195	[0] = PWRSTS_OFF, /* emu_bank */
f37c6dfa AP	196	},
f37c6dfa AP	197	.pwrsts_mem_on = {
4cb49fec	198	[0] = PWRSTS_ON, /* emu_bank */
f37c6dfa AP	199	},
	200	};
	201
	202	/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
	203	static struct powerdomain mpu_44xx_pwrdm = {
	204	.name = "mpu_pwrdm",
7e1b9405	205	.voltdm = { .name = "mpu" },
cdb54c44	206	.prcm_offs = OMAP4430_PRM_MPU_INST,
a64bb9cd	207	.prcm_partition = OMAP4430_PRM_PARTITION,
a57341f7	208	.pwrsts = PWRSTS_RET_ON,
f37c6dfa AP	209	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	210	.banks = 3,
	211	.pwrsts_mem_ret = {
	212	[0] = PWRSTS_OFF_RET, /* mpu_l1 */
	213	[1] = PWRSTS_OFF_RET, /* mpu_l2 */
4cb49fec	214	[2] = PWRSTS_RET, /* mpu_ram */
f37c6dfa AP	215	},
f37c6dfa AP	216	.pwrsts_mem_on = {
4cb49fec PW	217	[0] = PWRSTS_ON, /* mpu_l1 */
	218	[1] = PWRSTS_ON, /* mpu_l2 */
	219	[2] = PWRSTS_ON, /* mpu_ram */
f37c6dfa AP	220	},
	221	};
	222
	223	/* ivahd_44xx_pwrdm: IVA-HD power domain */
	224	static struct powerdomain ivahd_44xx_pwrdm = {
	225	.name = "ivahd_pwrdm",
7e1b9405	226	.voltdm = { .name = "iva" },
cdb54c44	227	.prcm_offs = OMAP4430_PRM_IVAHD_INST,
a64bb9cd	228	.prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa	229	.pwrsts = PWRSTS_OFF_RET_ON,
3ed4566e	230	.pwrsts_logic_ret = PWRSTS_OFF,
f37c6dfa AP	231	.banks = 4,
f37c6dfa AP	232	.pwrsts_mem_ret = {
4cb49fec	233	[0] = PWRSTS_OFF, /* hwa_mem */
f37c6dfa AP	234	[1] = PWRSTS_OFF_RET, /* sl2_mem */
	235	[2] = PWRSTS_OFF_RET, /* tcm1_mem */
	236	[3] = PWRSTS_OFF_RET, /* tcm2_mem */
	237	},
	238	.pwrsts_mem_on = {
4cb49fec PW	239	[0] = PWRSTS_ON, /* hwa_mem */
	240	[1] = PWRSTS_ON, /* sl2_mem */
	241	[2] = PWRSTS_ON, /* tcm1_mem */
	242	[3] = PWRSTS_ON, /* tcm2_mem */
f37c6dfa	243	},
0fef6583	244	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa AP	245	};
	246
	247	/* cam_44xx_pwrdm: Camera subsystem power domain */
	248	static struct powerdomain cam_44xx_pwrdm = {
	249	.name = "cam_pwrdm",
7e1b9405	250	.voltdm = { .name = "core" },
cdb54c44	251	.prcm_offs = OMAP4430_PRM_CAM_INST,
a64bb9cd	252	.prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa AP	253	.pwrsts = PWRSTS_OFF_ON,
	254	.banks = 1,
	255	.pwrsts_mem_ret = {
4cb49fec	256	[0] = PWRSTS_OFF, /* cam_mem */
f37c6dfa AP	257	},
f37c6dfa AP	258	.pwrsts_mem_on = {
4cb49fec	259	[0] = PWRSTS_ON, /* cam_mem */
f37c6dfa	260	},
0fef6583	261	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa AP	262	};
	263
	264	/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
	265	static struct powerdomain l3init_44xx_pwrdm = {
	266	.name = "l3init_pwrdm",
7e1b9405	267	.voltdm = { .name = "core" },
cdb54c44	268	.prcm_offs = OMAP4430_PRM_L3INIT_INST,
a64bb9cd	269	.prcm_partition = OMAP4430_PRM_PARTITION,
80f09365	270	.pwrsts = PWRSTS_RET_ON,
f37c6dfa AP	271	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	272	.banks = 1,
	273	.pwrsts_mem_ret = {
4cb49fec	274	[0] = PWRSTS_OFF, /* l3init_bank1 */
f37c6dfa AP	275	},
f37c6dfa AP	276	.pwrsts_mem_on = {
4cb49fec	277	[0] = PWRSTS_ON, /* l3init_bank1 */
f37c6dfa	278	},
0fef6583	279	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa AP	280	};
	281
	282	/* l4per_44xx_pwrdm: Target peripherals power domain */
	283	static struct powerdomain l4per_44xx_pwrdm = {
	284	.name = "l4per_pwrdm",
7e1b9405	285	.voltdm = { .name = "core" },
cdb54c44	286	.prcm_offs = OMAP4430_PRM_L4PER_INST,
a64bb9cd	287	.prcm_partition = OMAP4430_PRM_PARTITION,
474e7aeb	288	.pwrsts = PWRSTS_RET_ON,
f37c6dfa AP	289	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	290	.banks = 2,
	291	.pwrsts_mem_ret = {
4cb49fec PW	292	[0] = PWRSTS_OFF, /* nonretained_bank */
4cb49fec PW	293	[1] = PWRSTS_RET, /* retained_bank */
f37c6dfa AP	294	},
f37c6dfa AP	295	.pwrsts_mem_on = {
4cb49fec PW	296	[0] = PWRSTS_ON, /* nonretained_bank */
4cb49fec PW	297	[1] = PWRSTS_ON, /* retained_bank */
f37c6dfa	298	},
0fef6583	299	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa AP	300	};
	301
	302	/*
	303	* always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
	304	* domain
	305	*/
	306	static struct powerdomain always_on_core_44xx_pwrdm = {
	307	.name = "always_on_core_pwrdm",
7e1b9405	308	.voltdm = { .name = "core" },
cdb54c44	309	.prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST,
a64bb9cd	310	.prcm_partition = OMAP4430_PRM_PARTITION,
d3353e16	311	.pwrsts = PWRSTS_ON,
f37c6dfa AP	312	};
	313
	314	/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
	315	static struct powerdomain cefuse_44xx_pwrdm = {
	316	.name = "cefuse_pwrdm",
7e1b9405	317	.voltdm = { .name = "core" },
cdb54c44	318	.prcm_offs = OMAP4430_PRM_CEFUSE_INST,
a64bb9cd	319	.prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa	320	.pwrsts = PWRSTS_OFF_ON,
9a2a3603	321	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa AP	322	};
	323
	324	/*
	325	* The following power domains are not under SW control
	326	*
	327	* always_on_iva
	328	* always_on_mpu
	329	* stdefuse
	330	*/
	331
6e01478a PW	332	/* As powerdomains are added or removed above, this list must also be changed */
	333	static struct powerdomain *powerdomains_omap44xx[] __initdata = {
	334	&core_44xx_pwrdm,
	335	&gfx_44xx_pwrdm,
	336	&abe_44xx_pwrdm,
	337	&dss_44xx_pwrdm,
	338	&tesla_44xx_pwrdm,
	339	&wkup_44xx_pwrdm,
	340	&cpu0_44xx_pwrdm,
	341	&cpu1_44xx_pwrdm,
	342	&emu_44xx_pwrdm,
	343	&mpu_44xx_pwrdm,
	344	&ivahd_44xx_pwrdm,
	345	&cam_44xx_pwrdm,
	346	&l3init_44xx_pwrdm,
	347	&l4per_44xx_pwrdm,
	348	&always_on_core_44xx_pwrdm,
	349	&cefuse_44xx_pwrdm,
	350	NULL
	351	};
f37c6dfa	352
6e01478a PW	353	void __init omap44xx_powerdomains_init(void)
6e01478a PW	354	{
129c65ee PW	355	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
	356	pwrdm_register_pwrdms(powerdomains_omap44xx);
	357	pwrdm_complete_init();
6e01478a	358	}