[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / powerdomains3xxx_data.c

/*
 * OMAP3 powerdomain definitions
 *
 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bug.h>

#include "soc.h"
#include "powerdomain.h"
#include "powerdomains2xxx_3xxx_data.h"
#include "prcm-common.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"

/*
 * 34XX-specific powerdomains, dependencies
 */

/*
 * Powerdomains
 */

static struct powerdomain iva2_pwrdm = {
	.name		  = "iva2_pwrdm",
	.prcm_offs	  = OMAP3430_IVA2_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 4,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
		[1] = PWRSTS_OFF_RET,
		[2] = PWRSTS_OFF_RET,
		[3] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,
		[1] = PWRSTS_ON,
		[2] = PWRSTS_OFF_ON,
		[3] = PWRSTS_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain mpu_3xxx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain mpu_am35x_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

/*
 * The USBTLL Save-and-Restore mechanism is broken on
 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
 * needs to be disabled on these chips.
 * Refer: 3430 errata ID i459 and 3630 errata ID i579
 *
 * Note: setting the SAR flag could help for errata ID i478
 *  which applies to 3430 <= ES3.1, but since the SAR feature
 *  is broken, do not use it.
 */
static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain core_3xxx_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	/*
	 * Setting the SAR flag for errata ID i478 which applies
	 *  to 3430 <= ES3.1
	 */
	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain core_am35x_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON,	 /* MEM1RETSTATE */
		[1] = PWRSTS_ON,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dss_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dss_am35x_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

/*
 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 * possible SGX powerstate, the SGX device itself does not support
 * retention.
 */
static struct powerdomain sgx_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	/* XXX This is accurate for 3430 SGX, but what about GFX? */
	.pwrsts		  = PWRSTS_OFF_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain sgx_am35x_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain cam_pwrdm = {
	.name		  = "cam_pwrdm",
	.prcm_offs	  = OMAP3430_CAM_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain per_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain per_am35x_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain emu_pwrdm = {
	.name		= "emu_pwrdm",
	.prcm_offs	= OMAP3430_EMU_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain neon_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain neon_am35x_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain usbhost_pwrdm = {
	.name		  = "usbhost_pwrdm",
	.prcm_offs	  = OMAP3430ES2_USBHOST_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	/*
	 * REVISIT: Enabling usb host save and restore mechanism seems to
	 * leave the usb host domain permanently in ACTIVE mode after
	 * changing the usb host power domain state from OFF to active once.
	 * Disabling for now.
	 */
	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll1_pwrdm = {
	.name		= "dpll1_pwrdm",
	.prcm_offs	= MPU_MOD,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain dpll2_pwrdm = {
	.name		= "dpll2_pwrdm",
	.prcm_offs	= OMAP3430_IVA2_MOD,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain dpll3_pwrdm = {
	.name		= "dpll3_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll4_pwrdm = {
	.name		= "dpll4_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll5_pwrdm = {
	.name		= "dpll5_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
	&wkup_omap2_pwrdm,
	&iva2_pwrdm,
	&mpu_3xxx_pwrdm,
	&neon_pwrdm,
	&cam_pwrdm,
	&dss_pwrdm,
	&per_pwrdm,
	&emu_pwrdm,
	&dpll1_pwrdm,
	&dpll2_pwrdm,
	&dpll3_pwrdm,
	&dpll4_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
	&gfx_omap2_pwrdm,
	&core_3xxx_pre_es3_1_pwrdm,
	NULL
};

/* also includes 3630ES1.0 */
static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
	&core_3xxx_pre_es3_1_pwrdm,
	&sgx_pwrdm,
	&usbhost_pwrdm,
	&dpll5_pwrdm,
	NULL
};

/* also includes 3630ES1.1+ */
static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
	&core_3xxx_es3_1_pwrdm,
	&sgx_pwrdm,
	&usbhost_pwrdm,
	&dpll5_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_am35x[] __initdata = {
	&wkup_omap2_pwrdm,
	&mpu_am35x_pwrdm,
	&neon_am35x_pwrdm,
	&core_am35x_pwrdm,
	&sgx_am35x_pwrdm,
	&dss_am35x_pwrdm,
	&per_am35x_pwrdm,
	&emu_pwrdm,
	&dpll1_pwrdm,
	&dpll3_pwrdm,
	&dpll4_pwrdm,
	&dpll5_pwrdm,
	NULL
};

void __init omap3xxx_powerdomains_init(void)
{
	unsigned int rev;

	if (!cpu_is_omap34xx())
		return;

	pwrdm_register_platform_funcs(&omap3_pwrdm_operations);

	rev = omap_rev();

	if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
		pwrdm_register_pwrdms(powerdomains_am35x);
	} else {
		pwrdm_register_pwrdms(powerdomains_omap3430_common);

		switch (rev) {
		case OMAP3430_REV_ES1_0:
			pwrdm_register_pwrdms(powerdomains_omap3430es1);
			break;
		case OMAP3430_REV_ES2_0:
		case OMAP3430_REV_ES2_1:
		case OMAP3430_REV_ES3_0:
		case OMAP3630_REV_ES1_0:
			pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
			break;
		case OMAP3430_REV_ES3_1:
		case OMAP3430_REV_ES3_1_2:
		case OMAP3630_REV_ES1_1:
		case OMAP3630_REV_ES1_2:
			pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
			break;
		default:
			WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
		}
	}

	pwrdm_complete_init();
}
Commit	Line	Data
ecb24aa1	1	/*
98fa3d8a	2	* OMAP3 powerdomain definitions
ecb24aa1	3	*
8179488a	4	* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
4cb49fec	5	* Copyright (C) 2007-2011 Nokia Corporation
ecb24aa1	6	*
6e01478a	7	* Paul Walmsley, Jouni Högander
ecb24aa1 PW	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
6e01478a PW	14	#include <linux/kernel.h>
6e01478a PW	15	#include <linux/init.h>
d9a5f4dd	16	#include <linux/bug.h>
ecb24aa1	17
dbc04161	18	#include "soc.h"
72e06d08	19	#include "powerdomain.h"
6e01478a	20	#include "powerdomains2xxx_3xxx_data.h"
ecb24aa1	21	#include "prcm-common.h"
59fb659b	22	#include "prm2xxx_3xxx.h"
ecb24aa1	23	#include "prm-regbits-34xx.h"
59fb659b	24	#include "cm2xxx_3xxx.h"
ecb24aa1 PW	25	#include "cm-regbits-34xx.h"
	26
	27	/*
	28	* 34XX-specific powerdomains, dependencies
	29	*/
	30
ecb24aa1 PW	31	/*
	32	* Powerdomains
	33	*/
	34
	35	static struct powerdomain iva2_pwrdm = {
	36	.name = "iva2_pwrdm",
	37	.prcm_offs = OMAP3430_IVA2_MOD,
ecb24aa1 PW	38	.pwrsts = PWRSTS_OFF_RET_ON,
	39	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	40	.banks = 4,
	41	.pwrsts_mem_ret = {
	42	[0] = PWRSTS_OFF_RET,
	43	[1] = PWRSTS_OFF_RET,
	44	[2] = PWRSTS_OFF_RET,
	45	[3] = PWRSTS_OFF_RET,
	46	},
	47	.pwrsts_mem_on = {
4cb49fec PW	48	[0] = PWRSTS_ON,
4cb49fec PW	49	[1] = PWRSTS_ON,
ecb24aa1	50	[2] = PWRSTS_OFF_ON,
4cb49fec	51	[3] = PWRSTS_ON,
ecb24aa1	52	},
562e54d1	53	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	54	};
ecb24aa1 PW	55
98fa3d8a	56	static struct powerdomain mpu_3xxx_pwrdm = {
ecb24aa1 PW	57	.name = "mpu_pwrdm",
ecb24aa1 PW	58	.prcm_offs = MPU_MOD,
ecb24aa1 PW	59	.pwrsts = PWRSTS_OFF_RET_ON,
ecb24aa1 PW	60	.pwrsts_logic_ret = PWRSTS_OFF_RET,
3863c74b	61	.flags = PWRDM_HAS_MPU_QUIRK,
ecb24aa1 PW	62	.banks = 1,
	63	.pwrsts_mem_ret = {
	64	[0] = PWRSTS_OFF_RET,
	65	},
	66	.pwrsts_mem_on = {
	67	[0] = PWRSTS_OFF_ON,
	68	},
562e54d1	69	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	70	};
ecb24aa1 PW	71
ff7ad7e4 MG	72	static struct powerdomain mpu_am35x_pwrdm = {
	73	.name = "mpu_pwrdm",
	74	.prcm_offs = MPU_MOD,
	75	.pwrsts = PWRSTS_ON,
	76	.pwrsts_logic_ret = PWRSTS_ON,
	77	.flags = PWRDM_HAS_MPU_QUIRK,
	78	.banks = 1,
	79	.pwrsts_mem_ret = {
	80	[0] = PWRSTS_ON,
	81	},
	82	.pwrsts_mem_on = {
	83	[0] = PWRSTS_ON,
	84	},
562e54d1	85	.voltdm = { .name = "mpu_iva" },
ff7ad7e4 MG	86	};
ff7ad7e4 MG	87
58dcfb3a AG	88	/*
58dcfb3a AG	89	* The USBTLL Save-and-Restore mechanism is broken on
25985edc	90	* 3430s up to ES3.0 and 3630ES1.0. Hence this feature
58dcfb3a AG	91	* needs to be disabled on these chips.
58dcfb3a AG	92	* Refer: 3430 errata ID i459 and 3630 errata ID i579
447b8da5 JP	93	*
	94	* Note: setting the SAR flag could help for errata ID i478
	95	* which applies to 3430 <= ES3.1, but since the SAR feature
	96	* is broken, do not use it.
58dcfb3a	97	*/
98fa3d8a	98	static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
ecb24aa1 PW	99	.name = "core_pwrdm",
ecb24aa1 PW	100	.prcm_offs = CORE_MOD,
7eb1afc9	101	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	102	.pwrsts_logic_ret = PWRSTS_OFF_RET,
7eb1afc9 PW	103	.banks = 2,
	104	.pwrsts_mem_ret = {
	105	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	106	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	107	},
	108	.pwrsts_mem_on = {
	109	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	110	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	111	},
562e54d1	112	.voltdm = { .name = "core" },
7eb1afc9 PW	113	};
7eb1afc9 PW	114
98fa3d8a	115	static struct powerdomain core_3xxx_es3_1_pwrdm = {
7eb1afc9 PW	116	.name = "core_pwrdm",
7eb1afc9 PW	117	.prcm_offs = CORE_MOD,
ecb24aa1	118	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	119	.pwrsts_logic_ret = PWRSTS_OFF_RET,
447b8da5 JP	120	/*
	121	* Setting the SAR flag for errata ID i478 which applies
	122	* to 3430 <= ES3.1
	123	*/
7eb1afc9	124	.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
ecb24aa1 PW	125	.banks = 2,
	126	.pwrsts_mem_ret = {
	127	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	128	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	129	},
	130	.pwrsts_mem_on = {
	131	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	132	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	133	},
562e54d1	134	.voltdm = { .name = "core" },
ecb24aa1 PW	135	};
ecb24aa1 PW	136
ff7ad7e4 MG	137	static struct powerdomain core_am35x_pwrdm = {
	138	.name = "core_pwrdm",
	139	.prcm_offs = CORE_MOD,
	140	.pwrsts = PWRSTS_ON,
	141	.pwrsts_logic_ret = PWRSTS_ON,
	142	.banks = 2,
	143	.pwrsts_mem_ret = {
	144	[0] = PWRSTS_ON, /* MEM1RETSTATE */
	145	[1] = PWRSTS_ON, /* MEM2RETSTATE */
	146	},
	147	.pwrsts_mem_on = {
	148	[0] = PWRSTS_ON, /* MEM1ONSTATE */
	149	[1] = PWRSTS_ON, /* MEM2ONSTATE */
	150	},
562e54d1	151	.voltdm = { .name = "core" },
ff7ad7e4 MG	152	};
ff7ad7e4 MG	153
ecb24aa1 PW	154	static struct powerdomain dss_pwrdm = {
ecb24aa1 PW	155	.name = "dss_pwrdm",
ecb24aa1	156	.prcm_offs = OMAP3430_DSS_MOD,
ecb24aa1	157	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	158	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	159	.banks = 1,
ecb24aa1 PW	160	.pwrsts_mem_ret = {
4cb49fec	161	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	162	},
ecb24aa1 PW	163	.pwrsts_mem_on = {
4cb49fec	164	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	165	},
562e54d1	166	.voltdm = { .name = "core" },
ecb24aa1 PW	167	};
ecb24aa1 PW	168
ff7ad7e4 MG	169	static struct powerdomain dss_am35x_pwrdm = {
	170	.name = "dss_pwrdm",
	171	.prcm_offs = OMAP3430_DSS_MOD,
	172	.pwrsts = PWRSTS_ON,
	173	.pwrsts_logic_ret = PWRSTS_ON,
	174	.banks = 1,
	175	.pwrsts_mem_ret = {
	176	[0] = PWRSTS_ON, /* MEMRETSTATE */
	177	},
	178	.pwrsts_mem_on = {
	179	[0] = PWRSTS_ON, /* MEMONSTATE */
	180	},
562e54d1	181	.voltdm = { .name = "core" },
ff7ad7e4 MG	182	};
ff7ad7e4 MG	183
be48ea74 PW	184	/*
	185	* Although the 34XX TRM Rev K Table 4-371 notes that retention is a
	186	* possible SGX powerstate, the SGX device itself does not support
	187	* retention.
	188	*/
ecb24aa1 PW	189	static struct powerdomain sgx_pwrdm = {
	190	.name = "sgx_pwrdm",
	191	.prcm_offs = OMAP3430ES2_SGX_MOD,
ecb24aa1	192	/* XXX This is accurate for 3430 SGX, but what about GFX? */
be48ea74	193	.pwrsts = PWRSTS_OFF_ON,
4cb49fec	194	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	195	.banks = 1,
ecb24aa1 PW	196	.pwrsts_mem_ret = {
4cb49fec	197	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	198	},
ecb24aa1 PW	199	.pwrsts_mem_on = {
4cb49fec	200	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	201	},
562e54d1	202	.voltdm = { .name = "core" },
ecb24aa1 PW	203	};
ecb24aa1 PW	204
ff7ad7e4 MG	205	static struct powerdomain sgx_am35x_pwrdm = {
	206	.name = "sgx_pwrdm",
	207	.prcm_offs = OMAP3430ES2_SGX_MOD,
	208	.pwrsts = PWRSTS_ON,
	209	.pwrsts_logic_ret = PWRSTS_ON,
	210	.banks = 1,
	211	.pwrsts_mem_ret = {
	212	[0] = PWRSTS_ON, /* MEMRETSTATE */
	213	},
	214	.pwrsts_mem_on = {
	215	[0] = PWRSTS_ON, /* MEMONSTATE */
	216	},
562e54d1	217	.voltdm = { .name = "core" },
ff7ad7e4 MG	218	};
ff7ad7e4 MG	219
ecb24aa1 PW	220	static struct powerdomain cam_pwrdm = {
ecb24aa1 PW	221	.name = "cam_pwrdm",
ecb24aa1	222	.prcm_offs = OMAP3430_CAM_MOD,
ecb24aa1	223	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	224	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	225	.banks = 1,
ecb24aa1 PW	226	.pwrsts_mem_ret = {
4cb49fec	227	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	228	},
ecb24aa1 PW	229	.pwrsts_mem_on = {
4cb49fec	230	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	231	},
562e54d1	232	.voltdm = { .name = "core" },
ecb24aa1 PW	233	};
	234
	235	static struct powerdomain per_pwrdm = {
	236	.name = "per_pwrdm",
	237	.prcm_offs = OMAP3430_PER_MOD,
ecb24aa1 PW	238	.pwrsts = PWRSTS_OFF_RET_ON,
	239	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	240	.banks = 1,
	241	.pwrsts_mem_ret = {
4cb49fec	242	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	243	},
ecb24aa1 PW	244	.pwrsts_mem_on = {
4cb49fec	245	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	246	},
562e54d1	247	.voltdm = { .name = "core" },
ecb24aa1 PW	248	};
ecb24aa1 PW	249
ff7ad7e4 MG	250	static struct powerdomain per_am35x_pwrdm = {
	251	.name = "per_pwrdm",
	252	.prcm_offs = OMAP3430_PER_MOD,
	253	.pwrsts = PWRSTS_ON,
	254	.pwrsts_logic_ret = PWRSTS_ON,
	255	.banks = 1,
	256	.pwrsts_mem_ret = {
	257	[0] = PWRSTS_ON, /* MEMRETSTATE */
	258	},
	259	.pwrsts_mem_on = {
	260	[0] = PWRSTS_ON, /* MEMONSTATE */
	261	},
562e54d1	262	.voltdm = { .name = "core" },
ff7ad7e4 MG	263	};
ff7ad7e4 MG	264
ecb24aa1 PW	265	static struct powerdomain emu_pwrdm = {
	266	.name = "emu_pwrdm",
	267	.prcm_offs = OMAP3430_EMU_MOD,
562e54d1	268	.voltdm = { .name = "core" },
ecb24aa1 PW	269	};
	270
	271	static struct powerdomain neon_pwrdm = {
	272	.name = "neon_pwrdm",
	273	.prcm_offs = OMAP3430_NEON_MOD,
ecb24aa1	274	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	275	.pwrsts_logic_ret = PWRSTS_RET,
562e54d1	276	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	277	};
ecb24aa1 PW	278
ff7ad7e4 MG	279	static struct powerdomain neon_am35x_pwrdm = {
	280	.name = "neon_pwrdm",
	281	.prcm_offs = OMAP3430_NEON_MOD,
	282	.pwrsts = PWRSTS_ON,
	283	.pwrsts_logic_ret = PWRSTS_ON,
562e54d1	284	.voltdm = { .name = "mpu_iva" },
ff7ad7e4 MG	285	};
ff7ad7e4 MG	286
ecb24aa1 PW	287	static struct powerdomain usbhost_pwrdm = {
	288	.name = "usbhost_pwrdm",
	289	.prcm_offs = OMAP3430ES2_USBHOST_MOD,
ecb24aa1	290	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	291	.pwrsts_logic_ret = PWRSTS_RET,
867d320b KJ	292	/*
	293	* REVISIT: Enabling usb host save and restore mechanism seems to
	294	* leave the usb host domain permanently in ACTIVE mode after
	295	* changing the usb host power domain state from OFF to active once.
	296	* Disabling for now.
	297	*/
	298	/.flags = PWRDM_HAS_HDWR_SAR,/ /* for USBHOST ctrlr only */
ecb24aa1 PW	299	.banks = 1,
ecb24aa1 PW	300	.pwrsts_mem_ret = {
4cb49fec	301	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	302	},
ecb24aa1 PW	303	.pwrsts_mem_on = {
4cb49fec	304	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	305	},
562e54d1	306	.voltdm = { .name = "core" },
ecb24aa1 PW	307	};
ecb24aa1 PW	308
46e0ccf8 PW	309	static struct powerdomain dpll1_pwrdm = {
	310	.name = "dpll1_pwrdm",
	311	.prcm_offs = MPU_MOD,
562e54d1	312	.voltdm = { .name = "mpu_iva" },
46e0ccf8 PW	313	};
	314
	315	static struct powerdomain dpll2_pwrdm = {
	316	.name = "dpll2_pwrdm",
	317	.prcm_offs = OMAP3430_IVA2_MOD,
562e54d1	318	.voltdm = { .name = "mpu_iva" },
46e0ccf8 PW	319	};
	320
	321	static struct powerdomain dpll3_pwrdm = {
	322	.name = "dpll3_pwrdm",
	323	.prcm_offs = PLL_MOD,
562e54d1	324	.voltdm = { .name = "core" },
46e0ccf8 PW	325	};
	326
	327	static struct powerdomain dpll4_pwrdm = {
	328	.name = "dpll4_pwrdm",
	329	.prcm_offs = PLL_MOD,
562e54d1	330	.voltdm = { .name = "core" },
46e0ccf8 PW	331	};
	332
	333	static struct powerdomain dpll5_pwrdm = {
	334	.name = "dpll5_pwrdm",
	335	.prcm_offs = PLL_MOD,
562e54d1	336	.voltdm = { .name = "core" },
46e0ccf8 PW	337	};
46e0ccf8 PW	338
6e01478a	339	/* As powerdomains are added or removed above, this list must also be changed */
8179488a	340	static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
6e01478a	341	&wkup_omap2_pwrdm,
6e01478a PW	342	&iva2_pwrdm,
	343	&mpu_3xxx_pwrdm,
	344	&neon_pwrdm,
6e01478a PW	345	&cam_pwrdm,
	346	&dss_pwrdm,
	347	&per_pwrdm,
	348	&emu_pwrdm,
6e01478a PW	349	&dpll1_pwrdm,
	350	&dpll2_pwrdm,
	351	&dpll3_pwrdm,
	352	&dpll4_pwrdm,
8179488a PW	353	NULL
	354	};
	355
	356	static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
	357	&gfx_omap2_pwrdm,
	358	&core_3xxx_pre_es3_1_pwrdm,
	359	NULL
	360	};
	361
	362	/* also includes 3630ES1.0 */
	363	static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
	364	&core_3xxx_pre_es3_1_pwrdm,
	365	&sgx_pwrdm,
	366	&usbhost_pwrdm,
6e01478a	367	&dpll5_pwrdm,
6e01478a PW	368	NULL
6e01478a PW	369	};
ecb24aa1	370
8179488a PW	371	/* also includes 3630ES1.1+ */
	372	static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
	373	&core_3xxx_es3_1_pwrdm,
	374	&sgx_pwrdm,
	375	&usbhost_pwrdm,
	376	&dpll5_pwrdm,
	377	NULL
	378	};
ecb24aa1	379
ff7ad7e4 MG	380	static struct powerdomain *powerdomains_am35x[] __initdata = {
	381	&wkup_omap2_pwrdm,
	382	&mpu_am35x_pwrdm,
	383	&neon_am35x_pwrdm,
	384	&core_am35x_pwrdm,
	385	&sgx_am35x_pwrdm,
	386	&dss_am35x_pwrdm,
	387	&per_am35x_pwrdm,
	388	&emu_pwrdm,
	389	&dpll1_pwrdm,
	390	&dpll3_pwrdm,
	391	&dpll4_pwrdm,
	392	&dpll5_pwrdm,
	393	NULL
	394	};
	395
6e01478a PW	396	void __init omap3xxx_powerdomains_init(void)
6e01478a PW	397	{
8179488a PW	398	unsigned int rev;
	399
	400	if (!cpu_is_omap34xx())
	401	return;
	402
129c65ee	403	pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
8179488a PW	404
	405	rev = omap_rev();
	406
ff7ad7e4 MG	407	if (rev == AM35XX_REV_ES1_0 \|\| rev == AM35XX_REV_ES1_1) {
	408	pwrdm_register_pwrdms(powerdomains_am35x);
	409	} else {
	410	pwrdm_register_pwrdms(powerdomains_omap3430_common);
	411
	412	switch (rev) {
	413	case OMAP3430_REV_ES1_0:
	414	pwrdm_register_pwrdms(powerdomains_omap3430es1);
	415	break;
	416	case OMAP3430_REV_ES2_0:
	417	case OMAP3430_REV_ES2_1:
	418	case OMAP3430_REV_ES3_0:
	419	case OMAP3630_REV_ES1_0:
	420	pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
	421	break;
	422	case OMAP3430_REV_ES3_1:
	423	case OMAP3430_REV_ES3_1_2:
	424	case OMAP3630_REV_ES1_1:
	425	case OMAP3630_REV_ES1_2:
	426	pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
	427	break;
	428	default:
	429	WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
	430	}
	431	}
8179488a	432
129c65ee	433	pwrdm_complete_init();
6e01478a	434	}