ARM: OMAP2+: Add mmc hwmod entries for dm814x
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / arch / arm / mach-omap2 / omap_hwmod_81xx_data.c
CommitLineData
4d38bd12
TL
1/*
2 * DM81xx hwmod data.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/platform_data/gpio-omap.h>
19#include <linux/platform_data/hsmmc-omap.h>
20#include <linux/platform_data/spi-omap2-mcspi.h>
21#include <plat/dmtimer.h>
22
23#include "omap_hwmod_common_data.h"
24#include "cm81xx.h"
25#include "ti81xx.h"
26#include "wd_timer.h"
27
28/*
29 * DM816X hardware modules integration data
30 *
31 * Note: This is incomplete and at present, not generated from h/w database.
32 */
33
34/*
7e1b11d1
TL
35 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
36 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
4d38bd12 37 */
7e1b11d1
TL
38#define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140
39#define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144
40#define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148
41#define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c
42#define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150
43#define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154
44#define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158
45#define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c
46#define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160
47#define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164
48#define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168
49#define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c
50#define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190
51#define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194
52#define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198
53#define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c
54#define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8
55#define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4
56#define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0
57#define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4
58#define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4
59#define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8
60#define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec
61#define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0
62#define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4
63#define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8
64#define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc
65#define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200
66#define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204
67
68/* Registers specific to dm814x */
69#define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c
70#define DM814X_CM_ALWON_ATL_CLKCTRL 0x170
71#define DM814X_CM_ALWON_MLB_CLKCTRL 0x174
72#define DM814X_CM_ALWON_PATA_CLKCTRL 0x178
73#define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180
74#define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184
75#define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188
76#define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4
77#define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8
78#define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc
79#define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0
80#define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218
81#define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c
82#define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220
83#define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224
84#define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228
85
86/* Registers specific to dm816x */
4d38bd12 87#define DM816X_DM_ALWON_BASE 0x1400
4d38bd12
TL
88#define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
89#define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
90#define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
91#define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
92#define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
93#define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
94#define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
4d38bd12
TL
95#define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE)
96#define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE)
97#define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE)
4d38bd12
TL
98#define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
99#define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE)
4d38bd12
TL
100#define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE)
101#define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE)
102
103/*
104 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
105 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
106 */
107#define DM816X_CM_DEFAULT_OFFSET 0x500
108#define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET)
109
110/* L3 Interconnect entries clocked at 125, 250 and 500MHz */
7e1b11d1 111static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
4d38bd12
TL
112 .name = "alwon_l3_slow",
113 .clkdm_name = "alwon_l3s_clkdm",
114 .class = &l3_hwmod_class,
115 .flags = HWMOD_NO_IDLEST,
116};
117
7e1b11d1 118static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
4d38bd12
TL
119 .name = "default_l3_slow",
120 .clkdm_name = "default_l3_slow_clkdm",
121 .class = &l3_hwmod_class,
122 .flags = HWMOD_NO_IDLEST,
123};
124
7e1b11d1 125static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
4d38bd12
TL
126 .name = "l3_med",
127 .clkdm_name = "alwon_l3_med_clkdm",
128 .class = &l3_hwmod_class,
129 .flags = HWMOD_NO_IDLEST,
130};
131
7e1b11d1 132static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
4d38bd12
TL
133 .name = "l3_fast",
134 .clkdm_name = "alwon_l3_fast_clkdm",
135 .class = &l3_hwmod_class,
136 .flags = HWMOD_NO_IDLEST,
137};
138
139/*
140 * L4 standard peripherals, see TRM table 1-12 for devices using this.
141 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
142 */
7e1b11d1 143static struct omap_hwmod dm81xx_l4_ls_hwmod = {
4d38bd12
TL
144 .name = "l4_ls",
145 .clkdm_name = "alwon_l3s_clkdm",
146 .class = &l4_hwmod_class,
147};
148
149/*
150 * L4 high-speed peripherals. For devices using this, please see the TRM
151 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
152 * table 1-73 for devices using 250MHz SYSCLK5 clock.
153 */
7e1b11d1 154static struct omap_hwmod dm81xx_l4_hs_hwmod = {
4d38bd12
TL
155 .name = "l4_hs",
156 .clkdm_name = "alwon_l3_med_clkdm",
157 .class = &l4_hwmod_class,
158};
159
160/* L3 slow -> L4 ls peripheral interface running at 125MHz */
7e1b11d1
TL
161static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
162 .master = &dm81xx_alwon_l3_slow_hwmod,
163 .slave = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
164 .user = OCP_USER_MPU,
165};
166
167/* L3 med -> L4 fast peripheral interface running at 250MHz */
7e1b11d1
TL
168static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
169 .master = &dm81xx_alwon_l3_med_hwmod,
170 .slave = &dm81xx_l4_hs_hwmod,
4d38bd12
TL
171 .user = OCP_USER_MPU,
172};
173
174/* MPU */
0f3ccb24
TL
175static struct omap_hwmod dm814x_mpu_hwmod = {
176 .name = "mpu",
177 .clkdm_name = "alwon_l3s_clkdm",
178 .class = &mpu_hwmod_class,
179 .flags = HWMOD_INIT_NO_IDLE,
180 .main_clk = "mpu_ck",
181 .prcm = {
182 .omap4 = {
183 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
184 .modulemode = MODULEMODE_SWCTRL,
185 },
186 },
187};
188
189static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
190 .master = &dm814x_mpu_hwmod,
191 .slave = &dm81xx_alwon_l3_slow_hwmod,
192 .user = OCP_USER_MPU,
193};
194
195/* L3 med peripheral interface running at 200MHz */
196static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
197 .master = &dm814x_mpu_hwmod,
198 .slave = &dm81xx_alwon_l3_med_hwmod,
199 .user = OCP_USER_MPU,
200};
201
4d38bd12
TL
202static struct omap_hwmod dm816x_mpu_hwmod = {
203 .name = "mpu",
204 .clkdm_name = "alwon_mpu_clkdm",
205 .class = &mpu_hwmod_class,
206 .flags = HWMOD_INIT_NO_IDLE,
207 .main_clk = "mpu_ck",
208 .prcm = {
209 .omap4 = {
210 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
211 .modulemode = MODULEMODE_SWCTRL,
212 },
213 },
214};
215
216static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
217 .master = &dm816x_mpu_hwmod,
7e1b11d1 218 .slave = &dm81xx_alwon_l3_slow_hwmod,
4d38bd12
TL
219 .user = OCP_USER_MPU,
220};
221
222/* L3 med peripheral interface running at 250MHz */
223static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
224 .master = &dm816x_mpu_hwmod,
7e1b11d1 225 .slave = &dm81xx_alwon_l3_med_hwmod,
4d38bd12
TL
226 .user = OCP_USER_MPU,
227};
228
229/* UART common */
230static struct omap_hwmod_class_sysconfig uart_sysc = {
231 .rev_offs = 0x50,
232 .sysc_offs = 0x54,
233 .syss_offs = 0x58,
234 .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
235 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
236 SYSS_HAS_RESET_STATUS,
237 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
238 MSTANDBY_SMART_WKUP,
239 .sysc_fields = &omap_hwmod_sysc_type1,
240};
241
242static struct omap_hwmod_class uart_class = {
243 .name = "uart",
244 .sysc = &uart_sysc,
245};
246
7e1b11d1 247static struct omap_hwmod dm81xx_uart1_hwmod = {
4d38bd12
TL
248 .name = "uart1",
249 .clkdm_name = "alwon_l3s_clkdm",
250 .main_clk = "sysclk10_ck",
251 .prcm = {
252 .omap4 = {
7e1b11d1 253 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
4d38bd12
TL
254 .modulemode = MODULEMODE_SWCTRL,
255 },
256 },
257 .class = &uart_class,
258 .flags = DEBUG_TI81XXUART1_FLAGS,
259};
260
7e1b11d1
TL
261static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
262 .master = &dm81xx_l4_ls_hwmod,
263 .slave = &dm81xx_uart1_hwmod,
4d38bd12
TL
264 .clk = "sysclk6_ck",
265 .user = OCP_USER_MPU,
266};
267
7e1b11d1 268static struct omap_hwmod dm81xx_uart2_hwmod = {
4d38bd12
TL
269 .name = "uart2",
270 .clkdm_name = "alwon_l3s_clkdm",
271 .main_clk = "sysclk10_ck",
272 .prcm = {
273 .omap4 = {
7e1b11d1 274 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
4d38bd12
TL
275 .modulemode = MODULEMODE_SWCTRL,
276 },
277 },
278 .class = &uart_class,
279 .flags = DEBUG_TI81XXUART2_FLAGS,
280};
281
7e1b11d1
TL
282static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
283 .master = &dm81xx_l4_ls_hwmod,
284 .slave = &dm81xx_uart2_hwmod,
4d38bd12
TL
285 .clk = "sysclk6_ck",
286 .user = OCP_USER_MPU,
287};
288
7e1b11d1 289static struct omap_hwmod dm81xx_uart3_hwmod = {
4d38bd12
TL
290 .name = "uart3",
291 .clkdm_name = "alwon_l3s_clkdm",
292 .main_clk = "sysclk10_ck",
293 .prcm = {
294 .omap4 = {
7e1b11d1 295 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
4d38bd12
TL
296 .modulemode = MODULEMODE_SWCTRL,
297 },
298 },
299 .class = &uart_class,
300 .flags = DEBUG_TI81XXUART3_FLAGS,
301};
302
7e1b11d1
TL
303static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
304 .master = &dm81xx_l4_ls_hwmod,
305 .slave = &dm81xx_uart3_hwmod,
4d38bd12
TL
306 .clk = "sysclk6_ck",
307 .user = OCP_USER_MPU,
308};
309
310static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
311 .rev_offs = 0x0,
312 .sysc_offs = 0x10,
313 .syss_offs = 0x14,
314 .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
315 SYSS_HAS_RESET_STATUS,
316 .sysc_fields = &omap_hwmod_sysc_type1,
317};
318
319static struct omap_hwmod_class wd_timer_class = {
320 .name = "wd_timer",
321 .sysc = &wd_timer_sysc,
322 .pre_shutdown = &omap2_wd_timer_disable,
323 .reset = &omap2_wd_timer_reset,
324};
325
7e1b11d1 326static struct omap_hwmod dm81xx_wd_timer_hwmod = {
4d38bd12
TL
327 .name = "wd_timer",
328 .clkdm_name = "alwon_l3s_clkdm",
329 .main_clk = "sysclk18_ck",
330 .flags = HWMOD_NO_IDLEST,
331 .prcm = {
332 .omap4 = {
7e1b11d1 333 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
4d38bd12
TL
334 .modulemode = MODULEMODE_SWCTRL,
335 },
336 },
337 .class = &wd_timer_class,
338};
339
7e1b11d1
TL
340static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
341 .master = &dm81xx_l4_ls_hwmod,
342 .slave = &dm81xx_wd_timer_hwmod,
4d38bd12
TL
343 .clk = "sysclk6_ck",
344 .user = OCP_USER_MPU,
345};
346
347/* I2C common */
348static struct omap_hwmod_class_sysconfig i2c_sysc = {
349 .rev_offs = 0x0,
350 .sysc_offs = 0x10,
351 .syss_offs = 0x90,
352 .sysc_flags = SYSC_HAS_SIDLEMODE |
353 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
354 SYSC_HAS_AUTOIDLE,
355 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
356 .sysc_fields = &omap_hwmod_sysc_type1,
357};
358
359static struct omap_hwmod_class i2c_class = {
360 .name = "i2c",
361 .sysc = &i2c_sysc,
362};
363
364static struct omap_hwmod dm81xx_i2c1_hwmod = {
365 .name = "i2c1",
366 .clkdm_name = "alwon_l3s_clkdm",
367 .main_clk = "sysclk10_ck",
368 .prcm = {
369 .omap4 = {
7e1b11d1 370 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
4d38bd12
TL
371 .modulemode = MODULEMODE_SWCTRL,
372 },
373 },
374 .class = &i2c_class,
375};
376
7e1b11d1
TL
377static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
378 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
379 .slave = &dm81xx_i2c1_hwmod,
380 .clk = "sysclk6_ck",
381 .user = OCP_USER_MPU,
382};
383
7e1b11d1 384static struct omap_hwmod dm81xx_i2c2_hwmod = {
4d38bd12
TL
385 .name = "i2c2",
386 .clkdm_name = "alwon_l3s_clkdm",
387 .main_clk = "sysclk10_ck",
388 .prcm = {
389 .omap4 = {
7e1b11d1 390 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
4d38bd12
TL
391 .modulemode = MODULEMODE_SWCTRL,
392 },
393 },
394 .class = &i2c_class,
395};
396
397static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
398 .rev_offs = 0x0000,
399 .sysc_offs = 0x0010,
400 .syss_offs = 0x0014,
401 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
402 SYSC_HAS_SOFTRESET |
403 SYSS_HAS_RESET_STATUS,
404 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
405 .sysc_fields = &omap_hwmod_sysc_type1,
406};
407
7e1b11d1
TL
408static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
409 .master = &dm81xx_l4_ls_hwmod,
410 .slave = &dm81xx_i2c2_hwmod,
4d38bd12
TL
411 .clk = "sysclk6_ck",
412 .user = OCP_USER_MPU,
413};
414
415static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
416 .name = "elm",
417 .sysc = &dm81xx_elm_sysc,
418};
419
420static struct omap_hwmod dm81xx_elm_hwmod = {
421 .name = "elm",
422 .clkdm_name = "alwon_l3s_clkdm",
423 .class = &dm81xx_elm_hwmod_class,
424 .main_clk = "sysclk6_ck",
425};
426
427static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
7e1b11d1 428 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
429 .slave = &dm81xx_elm_hwmod,
430 .user = OCP_USER_MPU,
431};
432
433static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
434 .rev_offs = 0x0000,
435 .sysc_offs = 0x0010,
436 .syss_offs = 0x0114,
437 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
438 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
439 SYSS_HAS_RESET_STATUS,
440 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
441 SIDLE_SMART_WKUP,
442 .sysc_fields = &omap_hwmod_sysc_type1,
443};
444
445static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
446 .name = "gpio",
447 .sysc = &dm81xx_gpio_sysc,
448 .rev = 2,
449};
450
451static struct omap_gpio_dev_attr gpio_dev_attr = {
452 .bank_width = 32,
453 .dbck_flag = true,
454};
455
456static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
457 { .role = "dbclk", .clk = "sysclk18_ck" },
458};
459
460static struct omap_hwmod dm81xx_gpio1_hwmod = {
461 .name = "gpio1",
462 .clkdm_name = "alwon_l3s_clkdm",
463 .class = &dm81xx_gpio_hwmod_class,
464 .main_clk = "sysclk6_ck",
465 .prcm = {
466 .omap4 = {
7e1b11d1 467 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
4d38bd12
TL
468 .modulemode = MODULEMODE_SWCTRL,
469 },
470 },
471 .opt_clks = gpio1_opt_clks,
472 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
473 .dev_attr = &gpio_dev_attr,
474};
475
476static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
7e1b11d1 477 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
478 .slave = &dm81xx_gpio1_hwmod,
479 .user = OCP_USER_MPU,
480};
481
482static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
483 { .role = "dbclk", .clk = "sysclk18_ck" },
484};
485
486static struct omap_hwmod dm81xx_gpio2_hwmod = {
487 .name = "gpio2",
488 .clkdm_name = "alwon_l3s_clkdm",
489 .class = &dm81xx_gpio_hwmod_class,
490 .main_clk = "sysclk6_ck",
491 .prcm = {
492 .omap4 = {
7e1b11d1 493 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
4d38bd12
TL
494 .modulemode = MODULEMODE_SWCTRL,
495 },
496 },
497 .opt_clks = gpio2_opt_clks,
498 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
499 .dev_attr = &gpio_dev_attr,
500};
501
502static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
7e1b11d1 503 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
504 .slave = &dm81xx_gpio2_hwmod,
505 .user = OCP_USER_MPU,
506};
507
508static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
509 .rev_offs = 0x0,
510 .sysc_offs = 0x10,
511 .syss_offs = 0x14,
512 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
513 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
514 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
515 .sysc_fields = &omap_hwmod_sysc_type1,
516};
517
518static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
519 .name = "gpmc",
520 .sysc = &dm81xx_gpmc_sysc,
521};
522
523static struct omap_hwmod dm81xx_gpmc_hwmod = {
524 .name = "gpmc",
525 .clkdm_name = "alwon_l3s_clkdm",
526 .class = &dm81xx_gpmc_hwmod_class,
527 .main_clk = "sysclk6_ck",
63aa945b
TL
528 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
529 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
4d38bd12
TL
530 .prcm = {
531 .omap4 = {
7e1b11d1 532 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
4d38bd12
TL
533 .modulemode = MODULEMODE_SWCTRL,
534 },
535 },
536};
537
f734a9b3 538static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
7e1b11d1 539 .master = &dm81xx_alwon_l3_slow_hwmod,
4d38bd12
TL
540 .slave = &dm81xx_gpmc_hwmod,
541 .user = OCP_USER_MPU,
542};
543
544static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
545 .rev_offs = 0x0,
546 .sysc_offs = 0x10,
547 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
548 SYSC_HAS_SOFTRESET,
549 .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
550 .sysc_fields = &omap_hwmod_sysc_type2,
551};
552
553static struct omap_hwmod_class dm81xx_usbotg_class = {
554 .name = "usbotg",
555 .sysc = &dm81xx_usbhsotg_sysc,
556};
557
558static struct omap_hwmod dm81xx_usbss_hwmod = {
559 .name = "usb_otg_hs",
560 .clkdm_name = "default_l3_slow_clkdm",
561 .main_clk = "sysclk6_ck",
562 .prcm = {
563 .omap4 = {
564 .clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL,
565 .modulemode = MODULEMODE_SWCTRL,
566 },
567 },
568 .class = &dm81xx_usbotg_class,
569};
570
571static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = {
7e1b11d1 572 .master = &dm81xx_default_l3_slow_hwmod,
4d38bd12
TL
573 .slave = &dm81xx_usbss_hwmod,
574 .clk = "sysclk6_ck",
575 .user = OCP_USER_MPU,
576};
577
578static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
579 .rev_offs = 0x0000,
580 .sysc_offs = 0x0010,
581 .syss_offs = 0x0014,
582 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
583 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
584 SIDLE_SMART_WKUP,
585 .sysc_fields = &omap_hwmod_sysc_type2,
586};
587
588static struct omap_hwmod_class dm816x_timer_hwmod_class = {
589 .name = "timer",
590 .sysc = &dm816x_timer_sysc,
591};
592
593static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
594 .timer_capability = OMAP_TIMER_ALWON,
595};
596
0f3ccb24
TL
597static struct omap_hwmod dm814x_timer1_hwmod = {
598 .name = "timer1",
599 .clkdm_name = "alwon_l3s_clkdm",
600 .main_clk = "timer_sys_ck",
601 .dev_attr = &capability_alwon_dev_attr,
602 .class = &dm816x_timer_hwmod_class,
603 .flags = HWMOD_NO_IDLEST,
604};
605
606static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
607 .master = &dm81xx_l4_ls_hwmod,
608 .slave = &dm814x_timer1_hwmod,
609 .clk = "timer_sys_ck",
610 .user = OCP_USER_MPU,
611};
612
4d38bd12
TL
613static struct omap_hwmod dm816x_timer1_hwmod = {
614 .name = "timer1",
615 .clkdm_name = "alwon_l3s_clkdm",
616 .main_clk = "timer1_fck",
617 .prcm = {
618 .omap4 = {
619 .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
620 .modulemode = MODULEMODE_SWCTRL,
621 },
622 },
623 .dev_attr = &capability_alwon_dev_attr,
624 .class = &dm816x_timer_hwmod_class,
625};
626
627static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
7e1b11d1 628 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
629 .slave = &dm816x_timer1_hwmod,
630 .clk = "sysclk6_ck",
631 .user = OCP_USER_MPU,
632};
633
0f3ccb24
TL
634static struct omap_hwmod dm814x_timer2_hwmod = {
635 .name = "timer2",
636 .clkdm_name = "alwon_l3s_clkdm",
637 .main_clk = "timer_sys_ck",
638 .dev_attr = &capability_alwon_dev_attr,
639 .class = &dm816x_timer_hwmod_class,
640 .flags = HWMOD_NO_IDLEST,
641};
642
643static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
644 .master = &dm81xx_l4_ls_hwmod,
645 .slave = &dm814x_timer2_hwmod,
646 .clk = "timer_sys_ck",
647 .user = OCP_USER_MPU,
648};
649
4d38bd12
TL
650static struct omap_hwmod dm816x_timer2_hwmod = {
651 .name = "timer2",
652 .clkdm_name = "alwon_l3s_clkdm",
653 .main_clk = "timer2_fck",
654 .prcm = {
655 .omap4 = {
656 .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
657 .modulemode = MODULEMODE_SWCTRL,
658 },
659 },
660 .dev_attr = &capability_alwon_dev_attr,
661 .class = &dm816x_timer_hwmod_class,
662};
663
664static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
7e1b11d1 665 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
666 .slave = &dm816x_timer2_hwmod,
667 .clk = "sysclk6_ck",
668 .user = OCP_USER_MPU,
669};
670
671static struct omap_hwmod dm816x_timer3_hwmod = {
672 .name = "timer3",
673 .clkdm_name = "alwon_l3s_clkdm",
674 .main_clk = "timer3_fck",
675 .prcm = {
676 .omap4 = {
677 .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
678 .modulemode = MODULEMODE_SWCTRL,
679 },
680 },
681 .dev_attr = &capability_alwon_dev_attr,
682 .class = &dm816x_timer_hwmod_class,
683};
684
685static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
7e1b11d1 686 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
687 .slave = &dm816x_timer3_hwmod,
688 .clk = "sysclk6_ck",
689 .user = OCP_USER_MPU,
690};
691
692static struct omap_hwmod dm816x_timer4_hwmod = {
693 .name = "timer4",
694 .clkdm_name = "alwon_l3s_clkdm",
695 .main_clk = "timer4_fck",
696 .prcm = {
697 .omap4 = {
698 .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
699 .modulemode = MODULEMODE_SWCTRL,
700 },
701 },
702 .dev_attr = &capability_alwon_dev_attr,
703 .class = &dm816x_timer_hwmod_class,
704};
705
706static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
7e1b11d1 707 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
708 .slave = &dm816x_timer4_hwmod,
709 .clk = "sysclk6_ck",
710 .user = OCP_USER_MPU,
711};
712
713static struct omap_hwmod dm816x_timer5_hwmod = {
714 .name = "timer5",
715 .clkdm_name = "alwon_l3s_clkdm",
716 .main_clk = "timer5_fck",
717 .prcm = {
718 .omap4 = {
719 .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
720 .modulemode = MODULEMODE_SWCTRL,
721 },
722 },
723 .dev_attr = &capability_alwon_dev_attr,
724 .class = &dm816x_timer_hwmod_class,
725};
726
727static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
7e1b11d1 728 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
729 .slave = &dm816x_timer5_hwmod,
730 .clk = "sysclk6_ck",
731 .user = OCP_USER_MPU,
732};
733
734static struct omap_hwmod dm816x_timer6_hwmod = {
735 .name = "timer6",
736 .clkdm_name = "alwon_l3s_clkdm",
737 .main_clk = "timer6_fck",
738 .prcm = {
739 .omap4 = {
740 .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
741 .modulemode = MODULEMODE_SWCTRL,
742 },
743 },
744 .dev_attr = &capability_alwon_dev_attr,
745 .class = &dm816x_timer_hwmod_class,
746};
747
748static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
7e1b11d1 749 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
750 .slave = &dm816x_timer6_hwmod,
751 .clk = "sysclk6_ck",
752 .user = OCP_USER_MPU,
753};
754
755static struct omap_hwmod dm816x_timer7_hwmod = {
756 .name = "timer7",
757 .clkdm_name = "alwon_l3s_clkdm",
758 .main_clk = "timer7_fck",
759 .prcm = {
760 .omap4 = {
761 .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
762 .modulemode = MODULEMODE_SWCTRL,
763 },
764 },
765 .dev_attr = &capability_alwon_dev_attr,
766 .class = &dm816x_timer_hwmod_class,
767};
768
769static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
7e1b11d1 770 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
771 .slave = &dm816x_timer7_hwmod,
772 .clk = "sysclk6_ck",
773 .user = OCP_USER_MPU,
774};
775
0f3ccb24
TL
776/* CPSW on dm814x */
777static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
778 .rev_offs = 0x0,
779 .sysc_offs = 0x8,
780 .syss_offs = 0x4,
781 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
782 SYSS_HAS_RESET_STATUS,
783 .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
784 MSTANDBY_NO,
785 .sysc_fields = &omap_hwmod_sysc_type3,
786};
787
788static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
789 .name = "cpgmac0",
790 .sysc = &dm814x_cpgmac_sysc,
791};
792
24da741c 793static struct omap_hwmod dm814x_cpgmac0_hwmod = {
0f3ccb24
TL
794 .name = "cpgmac0",
795 .class = &dm814x_cpgmac0_hwmod_class,
796 .clkdm_name = "alwon_ethernet_clkdm",
797 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
798 .main_clk = "cpsw_125mhz_gclk",
799 .prcm = {
800 .omap4 = {
801 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
802 .modulemode = MODULEMODE_SWCTRL,
803 },
804 },
805};
806
807static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
808 .name = "davinci_mdio",
809};
810
24da741c 811static struct omap_hwmod dm814x_mdio_hwmod = {
0f3ccb24
TL
812 .name = "davinci_mdio",
813 .class = &dm814x_mdio_hwmod_class,
814 .clkdm_name = "alwon_ethernet_clkdm",
815 .main_clk = "cpsw_125mhz_gclk",
816};
817
818static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
819 .master = &dm81xx_l4_hs_hwmod,
820 .slave = &dm814x_cpgmac0_hwmod,
821 .clk = "cpsw_125mhz_gclk",
822 .user = OCP_USER_MPU,
823};
824
24da741c 825static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
0f3ccb24
TL
826 .master = &dm814x_cpgmac0_hwmod,
827 .slave = &dm814x_mdio_hwmod,
828 .user = OCP_USER_MPU,
829 .flags = HWMOD_NO_IDLEST,
830};
831
4d38bd12
TL
832/* EMAC Ethernet */
833static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
834 .rev_offs = 0x0,
835 .sysc_offs = 0x4,
836 .sysc_flags = SYSC_HAS_SOFTRESET,
837 .sysc_fields = &omap_hwmod_sysc_type2,
838};
839
840static struct omap_hwmod_class dm816x_emac_hwmod_class = {
841 .name = "emac",
842 .sysc = &dm816x_emac_sysc,
843};
844
845/*
846 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
847 * driver probed before EMAC0, we let MDIO do the clock idling.
848 */
849static struct omap_hwmod dm816x_emac0_hwmod = {
850 .name = "emac0",
851 .clkdm_name = "alwon_ethernet_clkdm",
852 .class = &dm816x_emac_hwmod_class,
853};
854
7e1b11d1
TL
855static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
856 .master = &dm81xx_l4_hs_hwmod,
4d38bd12
TL
857 .slave = &dm816x_emac0_hwmod,
858 .clk = "sysclk5_ck",
859 .user = OCP_USER_MPU,
860};
861
7e1b11d1 862static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
4d38bd12
TL
863 .name = "davinci_mdio",
864 .sysc = &dm816x_emac_sysc,
865};
866
24da741c 867static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
4d38bd12 868 .name = "davinci_mdio",
7e1b11d1 869 .class = &dm81xx_mdio_hwmod_class,
4d38bd12
TL
870 .clkdm_name = "alwon_ethernet_clkdm",
871 .main_clk = "sysclk24_ck",
872 .flags = HWMOD_NO_IDLEST,
873 /*
874 * REVISIT: This should be moved to the emac0_hwmod
875 * once we have a better way to handle device slaves.
876 */
877 .prcm = {
878 .omap4 = {
7e1b11d1 879 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
4d38bd12
TL
880 .modulemode = MODULEMODE_SWCTRL,
881 },
882 },
883};
884
24da741c 885static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
7e1b11d1
TL
886 .master = &dm81xx_l4_hs_hwmod,
887 .slave = &dm81xx_emac0_mdio_hwmod,
4d38bd12
TL
888 .user = OCP_USER_MPU,
889};
890
891static struct omap_hwmod dm816x_emac1_hwmod = {
892 .name = "emac1",
893 .clkdm_name = "alwon_ethernet_clkdm",
894 .main_clk = "sysclk24_ck",
895 .flags = HWMOD_NO_IDLEST,
896 .prcm = {
897 .omap4 = {
898 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
899 .modulemode = MODULEMODE_SWCTRL,
900 },
901 },
902 .class = &dm816x_emac_hwmod_class,
903};
904
905static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
7e1b11d1 906 .master = &dm81xx_l4_hs_hwmod,
4d38bd12
TL
907 .slave = &dm816x_emac1_hwmod,
908 .clk = "sysclk5_ck",
909 .user = OCP_USER_MPU,
910};
911
c757fda8 912static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
4d38bd12
TL
913 .rev_offs = 0x0,
914 .sysc_offs = 0x110,
915 .syss_offs = 0x114,
916 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
917 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
918 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
919 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
920 .sysc_fields = &omap_hwmod_sysc_type1,
921};
922
c757fda8 923static struct omap_hwmod_class dm81xx_mmc_class = {
4d38bd12 924 .name = "mmc",
c757fda8 925 .sysc = &dm81xx_mmc_sysc,
4d38bd12
TL
926};
927
c757fda8 928static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
4d38bd12
TL
929 { .role = "dbck", .clk = "sysclk18_ck", },
930};
931
c757fda8
TL
932static struct omap_hsmmc_dev_attr mmc_dev_attr = {
933};
934
935static struct omap_hwmod dm814x_mmc1_hwmod = {
936 .name = "mmc1",
937 .clkdm_name = "alwon_l3s_clkdm",
938 .opt_clks = dm81xx_mmc_opt_clks,
939 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
940 .main_clk = "sysclk8_ck",
941 .prcm = {
942 .omap4 = {
943 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
944 .modulemode = MODULEMODE_SWCTRL,
945 },
946 },
947 .dev_attr = &mmc_dev_attr,
948 .class = &dm81xx_mmc_class,
949};
950
951static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
952 .master = &dm81xx_l4_ls_hwmod,
953 .slave = &dm814x_mmc1_hwmod,
954 .clk = "sysclk6_ck",
955 .user = OCP_USER_MPU,
956 .flags = OMAP_FIREWALL_L4
957};
958
959static struct omap_hwmod dm814x_mmc2_hwmod = {
960 .name = "mmc2",
961 .clkdm_name = "alwon_l3s_clkdm",
962 .opt_clks = dm81xx_mmc_opt_clks,
963 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
964 .main_clk = "sysclk8_ck",
965 .prcm = {
966 .omap4 = {
967 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
968 .modulemode = MODULEMODE_SWCTRL,
969 },
970 },
971 .dev_attr = &mmc_dev_attr,
972 .class = &dm81xx_mmc_class,
973};
974
975static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
976 .master = &dm81xx_l4_ls_hwmod,
977 .slave = &dm814x_mmc2_hwmod,
978 .clk = "sysclk6_ck",
979 .user = OCP_USER_MPU,
980 .flags = OMAP_FIREWALL_L4
981};
982
983static struct omap_hwmod dm814x_mmc3_hwmod = {
984 .name = "mmc3",
985 .clkdm_name = "alwon_l3_med_clkdm",
986 .opt_clks = dm81xx_mmc_opt_clks,
987 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
988 .main_clk = "sysclk8_ck",
989 .prcm = {
990 .omap4 = {
991 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
992 .modulemode = MODULEMODE_SWCTRL,
993 },
994 },
995 .dev_attr = &mmc_dev_attr,
996 .class = &dm81xx_mmc_class,
997};
998
999static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
1000 .master = &dm81xx_alwon_l3_med_hwmod,
1001 .slave = &dm814x_mmc3_hwmod,
1002 .clk = "sysclk4_ck",
1003 .user = OCP_USER_MPU,
4d38bd12
TL
1004};
1005
1006static struct omap_hwmod dm816x_mmc1_hwmod = {
1007 .name = "mmc1",
1008 .clkdm_name = "alwon_l3s_clkdm",
c757fda8
TL
1009 .opt_clks = dm81xx_mmc_opt_clks,
1010 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
4d38bd12
TL
1011 .main_clk = "sysclk10_ck",
1012 .prcm = {
1013 .omap4 = {
1014 .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
1015 .modulemode = MODULEMODE_SWCTRL,
1016 },
1017 },
c757fda8
TL
1018 .dev_attr = &mmc_dev_attr,
1019 .class = &dm81xx_mmc_class,
4d38bd12
TL
1020};
1021
1022static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
7e1b11d1 1023 .master = &dm81xx_l4_ls_hwmod,
4d38bd12
TL
1024 .slave = &dm816x_mmc1_hwmod,
1025 .clk = "sysclk6_ck",
1026 .user = OCP_USER_MPU,
1027 .flags = OMAP_FIREWALL_L4
1028};
1029
1030static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
1031 .rev_offs = 0x0,
1032 .sysc_offs = 0x110,
1033 .syss_offs = 0x114,
1034 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1035 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1036 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1037 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1038 .sysc_fields = &omap_hwmod_sysc_type1,
1039};
1040
1041static struct omap_hwmod_class dm816x_mcspi_class = {
1042 .name = "mcspi",
1043 .sysc = &dm816x_mcspi_sysc,
1044 .rev = OMAP3_MCSPI_REV,
1045};
1046
1047static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
1048 .num_chipselect = 4,
1049};
1050
7e1b11d1 1051static struct omap_hwmod dm81xx_mcspi1_hwmod = {
4d38bd12
TL
1052 .name = "mcspi1",
1053 .clkdm_name = "alwon_l3s_clkdm",
1054 .main_clk = "sysclk10_ck",
1055 .prcm = {
1056 .omap4 = {
7e1b11d1 1057 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
4d38bd12
TL
1058 .modulemode = MODULEMODE_SWCTRL,
1059 },
1060 },
1061 .class = &dm816x_mcspi_class,
1062 .dev_attr = &dm816x_mcspi1_dev_attr,
1063};
1064
7e1b11d1
TL
1065static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
1066 .master = &dm81xx_l4_ls_hwmod,
1067 .slave = &dm81xx_mcspi1_hwmod,
4d38bd12
TL
1068 .clk = "sysclk6_ck",
1069 .user = OCP_USER_MPU,
1070};
1071
7e1b11d1 1072static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
4d38bd12
TL
1073 .rev_offs = 0x000,
1074 .sysc_offs = 0x010,
1075 .syss_offs = 0x014,
1076 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1077 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1078 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1079 .sysc_fields = &omap_hwmod_sysc_type1,
1080};
1081
7e1b11d1 1082static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
4d38bd12 1083 .name = "mailbox",
7e1b11d1 1084 .sysc = &dm81xx_mailbox_sysc,
4d38bd12
TL
1085};
1086
7e1b11d1 1087static struct omap_hwmod dm81xx_mailbox_hwmod = {
4d38bd12
TL
1088 .name = "mailbox",
1089 .clkdm_name = "alwon_l3s_clkdm",
7e1b11d1 1090 .class = &dm81xx_mailbox_hwmod_class,
4d38bd12
TL
1091 .main_clk = "sysclk6_ck",
1092 .prcm = {
1093 .omap4 = {
7e1b11d1 1094 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
4d38bd12
TL
1095 .modulemode = MODULEMODE_SWCTRL,
1096 },
1097 },
1098};
1099
7e1b11d1
TL
1100static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
1101 .master = &dm81xx_l4_ls_hwmod,
1102 .slave = &dm81xx_mailbox_hwmod,
4d38bd12
TL
1103 .user = OCP_USER_MPU,
1104};
1105
1539569b
NA
1106static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = {
1107 .rev_offs = 0x000,
1108 .sysc_offs = 0x010,
1109 .syss_offs = 0x014,
1110 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1111 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1112 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1113 .sysc_fields = &omap_hwmod_sysc_type1,
1114};
1115
1116static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = {
1117 .name = "spinbox",
1118 .sysc = &dm81xx_spinbox_sysc,
1119};
1120
1121static struct omap_hwmod dm81xx_spinbox_hwmod = {
1122 .name = "spinbox",
1123 .clkdm_name = "alwon_l3s_clkdm",
1124 .class = &dm81xx_spinbox_hwmod_class,
1125 .main_clk = "sysclk6_ck",
1126 .prcm = {
1127 .omap4 = {
1128 .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL,
1129 .modulemode = MODULEMODE_SWCTRL,
1130 },
1131 },
1132};
1133
1134static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
1135 .master = &dm81xx_l4_ls_hwmod,
1136 .slave = &dm81xx_spinbox_hwmod,
1137 .user = OCP_USER_MPU,
1138};
1139
7e1b11d1 1140static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
4d38bd12
TL
1141 .name = "tpcc",
1142};
1143
24da741c 1144static struct omap_hwmod dm81xx_tpcc_hwmod = {
4d38bd12 1145 .name = "tpcc",
7e1b11d1 1146 .class = &dm81xx_tpcc_hwmod_class,
4d38bd12
TL
1147 .clkdm_name = "alwon_l3s_clkdm",
1148 .main_clk = "sysclk4_ck",
1149 .prcm = {
1150 .omap4 = {
7e1b11d1 1151 .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL,
4d38bd12
TL
1152 .modulemode = MODULEMODE_SWCTRL,
1153 },
1154 },
1155};
1156
24da741c 1157static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
7e1b11d1
TL
1158 .master = &dm81xx_alwon_l3_fast_hwmod,
1159 .slave = &dm81xx_tpcc_hwmod,
4d38bd12
TL
1160 .clk = "sysclk4_ck",
1161 .user = OCP_USER_MPU,
1162};
1163
7e1b11d1 1164static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = {
4d38bd12
TL
1165 {
1166 .pa_start = 0x49800000,
1167 .pa_end = 0x49800000 + SZ_8K - 1,
1168 .flags = ADDR_TYPE_RT,
1169 },
1170 { },
1171};
1172
7e1b11d1 1173static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
4d38bd12
TL
1174 .name = "tptc0",
1175};
1176
24da741c 1177static struct omap_hwmod dm81xx_tptc0_hwmod = {
4d38bd12 1178 .name = "tptc0",
7e1b11d1 1179 .class = &dm81xx_tptc0_hwmod_class,
4d38bd12
TL
1180 .clkdm_name = "alwon_l3s_clkdm",
1181 .main_clk = "sysclk4_ck",
1182 .prcm = {
1183 .omap4 = {
7e1b11d1 1184 .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
4d38bd12
TL
1185 .modulemode = MODULEMODE_SWCTRL,
1186 },
1187 },
1188};
1189
24da741c 1190static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
7e1b11d1
TL
1191 .master = &dm81xx_alwon_l3_fast_hwmod,
1192 .slave = &dm81xx_tptc0_hwmod,
4d38bd12 1193 .clk = "sysclk4_ck",
7e1b11d1 1194 .addr = dm81xx_tptc0_addr_space,
4d38bd12
TL
1195 .user = OCP_USER_MPU,
1196};
1197
24da741c 1198static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
7e1b11d1
TL
1199 .master = &dm81xx_tptc0_hwmod,
1200 .slave = &dm81xx_alwon_l3_fast_hwmod,
4d38bd12 1201 .clk = "sysclk4_ck",
7e1b11d1 1202 .addr = dm81xx_tptc0_addr_space,
4d38bd12
TL
1203 .user = OCP_USER_MPU,
1204};
1205
7e1b11d1 1206static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = {
4d38bd12
TL
1207 {
1208 .pa_start = 0x49900000,
1209 .pa_end = 0x49900000 + SZ_8K - 1,
1210 .flags = ADDR_TYPE_RT,
1211 },
1212 { },
1213};
1214
7e1b11d1 1215static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
4d38bd12
TL
1216 .name = "tptc1",
1217};
1218
24da741c 1219static struct omap_hwmod dm81xx_tptc1_hwmod = {
4d38bd12 1220 .name = "tptc1",
7e1b11d1 1221 .class = &dm81xx_tptc1_hwmod_class,
4d38bd12
TL
1222 .clkdm_name = "alwon_l3s_clkdm",
1223 .main_clk = "sysclk4_ck",
1224 .prcm = {
1225 .omap4 = {
7e1b11d1 1226 .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
4d38bd12
TL
1227 .modulemode = MODULEMODE_SWCTRL,
1228 },
1229 },
1230};
1231
24da741c 1232static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
7e1b11d1
TL
1233 .master = &dm81xx_alwon_l3_fast_hwmod,
1234 .slave = &dm81xx_tptc1_hwmod,
4d38bd12 1235 .clk = "sysclk4_ck",
7e1b11d1 1236 .addr = dm81xx_tptc1_addr_space,
4d38bd12
TL
1237 .user = OCP_USER_MPU,
1238};
1239
24da741c 1240static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
7e1b11d1
TL
1241 .master = &dm81xx_tptc1_hwmod,
1242 .slave = &dm81xx_alwon_l3_fast_hwmod,
4d38bd12 1243 .clk = "sysclk4_ck",
7e1b11d1 1244 .addr = dm81xx_tptc1_addr_space,
4d38bd12
TL
1245 .user = OCP_USER_MPU,
1246};
1247
7e1b11d1 1248static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = {
4d38bd12
TL
1249 {
1250 .pa_start = 0x49a00000,
1251 .pa_end = 0x49a00000 + SZ_8K - 1,
1252 .flags = ADDR_TYPE_RT,
1253 },
1254 { },
1255};
1256
7e1b11d1 1257static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
4d38bd12
TL
1258 .name = "tptc2",
1259};
1260
24da741c 1261static struct omap_hwmod dm81xx_tptc2_hwmod = {
4d38bd12 1262 .name = "tptc2",
7e1b11d1 1263 .class = &dm81xx_tptc2_hwmod_class,
4d38bd12
TL
1264 .clkdm_name = "alwon_l3s_clkdm",
1265 .main_clk = "sysclk4_ck",
1266 .prcm = {
1267 .omap4 = {
7e1b11d1 1268 .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
4d38bd12
TL
1269 .modulemode = MODULEMODE_SWCTRL,
1270 },
1271 },
1272};
1273
24da741c 1274static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
7e1b11d1
TL
1275 .master = &dm81xx_alwon_l3_fast_hwmod,
1276 .slave = &dm81xx_tptc2_hwmod,
4d38bd12 1277 .clk = "sysclk4_ck",
7e1b11d1 1278 .addr = dm81xx_tptc2_addr_space,
4d38bd12
TL
1279 .user = OCP_USER_MPU,
1280};
1281
24da741c 1282static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
7e1b11d1
TL
1283 .master = &dm81xx_tptc2_hwmod,
1284 .slave = &dm81xx_alwon_l3_fast_hwmod,
4d38bd12 1285 .clk = "sysclk4_ck",
7e1b11d1 1286 .addr = dm81xx_tptc2_addr_space,
4d38bd12
TL
1287 .user = OCP_USER_MPU,
1288};
1289
7e1b11d1 1290static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = {
4d38bd12
TL
1291 {
1292 .pa_start = 0x49b00000,
1293 .pa_end = 0x49b00000 + SZ_8K - 1,
1294 .flags = ADDR_TYPE_RT,
1295 },
1296 { },
1297};
1298
7e1b11d1 1299static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
4d38bd12
TL
1300 .name = "tptc3",
1301};
1302
24da741c 1303static struct omap_hwmod dm81xx_tptc3_hwmod = {
4d38bd12 1304 .name = "tptc3",
7e1b11d1 1305 .class = &dm81xx_tptc3_hwmod_class,
4d38bd12
TL
1306 .clkdm_name = "alwon_l3s_clkdm",
1307 .main_clk = "sysclk4_ck",
1308 .prcm = {
1309 .omap4 = {
7e1b11d1 1310 .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
4d38bd12
TL
1311 .modulemode = MODULEMODE_SWCTRL,
1312 },
1313 },
1314};
1315
24da741c 1316static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
7e1b11d1
TL
1317 .master = &dm81xx_alwon_l3_fast_hwmod,
1318 .slave = &dm81xx_tptc3_hwmod,
4d38bd12 1319 .clk = "sysclk4_ck",
7e1b11d1 1320 .addr = dm81xx_tptc3_addr_space,
4d38bd12
TL
1321 .user = OCP_USER_MPU,
1322};
1323
24da741c 1324static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
7e1b11d1
TL
1325 .master = &dm81xx_tptc3_hwmod,
1326 .slave = &dm81xx_alwon_l3_fast_hwmod,
4d38bd12 1327 .clk = "sysclk4_ck",
7e1b11d1 1328 .addr = dm81xx_tptc3_addr_space,
4d38bd12
TL
1329 .user = OCP_USER_MPU,
1330};
1331
0f3ccb24
TL
1332/*
1333 * REVISIT: Test and enable the following once clocks work:
1334 * dm81xx_l4_ls__gpio1
1335 * dm81xx_l4_ls__gpio2
1336 * dm81xx_l4_ls__mailbox
1337 * dm81xx_alwon_l3_slow__gpmc
1338 * dm81xx_default_l3_slow__usbss
1339 *
1340 * Also note that some devices share a single clkctrl_offs..
1341 * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1342 */
1343static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1344 &dm814x_mpu__alwon_l3_slow,
1345 &dm814x_mpu__alwon_l3_med,
1346 &dm81xx_alwon_l3_slow__l4_ls,
1347 &dm81xx_alwon_l3_slow__l4_hs,
1348 &dm81xx_l4_ls__uart1,
1349 &dm81xx_l4_ls__uart2,
1350 &dm81xx_l4_ls__uart3,
1351 &dm81xx_l4_ls__wd_timer1,
1352 &dm81xx_l4_ls__i2c1,
1353 &dm81xx_l4_ls__i2c2,
1354 &dm81xx_l4_ls__elm,
1355 &dm81xx_l4_ls__mcspi1,
c757fda8
TL
1356 &dm814x_l4_ls__mmc1,
1357 &dm814x_l4_ls__mmc2,
0f3ccb24
TL
1358 &dm81xx_alwon_l3_fast__tpcc,
1359 &dm81xx_alwon_l3_fast__tptc0,
1360 &dm81xx_alwon_l3_fast__tptc1,
1361 &dm81xx_alwon_l3_fast__tptc2,
1362 &dm81xx_alwon_l3_fast__tptc3,
1363 &dm81xx_tptc0__alwon_l3_fast,
1364 &dm81xx_tptc1__alwon_l3_fast,
1365 &dm81xx_tptc2__alwon_l3_fast,
1366 &dm81xx_tptc3__alwon_l3_fast,
1367 &dm814x_l4_ls__timer1,
1368 &dm814x_l4_ls__timer2,
1369 &dm814x_l4_hs__cpgmac0,
1370 &dm814x_cpgmac0__mdio,
c757fda8 1371 &dm814x_alwon_l3_med__mmc3,
0f3ccb24
TL
1372 NULL,
1373};
1374
1375int __init dm814x_hwmod_init(void)
1376{
1377 omap_hwmod_init();
1378 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1379}
1380
4d38bd12
TL
1381static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1382 &dm816x_mpu__alwon_l3_slow,
1383 &dm816x_mpu__alwon_l3_med,
7e1b11d1
TL
1384 &dm81xx_alwon_l3_slow__l4_ls,
1385 &dm81xx_alwon_l3_slow__l4_hs,
1386 &dm81xx_l4_ls__uart1,
1387 &dm81xx_l4_ls__uart2,
1388 &dm81xx_l4_ls__uart3,
1389 &dm81xx_l4_ls__wd_timer1,
1390 &dm81xx_l4_ls__i2c1,
1391 &dm81xx_l4_ls__i2c2,
4d38bd12
TL
1392 &dm81xx_l4_ls__gpio1,
1393 &dm81xx_l4_ls__gpio2,
1394 &dm81xx_l4_ls__elm,
1395 &dm816x_l4_ls__mmc1,
1396 &dm816x_l4_ls__timer1,
1397 &dm816x_l4_ls__timer2,
1398 &dm816x_l4_ls__timer3,
1399 &dm816x_l4_ls__timer4,
1400 &dm816x_l4_ls__timer5,
1401 &dm816x_l4_ls__timer6,
1402 &dm816x_l4_ls__timer7,
7e1b11d1
TL
1403 &dm81xx_l4_ls__mcspi1,
1404 &dm81xx_l4_ls__mailbox,
1539569b 1405 &dm81xx_l4_ls__spinbox,
7e1b11d1
TL
1406 &dm81xx_l4_hs__emac0,
1407 &dm81xx_emac0__mdio,
4d38bd12 1408 &dm816x_l4_hs__emac1,
7e1b11d1
TL
1409 &dm81xx_alwon_l3_fast__tpcc,
1410 &dm81xx_alwon_l3_fast__tptc0,
1411 &dm81xx_alwon_l3_fast__tptc1,
1412 &dm81xx_alwon_l3_fast__tptc2,
1413 &dm81xx_alwon_l3_fast__tptc3,
1414 &dm81xx_tptc0__alwon_l3_fast,
1415 &dm81xx_tptc1__alwon_l3_fast,
1416 &dm81xx_tptc2__alwon_l3_fast,
1417 &dm81xx_tptc3__alwon_l3_fast,
4d38bd12
TL
1418 &dm81xx_alwon_l3_slow__gpmc,
1419 &dm81xx_default_l3_slow__usbss,
1420 NULL,
1421};
1422
0f3ccb24 1423int __init dm816x_hwmod_init(void)
4d38bd12
TL
1424{
1425 omap_hwmod_init();
1426 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
1427}