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OMAP4: hwmod data: Add clock domain attribute
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
CommitLineData
55d2cb08
BC		 1/*
2 * Hardware modules present on the OMAP44xx chips
3 *
d63bd74f 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
55d2cb08
BC		 5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/io.h>
22
23#include <plat/omap_hwmod.h>
24#include <plat/cpu.h>
6d3c55fd 25#include <plat/i2c.h>
9780a9cf 26#include <plat/gpio.h>
531ce0d5 27#include <plat/dma.h>
905a74d9 28#include <plat/mcspi.h>
cb7e9ded 29#include <plat/mcbsp.h>
6ab8946f 30#include <plat/mmc.h>
4d4441a6 31#include <plat/i2c.h>
55d2cb08
BC		 32
33#include "omap_hwmod_common_data.h"
34
d198b514
PW		 35#include "cm1_44xx.h"
36#include "cm2_44xx.h"
37#include "prm44xx.h"
55d2cb08 38#include "prm-regbits-44xx.h"
ff2516fb 39#include "wd_timer.h"
55d2cb08
BC		 40
41/* Base offset for all OMAP4 interrupts external to MPUSS */
42#define OMAP44XX_IRQ_GIC_START 32
43
44/* Base offset for all OMAP4 dma requests */
45#define OMAP44XX_DMA_REQ_START 1
46
47/* Backward references (IPs with Bus Master capability) */
407a6888 48static struct omap_hwmod omap44xx_aess_hwmod;
531ce0d5 49static struct omap_hwmod omap44xx_dma_system_hwmod;
55d2cb08 50static struct omap_hwmod omap44xx_dmm_hwmod;
8f25bdc5 51static struct omap_hwmod omap44xx_dsp_hwmod;
d63bd74f 52static struct omap_hwmod omap44xx_dss_hwmod;
55d2cb08 53static struct omap_hwmod omap44xx_emif_fw_hwmod;
407a6888
BC		 54static struct omap_hwmod omap44xx_hsi_hwmod;
55static struct omap_hwmod omap44xx_ipu_hwmod;
56static struct omap_hwmod omap44xx_iss_hwmod;
8f25bdc5 57static struct omap_hwmod omap44xx_iva_hwmod;
55d2cb08
BC		 58static struct omap_hwmod omap44xx_l3_instr_hwmod;
59static struct omap_hwmod omap44xx_l3_main_1_hwmod;
60static struct omap_hwmod omap44xx_l3_main_2_hwmod;
61static struct omap_hwmod omap44xx_l3_main_3_hwmod;
62static struct omap_hwmod omap44xx_l4_abe_hwmod;
63static struct omap_hwmod omap44xx_l4_cfg_hwmod;
64static struct omap_hwmod omap44xx_l4_per_hwmod;
65static struct omap_hwmod omap44xx_l4_wkup_hwmod;
407a6888
BC		 66static struct omap_hwmod omap44xx_mmc1_hwmod;
67static struct omap_hwmod omap44xx_mmc2_hwmod;
55d2cb08
BC		 68static struct omap_hwmod omap44xx_mpu_hwmod;
69static struct omap_hwmod omap44xx_mpu_private_hwmod;
5844c4ea 70static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
55d2cb08
BC		 71
72/*
73 * Interconnects omap_hwmod structures
74 * hwmods that compose the global OMAP interconnect
75 */
76
77/*
78 * 'dmm' class
79 * instance(s): dmm
80 */
81static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
fe13471c 82 .name = "dmm",
55d2cb08
BC		 83};
84
7e69ed97
BC		 85/* dmm */
86static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
87 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
88 { .irq = -1 }
89};
90
55d2cb08
BC		 91/* l3_main_1 -> dmm */
92static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
93 .master = &omap44xx_l3_main_1_hwmod,
94 .slave = &omap44xx_dmm_hwmod,
95 .clk = "l3_div_ck",
659fa822
BC		 96 .user = OCP_USER_SDMA,
97};
98
99static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
100 {
101 .pa_start = 0x4e000000,
102 .pa_end = 0x4e0007ff,
103 .flags = ADDR_TYPE_RT
104 },
78183f3f 105 { }
55d2cb08
BC		 106};
107
108/* mpu -> dmm */
109static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
110 .master = &omap44xx_mpu_hwmod,
111 .slave = &omap44xx_dmm_hwmod,
112 .clk = "l3_div_ck",
659fa822 113 .addr = omap44xx_dmm_addrs,
659fa822 114 .user = OCP_USER_MPU,
55d2cb08
BC		 115};
116
117/* dmm slave ports */
118static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
119 &omap44xx_l3_main_1__dmm,
120 &omap44xx_mpu__dmm,
121};
122
55d2cb08
BC		 123static struct omap_hwmod omap44xx_dmm_hwmod = {
124 .name = "dmm",
125 .class = &omap44xx_dmm_hwmod_class,
a5322c6f 126 .clkdm_name = "l3_emif_clkdm",
55d2cb08
BC		 127 .slaves = omap44xx_dmm_slaves,
128 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
a5322c6f 129 .mpu_irqs = omap44xx_dmm_irqs,
55d2cb08
BC		 130 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
131};
132
133/*
134 * 'emif_fw' class
135 * instance(s): emif_fw
136 */
137static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
fe13471c 138 .name = "emif_fw",
55d2cb08
BC		 139};
140
7e69ed97 141/* emif_fw */
55d2cb08
BC		 142/* dmm -> emif_fw */
143static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
144 .master = &omap44xx_dmm_hwmod,
145 .slave = &omap44xx_emif_fw_hwmod,
146 .clk = "l3_div_ck",
147 .user = OCP_USER_MPU | OCP_USER_SDMA,
148};
149
659fa822
BC		 150static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
151 {
152 .pa_start = 0x4a20c000,
153 .pa_end = 0x4a20c0ff,
154 .flags = ADDR_TYPE_RT
155 },
78183f3f 156 { }
659fa822
BC		 157};
158
55d2cb08
BC		 159/* l4_cfg -> emif_fw */
160static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
161 .master = &omap44xx_l4_cfg_hwmod,
162 .slave = &omap44xx_emif_fw_hwmod,
163 .clk = "l4_div_ck",
659fa822 164 .addr = omap44xx_emif_fw_addrs,
659fa822 165 .user = OCP_USER_MPU,
55d2cb08
BC		 166};
167
168/* emif_fw slave ports */
169static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
170 &omap44xx_dmm__emif_fw,
171 &omap44xx_l4_cfg__emif_fw,
172};
173
174static struct omap_hwmod omap44xx_emif_fw_hwmod = {
175 .name = "emif_fw",
176 .class = &omap44xx_emif_fw_hwmod_class,
a5322c6f 177 .clkdm_name = "l3_emif_clkdm",
55d2cb08
BC		 178 .slaves = omap44xx_emif_fw_slaves,
179 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
180 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
181};
182
183/*
184 * 'l3' class
185 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
186 */
187static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
fe13471c 188 .name = "l3",
55d2cb08
BC		 189};
190
7e69ed97 191/* l3_instr */
8f25bdc5
BC		 192/* iva -> l3_instr */
193static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
194 .master = &omap44xx_iva_hwmod,
195 .slave = &omap44xx_l3_instr_hwmod,
196 .clk = "l3_div_ck",
197 .user = OCP_USER_MPU | OCP_USER_SDMA,
198};
199
55d2cb08
BC		 200/* l3_main_3 -> l3_instr */
201static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
202 .master = &omap44xx_l3_main_3_hwmod,
203 .slave = &omap44xx_l3_instr_hwmod,
204 .clk = "l3_div_ck",
205 .user = OCP_USER_MPU | OCP_USER_SDMA,
206};
207
208/* l3_instr slave ports */
209static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
8f25bdc5 210 &omap44xx_iva__l3_instr,
55d2cb08
BC		 211 &omap44xx_l3_main_3__l3_instr,
212};
213
214static struct omap_hwmod omap44xx_l3_instr_hwmod = {
215 .name = "l3_instr",
216 .class = &omap44xx_l3_hwmod_class,
a5322c6f 217 .clkdm_name = "l3_instr_clkdm",
55d2cb08
BC		 218 .slaves = omap44xx_l3_instr_slaves,
219 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
220 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
221};
222
7e69ed97 223/* l3_main_1 */
9b4021be
BC		 224static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
225 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
226 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
227 { .irq = -1 }
228};
229
8f25bdc5
BC		 230/* dsp -> l3_main_1 */
231static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
232 .master = &omap44xx_dsp_hwmod,
233 .slave = &omap44xx_l3_main_1_hwmod,
234 .clk = "l3_div_ck",
235 .user = OCP_USER_MPU | OCP_USER_SDMA,
236};
237
d63bd74f
BC		 238/* dss -> l3_main_1 */
239static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
240 .master = &omap44xx_dss_hwmod,
241 .slave = &omap44xx_l3_main_1_hwmod,
242 .clk = "l3_div_ck",
243 .user = OCP_USER_MPU | OCP_USER_SDMA,
244};
245
55d2cb08
BC		 246/* l3_main_2 -> l3_main_1 */
247static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
248 .master = &omap44xx_l3_main_2_hwmod,
249 .slave = &omap44xx_l3_main_1_hwmod,
250 .clk = "l3_div_ck",
251 .user = OCP_USER_MPU | OCP_USER_SDMA,
252};
253
254/* l4_cfg -> l3_main_1 */
255static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
256 .master = &omap44xx_l4_cfg_hwmod,
257 .slave = &omap44xx_l3_main_1_hwmod,
258 .clk = "l4_div_ck",
259 .user = OCP_USER_MPU | OCP_USER_SDMA,
260};
261
407a6888
BC		 262/* mmc1 -> l3_main_1 */
263static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
264 .master = &omap44xx_mmc1_hwmod,
265 .slave = &omap44xx_l3_main_1_hwmod,
266 .clk = "l3_div_ck",
267 .user = OCP_USER_MPU | OCP_USER_SDMA,
268};
269
270/* mmc2 -> l3_main_1 */
271static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
272 .master = &omap44xx_mmc2_hwmod,
273 .slave = &omap44xx_l3_main_1_hwmod,
274 .clk = "l3_div_ck",
275 .user = OCP_USER_MPU | OCP_USER_SDMA,
276};
277
c4645234 278static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
279 {
280 .pa_start = 0x44000000,
281 .pa_end = 0x44000fff,
9b4021be 282 .flags = ADDR_TYPE_RT
c4645234 283 },
78183f3f 284 { }
c4645234 285};
286
55d2cb08
BC		 287/* mpu -> l3_main_1 */
288static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
289 .master = &omap44xx_mpu_hwmod,
290 .slave = &omap44xx_l3_main_1_hwmod,
291 .clk = "l3_div_ck",
c4645234 292 .addr = omap44xx_l3_main_1_addrs,
9b4021be 293 .user = OCP_USER_MPU,
55d2cb08
BC		 294};
295
296/* l3_main_1 slave ports */
297static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
8f25bdc5 298 &omap44xx_dsp__l3_main_1,
d63bd74f 299 &omap44xx_dss__l3_main_1,
55d2cb08
BC		 300 &omap44xx_l3_main_2__l3_main_1,
301 &omap44xx_l4_cfg__l3_main_1,
407a6888
BC		 302 &omap44xx_mmc1__l3_main_1,
303 &omap44xx_mmc2__l3_main_1,
55d2cb08
BC		 304 &omap44xx_mpu__l3_main_1,
305};
306
307static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
308 .name = "l3_main_1",
309 .class = &omap44xx_l3_hwmod_class,
a5322c6f 310 .clkdm_name = "l3_1_clkdm",
7e69ed97 311 .mpu_irqs = omap44xx_l3_main_1_irqs,
55d2cb08
BC		 312 .slaves = omap44xx_l3_main_1_slaves,
313 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
314 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
315};
316
7e69ed97 317/* l3_main_2 */
d7cf5f33
BC		 318/* dma_system -> l3_main_2 */
319static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
320 .master = &omap44xx_dma_system_hwmod,
321 .slave = &omap44xx_l3_main_2_hwmod,
322 .clk = "l3_div_ck",
323 .user = OCP_USER_MPU | OCP_USER_SDMA,
324};
325
407a6888
BC		 326/* hsi -> l3_main_2 */
327static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
328 .master = &omap44xx_hsi_hwmod,
329 .slave = &omap44xx_l3_main_2_hwmod,
330 .clk = "l3_div_ck",
331 .user = OCP_USER_MPU | OCP_USER_SDMA,
332};
333
334/* ipu -> l3_main_2 */
335static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
336 .master = &omap44xx_ipu_hwmod,
337 .slave = &omap44xx_l3_main_2_hwmod,
338 .clk = "l3_div_ck",
339 .user = OCP_USER_MPU | OCP_USER_SDMA,
340};
341
342/* iss -> l3_main_2 */
343static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
344 .master = &omap44xx_iss_hwmod,
345 .slave = &omap44xx_l3_main_2_hwmod,
346 .clk = "l3_div_ck",
347 .user = OCP_USER_MPU | OCP_USER_SDMA,
348};
349
8f25bdc5
BC		 350/* iva -> l3_main_2 */
351static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
352 .master = &omap44xx_iva_hwmod,
353 .slave = &omap44xx_l3_main_2_hwmod,
354 .clk = "l3_div_ck",
355 .user = OCP_USER_MPU | OCP_USER_SDMA,
356};
357
c4645234 358static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
359 {
360 .pa_start = 0x44800000,
361 .pa_end = 0x44801fff,
9b4021be 362 .flags = ADDR_TYPE_RT
c4645234 363 },
78183f3f 364 { }
c4645234 365};
366
55d2cb08
BC		 367/* l3_main_1 -> l3_main_2 */
368static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
369 .master = &omap44xx_l3_main_1_hwmod,
370 .slave = &omap44xx_l3_main_2_hwmod,
371 .clk = "l3_div_ck",
c4645234 372 .addr = omap44xx_l3_main_2_addrs,
9b4021be 373 .user = OCP_USER_MPU,
55d2cb08
BC		 374};
375
376/* l4_cfg -> l3_main_2 */
377static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
378 .master = &omap44xx_l4_cfg_hwmod,
379 .slave = &omap44xx_l3_main_2_hwmod,
380 .clk = "l4_div_ck",
381 .user = OCP_USER_MPU | OCP_USER_SDMA,
382};
383
5844c4ea
BC		 384/* usb_otg_hs -> l3_main_2 */
385static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
386 .master = &omap44xx_usb_otg_hs_hwmod,
387 .slave = &omap44xx_l3_main_2_hwmod,
388 .clk = "l3_div_ck",
389 .user = OCP_USER_MPU | OCP_USER_SDMA,
390};
391
55d2cb08
BC		 392/* l3_main_2 slave ports */
393static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
531ce0d5 394 &omap44xx_dma_system__l3_main_2,
407a6888
BC		 395 &omap44xx_hsi__l3_main_2,
396 &omap44xx_ipu__l3_main_2,
397 &omap44xx_iss__l3_main_2,
8f25bdc5 398 &omap44xx_iva__l3_main_2,
55d2cb08
BC		 399 &omap44xx_l3_main_1__l3_main_2,
400 &omap44xx_l4_cfg__l3_main_2,
5844c4ea 401 &omap44xx_usb_otg_hs__l3_main_2,
55d2cb08
BC		 402};
403
404static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
405 .name = "l3_main_2",
406 .class = &omap44xx_l3_hwmod_class,
a5322c6f 407 .clkdm_name = "l3_2_clkdm",
55d2cb08
BC		 408 .slaves = omap44xx_l3_main_2_slaves,
409 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
410 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
411};
412
7e69ed97 413/* l3_main_3 */
c4645234 414static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
415 {
416 .pa_start = 0x45000000,
417 .pa_end = 0x45000fff,
9b4021be 418 .flags = ADDR_TYPE_RT
c4645234 419 },
78183f3f 420 { }
c4645234 421};
422
55d2cb08
BC		 423/* l3_main_1 -> l3_main_3 */
424static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
425 .master = &omap44xx_l3_main_1_hwmod,
426 .slave = &omap44xx_l3_main_3_hwmod,
427 .clk = "l3_div_ck",
c4645234 428 .addr = omap44xx_l3_main_3_addrs,
9b4021be 429 .user = OCP_USER_MPU,
55d2cb08
BC		 430};
431
432/* l3_main_2 -> l3_main_3 */
433static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
434 .master = &omap44xx_l3_main_2_hwmod,
435 .slave = &omap44xx_l3_main_3_hwmod,
436 .clk = "l3_div_ck",
437 .user = OCP_USER_MPU | OCP_USER_SDMA,
438};
439
440/* l4_cfg -> l3_main_3 */
441static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
442 .master = &omap44xx_l4_cfg_hwmod,
443 .slave = &omap44xx_l3_main_3_hwmod,
444 .clk = "l4_div_ck",
445 .user = OCP_USER_MPU | OCP_USER_SDMA,
446};
447
448/* l3_main_3 slave ports */
449static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
450 &omap44xx_l3_main_1__l3_main_3,
451 &omap44xx_l3_main_2__l3_main_3,
452 &omap44xx_l4_cfg__l3_main_3,
453};
454
455static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
456 .name = "l3_main_3",
457 .class = &omap44xx_l3_hwmod_class,
a5322c6f 458 .clkdm_name = "l3_instr_clkdm",
55d2cb08
BC		 459 .slaves = omap44xx_l3_main_3_slaves,
460 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
461 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
462};
463
464/*
465 * 'l4' class
466 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
467 */
468static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
fe13471c 469 .name = "l4",
55d2cb08
BC		 470};
471
7e69ed97 472/* l4_abe */
407a6888
BC		 473/* aess -> l4_abe */
474static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
475 .master = &omap44xx_aess_hwmod,
476 .slave = &omap44xx_l4_abe_hwmod,
477 .clk = "ocp_abe_iclk",
478 .user = OCP_USER_MPU | OCP_USER_SDMA,
479};
480
8f25bdc5
BC		 481/* dsp -> l4_abe */
482static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
483 .master = &omap44xx_dsp_hwmod,
484 .slave = &omap44xx_l4_abe_hwmod,
485 .clk = "ocp_abe_iclk",
486 .user = OCP_USER_MPU | OCP_USER_SDMA,
487};
488
55d2cb08
BC		 489/* l3_main_1 -> l4_abe */
490static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
491 .master = &omap44xx_l3_main_1_hwmod,
492 .slave = &omap44xx_l4_abe_hwmod,
493 .clk = "l3_div_ck",
494 .user = OCP_USER_MPU | OCP_USER_SDMA,
495};
496
497/* mpu -> l4_abe */
498static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
499 .master = &omap44xx_mpu_hwmod,
500 .slave = &omap44xx_l4_abe_hwmod,
501 .clk = "ocp_abe_iclk",
502 .user = OCP_USER_MPU | OCP_USER_SDMA,
503};
504
505/* l4_abe slave ports */
506static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
407a6888 507 &omap44xx_aess__l4_abe,
8f25bdc5 508 &omap44xx_dsp__l4_abe,
55d2cb08
BC		 509 &omap44xx_l3_main_1__l4_abe,
510 &omap44xx_mpu__l4_abe,
511};
512
513static struct omap_hwmod omap44xx_l4_abe_hwmod = {
514 .name = "l4_abe",
515 .class = &omap44xx_l4_hwmod_class,
a5322c6f 516 .clkdm_name = "abe_clkdm",
55d2cb08
BC		 517 .slaves = omap44xx_l4_abe_slaves,
518 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
519 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
520};
521
7e69ed97 522/* l4_cfg */
55d2cb08
BC		 523/* l3_main_1 -> l4_cfg */
524static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
525 .master = &omap44xx_l3_main_1_hwmod,
526 .slave = &omap44xx_l4_cfg_hwmod,
527 .clk = "l3_div_ck",
528 .user = OCP_USER_MPU | OCP_USER_SDMA,
529};
530
531/* l4_cfg slave ports */
532static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
533 &omap44xx_l3_main_1__l4_cfg,
534};
535
536static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
537 .name = "l4_cfg",
538 .class = &omap44xx_l4_hwmod_class,
a5322c6f 539 .clkdm_name = "l4_cfg_clkdm",
55d2cb08
BC		 540 .slaves = omap44xx_l4_cfg_slaves,
541 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
542 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
543};
544
7e69ed97 545/* l4_per */
55d2cb08
BC		 546/* l3_main_2 -> l4_per */
547static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
548 .master = &omap44xx_l3_main_2_hwmod,
549 .slave = &omap44xx_l4_per_hwmod,
550 .clk = "l3_div_ck",
551 .user = OCP_USER_MPU | OCP_USER_SDMA,
552};
553
554/* l4_per slave ports */
555static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
556 &omap44xx_l3_main_2__l4_per,
557};
558
559static struct omap_hwmod omap44xx_l4_per_hwmod = {
560 .name = "l4_per",
561 .class = &omap44xx_l4_hwmod_class,
a5322c6f 562 .clkdm_name = "l4_per_clkdm",
55d2cb08
BC		 563 .slaves = omap44xx_l4_per_slaves,
564 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
565 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
566};
567
7e69ed97 568/* l4_wkup */
55d2cb08
BC		 569/* l4_cfg -> l4_wkup */
570static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
571 .master = &omap44xx_l4_cfg_hwmod,
572 .slave = &omap44xx_l4_wkup_hwmod,
573 .clk = "l4_div_ck",
574 .user = OCP_USER_MPU | OCP_USER_SDMA,
575};
576
577/* l4_wkup slave ports */
578static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
579 &omap44xx_l4_cfg__l4_wkup,
580};
581
582static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
583 .name = "l4_wkup",
584 .class = &omap44xx_l4_hwmod_class,
a5322c6f 585 .clkdm_name = "l4_wkup_clkdm",
55d2cb08
BC		 586 .slaves = omap44xx_l4_wkup_slaves,
587 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
588 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
589};
590
f776471f 591/*
3b54baad
BC		 592 * 'mpu_bus' class
593 * instance(s): mpu_private
f776471f 594 */
3b54baad 595static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
fe13471c 596 .name = "mpu_bus",
3b54baad 597};
f776471f 598
7e69ed97 599/* mpu_private */
3b54baad
BC		 600/* mpu -> mpu_private */
601static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
602 .master = &omap44xx_mpu_hwmod,
603 .slave = &omap44xx_mpu_private_hwmod,
604 .clk = "l3_div_ck",
605 .user = OCP_USER_MPU | OCP_USER_SDMA,
606};
607
608/* mpu_private slave ports */
609static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
610 &omap44xx_mpu__mpu_private,
611};
612
613static struct omap_hwmod omap44xx_mpu_private_hwmod = {
614 .name = "mpu_private",
615 .class = &omap44xx_mpu_bus_hwmod_class,
a5322c6f 616 .clkdm_name = "mpuss_clkdm",
3b54baad
BC		 617 .slaves = omap44xx_mpu_private_slaves,
618 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
619 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
620};
621
622/*
623 * Modules omap_hwmod structures
624 *
625 * The following IPs are excluded for the moment because:
626 * - They do not need an explicit SW control using omap_hwmod API.
627 * - They still need to be validated with the driver
628 * properly adapted to omap_hwmod / omap_device
629 *
3b54baad
BC		 630 * c2c
631 * c2c_target_fw
632 * cm_core
633 * cm_core_aon
3b54baad
BC		 634 * ctrl_module_core
635 * ctrl_module_pad_core
636 * ctrl_module_pad_wkup
637 * ctrl_module_wkup
638 * debugss
3b54baad
BC		 639 * efuse_ctrl_cust
640 * efuse_ctrl_std
641 * elm
642 * emif1
643 * emif2
644 * fdif
645 * gpmc
646 * gpu
647 * hdq1w
00fe610b
BC		 648 * mcasp
649 * mpu_c0
650 * mpu_c1
3b54baad
BC		 651 * ocmc_ram
652 * ocp2scp_usb_phy
653 * ocp_wp_noc
3b54baad
BC		 654 * prcm_mpu
655 * prm
656 * scrm
657 * sl2if
658 * slimbus1
659 * slimbus2
3b54baad
BC		 660 * usb_host_fs
661 * usb_host_hs
3b54baad
BC		 662 * usb_phy_cm
663 * usb_tll_hs
664 * usim
665 */
666
407a6888
BC		 667/*
668 * 'aess' class
669 * audio engine sub system
670 */
671
672static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
673 .rev_offs = 0x0000,
674 .sysc_offs = 0x0010,
675 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
676 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
c614ebf6
BC		 677 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
678 MSTANDBY_SMART_WKUP),
407a6888
BC		 679 .sysc_fields = &omap_hwmod_sysc_type2,
680};
681
682static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
683 .name = "aess",
684 .sysc = &omap44xx_aess_sysc,
685};
686
687/* aess */
688static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
689 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
212738a4 690 { .irq = -1 }
407a6888
BC		 691};
692
693static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
694 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
695 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
696 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
697 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
698 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
699 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
700 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
701 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
bc614958 702 { .dma_req = -1 }
407a6888
BC		 703};
704
705/* aess master ports */
706static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
707 &omap44xx_aess__l4_abe,
708};
709
710static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
711 {
712 .pa_start = 0x401f1000,
713 .pa_end = 0x401f13ff,
714 .flags = ADDR_TYPE_RT
715 },
78183f3f 716 { }
407a6888
BC		 717};
718
719/* l4_abe -> aess */
720static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
721 .master = &omap44xx_l4_abe_hwmod,
722 .slave = &omap44xx_aess_hwmod,
723 .clk = "ocp_abe_iclk",
724 .addr = omap44xx_aess_addrs,
407a6888
BC		 725 .user = OCP_USER_MPU,
726};
727
728static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
729 {
730 .pa_start = 0x490f1000,
731 .pa_end = 0x490f13ff,
732 .flags = ADDR_TYPE_RT
733 },
78183f3f 734 { }
407a6888
BC		 735};
736
737/* l4_abe -> aess (dma) */
738static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
739 .master = &omap44xx_l4_abe_hwmod,
740 .slave = &omap44xx_aess_hwmod,
741 .clk = "ocp_abe_iclk",
742 .addr = omap44xx_aess_dma_addrs,
407a6888
BC		 743 .user = OCP_USER_SDMA,
744};
745
746/* aess slave ports */
747static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
748 &omap44xx_l4_abe__aess,
749 &omap44xx_l4_abe__aess_dma,
750};
751
752static struct omap_hwmod omap44xx_aess_hwmod = {
753 .name = "aess",
754 .class = &omap44xx_aess_hwmod_class,
a5322c6f 755 .clkdm_name = "abe_clkdm",
407a6888 756 .mpu_irqs = omap44xx_aess_irqs,
407a6888 757 .sdma_reqs = omap44xx_aess_sdma_reqs,
407a6888 758 .main_clk = "aess_fck",
00fe610b 759 .prcm = {
407a6888
BC		 760 .omap4 = {
761 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
762 },
763 },
764 .slaves = omap44xx_aess_slaves,
765 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
766 .masters = omap44xx_aess_masters,
767 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
768 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
769};
770
771/*
772 * 'bandgap' class
773 * bangap reference for ldo regulators
774 */
775
776static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
777 .name = "bandgap",
778};
779
780/* bandgap */
781static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
782 { .role = "fclk", .clk = "bandgap_fclk" },
783};
784
785static struct omap_hwmod omap44xx_bandgap_hwmod = {
786 .name = "bandgap",
787 .class = &omap44xx_bandgap_hwmod_class,
a5322c6f 788 .clkdm_name = "l4_wkup_clkdm",
00fe610b 789 .prcm = {
407a6888
BC		 790 .omap4 = {
791 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
792 },
793 },
794 .opt_clks = bandgap_opt_clks,
795 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
796 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
797};
798
799/*
800 * 'counter' class
801 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
802 */
803
804static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
805 .rev_offs = 0x0000,
806 .sysc_offs = 0x0004,
807 .sysc_flags = SYSC_HAS_SIDLEMODE,
808 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
809 SIDLE_SMART_WKUP),
810 .sysc_fields = &omap_hwmod_sysc_type1,
811};
812
813static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
814 .name = "counter",
815 .sysc = &omap44xx_counter_sysc,
816};
817
818/* counter_32k */
819static struct omap_hwmod omap44xx_counter_32k_hwmod;
820static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
821 {
822 .pa_start = 0x4a304000,
823 .pa_end = 0x4a30401f,
824 .flags = ADDR_TYPE_RT
825 },
78183f3f 826 { }
407a6888
BC		 827};
828
829/* l4_wkup -> counter_32k */
830static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
831 .master = &omap44xx_l4_wkup_hwmod,
832 .slave = &omap44xx_counter_32k_hwmod,
833 .clk = "l4_wkup_clk_mux_ck",
834 .addr = omap44xx_counter_32k_addrs,
407a6888
BC		 835 .user = OCP_USER_MPU | OCP_USER_SDMA,
836};
837
838/* counter_32k slave ports */
839static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
840 &omap44xx_l4_wkup__counter_32k,
841};
842
843static struct omap_hwmod omap44xx_counter_32k_hwmod = {
844 .name = "counter_32k",
845 .class = &omap44xx_counter_hwmod_class,
a5322c6f 846 .clkdm_name = "l4_wkup_clkdm",
407a6888
BC		 847 .flags = HWMOD_SWSUP_SIDLE,
848 .main_clk = "sys_32k_ck",
00fe610b 849 .prcm = {
407a6888
BC		 850 .omap4 = {
851 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
852 },
853 },
854 .slaves = omap44xx_counter_32k_slaves,
855 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
856 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
857};
858
d7cf5f33
BC		 859/*
860 * 'dma' class
861 * dma controller for data exchange between memory to memory (i.e. internal or
862 * external memory) and gp peripherals to memory or memory to gp peripherals
863 */
864
865static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
866 .rev_offs = 0x0000,
867 .sysc_offs = 0x002c,
868 .syss_offs = 0x0028,
869 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
870 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
871 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
872 SYSS_HAS_RESET_STATUS),
873 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
874 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
875 .sysc_fields = &omap_hwmod_sysc_type1,
876};
877
878static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
879 .name = "dma",
880 .sysc = &omap44xx_dma_sysc,
881};
882
883/* dma dev_attr */
884static struct omap_dma_dev_attr dma_dev_attr = {
885 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
886 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
887 .lch_count = 32,
888};
889
890/* dma_system */
891static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
892 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
893 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
894 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
895 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
212738a4 896 { .irq = -1 }
d7cf5f33
BC		 897};
898
899/* dma_system master ports */
900static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
901 &omap44xx_dma_system__l3_main_2,
902};
903
904static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
905 {
906 .pa_start = 0x4a056000,
1286eeb2 907 .pa_end = 0x4a056fff,
d7cf5f33
BC		 908 .flags = ADDR_TYPE_RT
909 },
78183f3f 910 { }
d7cf5f33
BC		 911};
912
913/* l4_cfg -> dma_system */
914static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
915 .master = &omap44xx_l4_cfg_hwmod,
916 .slave = &omap44xx_dma_system_hwmod,
917 .clk = "l4_div_ck",
918 .addr = omap44xx_dma_system_addrs,
d7cf5f33
BC		 919 .user = OCP_USER_MPU | OCP_USER_SDMA,
920};
921
922/* dma_system slave ports */
923static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
924 &omap44xx_l4_cfg__dma_system,
925};
926
927static struct omap_hwmod omap44xx_dma_system_hwmod = {
928 .name = "dma_system",
929 .class = &omap44xx_dma_hwmod_class,
a5322c6f 930 .clkdm_name = "l3_dma_clkdm",
d7cf5f33 931 .mpu_irqs = omap44xx_dma_system_irqs,
d7cf5f33
BC		 932 .main_clk = "l3_div_ck",
933 .prcm = {
934 .omap4 = {
935 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
936 },
937 },
938 .dev_attr = &dma_dev_attr,
939 .slaves = omap44xx_dma_system_slaves,
940 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
941 .masters = omap44xx_dma_system_masters,
942 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
943 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
944};
945
8ca476da
BC		 946/*
947 * 'dmic' class
948 * digital microphone controller
949 */
950
951static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
952 .rev_offs = 0x0000,
953 .sysc_offs = 0x0010,
954 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
955 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
956 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
957 SIDLE_SMART_WKUP),
958 .sysc_fields = &omap_hwmod_sysc_type2,
959};
960
961static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
962 .name = "dmic",
963 .sysc = &omap44xx_dmic_sysc,
964};
965
966/* dmic */
967static struct omap_hwmod omap44xx_dmic_hwmod;
968static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
969 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
212738a4 970 { .irq = -1 }
8ca476da
BC		 971};
972
973static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
974 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
bc614958 975 { .dma_req = -1 }
8ca476da
BC		 976};
977
978static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
979 {
980 .pa_start = 0x4012e000,
981 .pa_end = 0x4012e07f,
982 .flags = ADDR_TYPE_RT
983 },
78183f3f 984 { }
8ca476da
BC		 985};
986
987/* l4_abe -> dmic */
988static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
989 .master = &omap44xx_l4_abe_hwmod,
990 .slave = &omap44xx_dmic_hwmod,
991 .clk = "ocp_abe_iclk",
992 .addr = omap44xx_dmic_addrs,
8ca476da
BC		 993 .user = OCP_USER_MPU,
994};
995
996static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
997 {
998 .pa_start = 0x4902e000,
999 .pa_end = 0x4902e07f,
1000 .flags = ADDR_TYPE_RT
1001 },
78183f3f 1002 { }
8ca476da
BC		 1003};
1004
1005/* l4_abe -> dmic (dma) */
1006static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1007 .master = &omap44xx_l4_abe_hwmod,
1008 .slave = &omap44xx_dmic_hwmod,
1009 .clk = "ocp_abe_iclk",
1010 .addr = omap44xx_dmic_dma_addrs,
8ca476da
BC		 1011 .user = OCP_USER_SDMA,
1012};
1013
1014/* dmic slave ports */
1015static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1016 &omap44xx_l4_abe__dmic,
1017 &omap44xx_l4_abe__dmic_dma,
1018};
1019
1020static struct omap_hwmod omap44xx_dmic_hwmod = {
1021 .name = "dmic",
1022 .class = &omap44xx_dmic_hwmod_class,
a5322c6f 1023 .clkdm_name = "abe_clkdm",
8ca476da 1024 .mpu_irqs = omap44xx_dmic_irqs,
8ca476da 1025 .sdma_reqs = omap44xx_dmic_sdma_reqs,
8ca476da 1026 .main_clk = "dmic_fck",
00fe610b 1027 .prcm = {
8ca476da
BC		 1028 .omap4 = {
1029 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1030 },
1031 },
1032 .slaves = omap44xx_dmic_slaves,
1033 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1034 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1035};
1036
8f25bdc5
BC		 1037/*
1038 * 'dsp' class
1039 * dsp sub-system
1040 */
1041
1042static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
fe13471c 1043 .name = "dsp",
8f25bdc5
BC		 1044};
1045
1046/* dsp */
1047static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1048 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
212738a4 1049 { .irq = -1 }
8f25bdc5
BC		 1050};
1051
1052static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1053 { .name = "mmu_cache", .rst_shift = 1 },
1054};
1055
1056static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1057 { .name = "dsp", .rst_shift = 0 },
1058};
1059
1060/* dsp -> iva */
1061static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1062 .master = &omap44xx_dsp_hwmod,
1063 .slave = &omap44xx_iva_hwmod,
1064 .clk = "dpll_iva_m5x2_ck",
1065};
1066
1067/* dsp master ports */
1068static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1069 &omap44xx_dsp__l3_main_1,
1070 &omap44xx_dsp__l4_abe,
1071 &omap44xx_dsp__iva,
1072};
1073
1074/* l4_cfg -> dsp */
1075static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1076 .master = &omap44xx_l4_cfg_hwmod,
1077 .slave = &omap44xx_dsp_hwmod,
1078 .clk = "l4_div_ck",
1079 .user = OCP_USER_MPU | OCP_USER_SDMA,
1080};
1081
1082/* dsp slave ports */
1083static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1084 &omap44xx_l4_cfg__dsp,
1085};
1086
1087/* Pseudo hwmod for reset control purpose only */
1088static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1089 .name = "dsp_c0",
1090 .class = &omap44xx_dsp_hwmod_class,
a5322c6f 1091 .clkdm_name = "tesla_clkdm",
8f25bdc5
BC		 1092 .flags = HWMOD_INIT_NO_RESET,
1093 .rst_lines = omap44xx_dsp_c0_resets,
1094 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1095 .prcm = {
1096 .omap4 = {
1097 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1098 },
1099 },
1100 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1101};
1102
1103static struct omap_hwmod omap44xx_dsp_hwmod = {
1104 .name = "dsp",
1105 .class = &omap44xx_dsp_hwmod_class,
a5322c6f 1106 .clkdm_name = "tesla_clkdm",
8f25bdc5 1107 .mpu_irqs = omap44xx_dsp_irqs,
8f25bdc5
BC		 1108 .rst_lines = omap44xx_dsp_resets,
1109 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1110 .main_clk = "dsp_fck",
1111 .prcm = {
1112 .omap4 = {
1113 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1114 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1115 },
1116 },
1117 .slaves = omap44xx_dsp_slaves,
1118 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1119 .masters = omap44xx_dsp_masters,
1120 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1121 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1122};
1123
d63bd74f
BC		 1124/*
1125 * 'dss' class
1126 * display sub-system
1127 */
1128
1129static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1130 .rev_offs = 0x0000,
1131 .syss_offs = 0x0014,
1132 .sysc_flags = SYSS_HAS_RESET_STATUS,
1133};
1134
1135static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1136 .name = "dss",
1137 .sysc = &omap44xx_dss_sysc,
1138};
1139
1140/* dss */
1141/* dss master ports */
1142static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1143 &omap44xx_dss__l3_main_1,
1144};
1145
1146static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1147 {
1148 .pa_start = 0x58000000,
1149 .pa_end = 0x5800007f,
1150 .flags = ADDR_TYPE_RT
1151 },
78183f3f 1152 { }
d63bd74f
BC		 1153};
1154
1155/* l3_main_2 -> dss */
1156static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1157 .master = &omap44xx_l3_main_2_hwmod,
1158 .slave = &omap44xx_dss_hwmod,
da7cdfac 1159 .clk = "dss_fck",
d63bd74f 1160 .addr = omap44xx_dss_dma_addrs,
d63bd74f
BC		 1161 .user = OCP_USER_SDMA,
1162};
1163
1164static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1165 {
1166 .pa_start = 0x48040000,
1167 .pa_end = 0x4804007f,
1168 .flags = ADDR_TYPE_RT
1169 },
78183f3f 1170 { }
d63bd74f
BC		 1171};
1172
1173/* l4_per -> dss */
1174static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1175 .master = &omap44xx_l4_per_hwmod,
1176 .slave = &omap44xx_dss_hwmod,
1177 .clk = "l4_div_ck",
1178 .addr = omap44xx_dss_addrs,
d63bd74f
BC		 1179 .user = OCP_USER_MPU,
1180};
1181
1182/* dss slave ports */
1183static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1184 &omap44xx_l3_main_2__dss,
1185 &omap44xx_l4_per__dss,
1186};
1187
1188static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1189 { .role = "sys_clk", .clk = "dss_sys_clk" },
1190 { .role = "tv_clk", .clk = "dss_tv_clk" },
1191 { .role = "dss_clk", .clk = "dss_dss_clk" },
1192 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1193};
1194
1195static struct omap_hwmod omap44xx_dss_hwmod = {
1196 .name = "dss_core",
1197 .class = &omap44xx_dss_hwmod_class,
a5322c6f 1198 .clkdm_name = "l3_dss_clkdm",
da7cdfac 1199 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1200 .prcm = {
1201 .omap4 = {
1202 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1203 },
1204 },
1205 .opt_clks = dss_opt_clks,
1206 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1207 .slaves = omap44xx_dss_slaves,
1208 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1209 .masters = omap44xx_dss_masters,
1210 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1211 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1212};
1213
1214/*
1215 * 'dispc' class
1216 * display controller
1217 */
1218
1219static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1220 .rev_offs = 0x0000,
1221 .sysc_offs = 0x0010,
1222 .syss_offs = 0x0014,
1223 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1224 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1225 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1226 SYSS_HAS_RESET_STATUS),
1227 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1228 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1229 .sysc_fields = &omap_hwmod_sysc_type1,
1230};
1231
1232static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1233 .name = "dispc",
1234 .sysc = &omap44xx_dispc_sysc,
1235};
1236
1237/* dss_dispc */
1238static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1239static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1240 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
212738a4 1241 { .irq = -1 }
d63bd74f
BC		 1242};
1243
1244static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1245 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
bc614958 1246 { .dma_req = -1 }
d63bd74f
BC		 1247};
1248
1249static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1250 {
1251 .pa_start = 0x58001000,
1252 .pa_end = 0x58001fff,
1253 .flags = ADDR_TYPE_RT
1254 },
78183f3f 1255 { }
d63bd74f
BC		 1256};
1257
1258/* l3_main_2 -> dss_dispc */
1259static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1260 .master = &omap44xx_l3_main_2_hwmod,
1261 .slave = &omap44xx_dss_dispc_hwmod,
da7cdfac 1262 .clk = "dss_fck",
d63bd74f 1263 .addr = omap44xx_dss_dispc_dma_addrs,
d63bd74f
BC		 1264 .user = OCP_USER_SDMA,
1265};
1266
1267static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1268 {
1269 .pa_start = 0x48041000,
1270 .pa_end = 0x48041fff,
1271 .flags = ADDR_TYPE_RT
1272 },
78183f3f 1273 { }
d63bd74f
BC		 1274};
1275
1276/* l4_per -> dss_dispc */
1277static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1278 .master = &omap44xx_l4_per_hwmod,
1279 .slave = &omap44xx_dss_dispc_hwmod,
1280 .clk = "l4_div_ck",
1281 .addr = omap44xx_dss_dispc_addrs,
d63bd74f
BC		 1282 .user = OCP_USER_MPU,
1283};
1284
1285/* dss_dispc slave ports */
1286static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1287 &omap44xx_l3_main_2__dss_dispc,
1288 &omap44xx_l4_per__dss_dispc,
1289};
1290
3a23aafc
TV		 1291static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1292 { .role = "sys_clk", .clk = "dss_sys_clk" },
1293 { .role = "tv_clk", .clk = "dss_tv_clk" },
1294 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1295};
1296
d63bd74f
BC		 1297static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1298 .name = "dss_dispc",
1299 .class = &omap44xx_dispc_hwmod_class,
a5322c6f 1300 .clkdm_name = "l3_dss_clkdm",
d63bd74f 1301 .mpu_irqs = omap44xx_dss_dispc_irqs,
d63bd74f 1302 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
da7cdfac 1303 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1304 .prcm = {
1305 .omap4 = {
1306 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1307 },
1308 },
3a23aafc
TV		 1309 .opt_clks = dss_dispc_opt_clks,
1310 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
d63bd74f
BC		 1311 .slaves = omap44xx_dss_dispc_slaves,
1312 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1313 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1314};
1315
1316/*
1317 * 'dsi' class
1318 * display serial interface controller
1319 */
1320
1321static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1322 .rev_offs = 0x0000,
1323 .sysc_offs = 0x0010,
1324 .syss_offs = 0x0014,
1325 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1326 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1327 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1328 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1329 .sysc_fields = &omap_hwmod_sysc_type1,
1330};
1331
1332static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1333 .name = "dsi",
1334 .sysc = &omap44xx_dsi_sysc,
1335};
1336
1337/* dss_dsi1 */
1338static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1339static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1340 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
212738a4 1341 { .irq = -1 }
d63bd74f
BC		 1342};
1343
1344static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1345 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
bc614958 1346 { .dma_req = -1 }
d63bd74f
BC		 1347};
1348
1349static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1350 {
1351 .pa_start = 0x58004000,
1352 .pa_end = 0x580041ff,
1353 .flags = ADDR_TYPE_RT
1354 },
78183f3f 1355 { }
d63bd74f
BC		 1356};
1357
1358/* l3_main_2 -> dss_dsi1 */
1359static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1360 .master = &omap44xx_l3_main_2_hwmod,
1361 .slave = &omap44xx_dss_dsi1_hwmod,
da7cdfac 1362 .clk = "dss_fck",
d63bd74f 1363 .addr = omap44xx_dss_dsi1_dma_addrs,
d63bd74f
BC		 1364 .user = OCP_USER_SDMA,
1365};
1366
1367static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1368 {
1369 .pa_start = 0x48044000,
1370 .pa_end = 0x480441ff,
1371 .flags = ADDR_TYPE_RT
1372 },
78183f3f 1373 { }
d63bd74f
BC		 1374};
1375
1376/* l4_per -> dss_dsi1 */
1377static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1378 .master = &omap44xx_l4_per_hwmod,
1379 .slave = &omap44xx_dss_dsi1_hwmod,
1380 .clk = "l4_div_ck",
1381 .addr = omap44xx_dss_dsi1_addrs,
d63bd74f
BC		 1382 .user = OCP_USER_MPU,
1383};
1384
1385/* dss_dsi1 slave ports */
1386static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1387 &omap44xx_l3_main_2__dss_dsi1,
1388 &omap44xx_l4_per__dss_dsi1,
1389};
1390
3a23aafc
TV		 1391static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1392 { .role = "sys_clk", .clk = "dss_sys_clk" },
1393};
1394
d63bd74f
BC		 1395static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1396 .name = "dss_dsi1",
1397 .class = &omap44xx_dsi_hwmod_class,
a5322c6f 1398 .clkdm_name = "l3_dss_clkdm",
d63bd74f 1399 .mpu_irqs = omap44xx_dss_dsi1_irqs,
d63bd74f 1400 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
da7cdfac 1401 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1402 .prcm = {
1403 .omap4 = {
1404 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1405 },
1406 },
3a23aafc
TV		 1407 .opt_clks = dss_dsi1_opt_clks,
1408 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
d63bd74f
BC		 1409 .slaves = omap44xx_dss_dsi1_slaves,
1410 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1411 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1412};
1413
1414/* dss_dsi2 */
1415static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1416static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1417 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
212738a4 1418 { .irq = -1 }
d63bd74f
BC		 1419};
1420
1421static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1422 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
bc614958 1423 { .dma_req = -1 }
d63bd74f
BC		 1424};
1425
1426static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1427 {
1428 .pa_start = 0x58005000,
1429 .pa_end = 0x580051ff,
1430 .flags = ADDR_TYPE_RT
1431 },
78183f3f 1432 { }
d63bd74f
BC		 1433};
1434
1435/* l3_main_2 -> dss_dsi2 */
1436static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1437 .master = &omap44xx_l3_main_2_hwmod,
1438 .slave = &omap44xx_dss_dsi2_hwmod,
da7cdfac 1439 .clk = "dss_fck",
d63bd74f 1440 .addr = omap44xx_dss_dsi2_dma_addrs,
d63bd74f
BC		 1441 .user = OCP_USER_SDMA,
1442};
1443
1444static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1445 {
1446 .pa_start = 0x48045000,
1447 .pa_end = 0x480451ff,
1448 .flags = ADDR_TYPE_RT
1449 },
78183f3f 1450 { }
d63bd74f
BC		 1451};
1452
1453/* l4_per -> dss_dsi2 */
1454static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1455 .master = &omap44xx_l4_per_hwmod,
1456 .slave = &omap44xx_dss_dsi2_hwmod,
1457 .clk = "l4_div_ck",
1458 .addr = omap44xx_dss_dsi2_addrs,
d63bd74f
BC		 1459 .user = OCP_USER_MPU,
1460};
1461
1462/* dss_dsi2 slave ports */
1463static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1464 &omap44xx_l3_main_2__dss_dsi2,
1465 &omap44xx_l4_per__dss_dsi2,
1466};
1467
3a23aafc
TV		 1468static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1469 { .role = "sys_clk", .clk = "dss_sys_clk" },
1470};
1471
d63bd74f
BC		 1472static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1473 .name = "dss_dsi2",
1474 .class = &omap44xx_dsi_hwmod_class,
a5322c6f 1475 .clkdm_name = "l3_dss_clkdm",
d63bd74f 1476 .mpu_irqs = omap44xx_dss_dsi2_irqs,
d63bd74f 1477 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
da7cdfac 1478 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1479 .prcm = {
1480 .omap4 = {
1481 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1482 },
1483 },
3a23aafc
TV		 1484 .opt_clks = dss_dsi2_opt_clks,
1485 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
d63bd74f
BC		 1486 .slaves = omap44xx_dss_dsi2_slaves,
1487 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1488 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1489};
1490
1491/*
1492 * 'hdmi' class
1493 * hdmi controller
1494 */
1495
1496static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1497 .rev_offs = 0x0000,
1498 .sysc_offs = 0x0010,
1499 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1500 SYSC_HAS_SOFTRESET),
1501 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1502 SIDLE_SMART_WKUP),
1503 .sysc_fields = &omap_hwmod_sysc_type2,
1504};
1505
1506static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1507 .name = "hdmi",
1508 .sysc = &omap44xx_hdmi_sysc,
1509};
1510
1511/* dss_hdmi */
1512static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1513static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1514 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
212738a4 1515 { .irq = -1 }
d63bd74f
BC		 1516};
1517
1518static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1519 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
bc614958 1520 { .dma_req = -1 }
d63bd74f
BC		 1521};
1522
1523static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1524 {
1525 .pa_start = 0x58006000,
1526 .pa_end = 0x58006fff,
1527 .flags = ADDR_TYPE_RT
1528 },
78183f3f 1529 { }
d63bd74f
BC		 1530};
1531
1532/* l3_main_2 -> dss_hdmi */
1533static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1534 .master = &omap44xx_l3_main_2_hwmod,
1535 .slave = &omap44xx_dss_hdmi_hwmod,
da7cdfac 1536 .clk = "dss_fck",
d63bd74f 1537 .addr = omap44xx_dss_hdmi_dma_addrs,
d63bd74f
BC		 1538 .user = OCP_USER_SDMA,
1539};
1540
1541static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1542 {
1543 .pa_start = 0x48046000,
1544 .pa_end = 0x48046fff,
1545 .flags = ADDR_TYPE_RT
1546 },
78183f3f 1547 { }
d63bd74f
BC		 1548};
1549
1550/* l4_per -> dss_hdmi */
1551static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1552 .master = &omap44xx_l4_per_hwmod,
1553 .slave = &omap44xx_dss_hdmi_hwmod,
1554 .clk = "l4_div_ck",
1555 .addr = omap44xx_dss_hdmi_addrs,
d63bd74f
BC		 1556 .user = OCP_USER_MPU,
1557};
1558
1559/* dss_hdmi slave ports */
1560static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1561 &omap44xx_l3_main_2__dss_hdmi,
1562 &omap44xx_l4_per__dss_hdmi,
1563};
1564
3a23aafc
TV		 1565static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1566 { .role = "sys_clk", .clk = "dss_sys_clk" },
1567};
1568
d63bd74f
BC		 1569static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1570 .name = "dss_hdmi",
1571 .class = &omap44xx_hdmi_hwmod_class,
a5322c6f 1572 .clkdm_name = "l3_dss_clkdm",
d63bd74f 1573 .mpu_irqs = omap44xx_dss_hdmi_irqs,
d63bd74f 1574 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
da7cdfac 1575 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1576 .prcm = {
1577 .omap4 = {
1578 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1579 },
1580 },
3a23aafc
TV		 1581 .opt_clks = dss_hdmi_opt_clks,
1582 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
d63bd74f
BC		 1583 .slaves = omap44xx_dss_hdmi_slaves,
1584 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1585 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1586};
1587
1588/*
1589 * 'rfbi' class
1590 * remote frame buffer interface
1591 */
1592
1593static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1594 .rev_offs = 0x0000,
1595 .sysc_offs = 0x0010,
1596 .syss_offs = 0x0014,
1597 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1598 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1599 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1600 .sysc_fields = &omap_hwmod_sysc_type1,
1601};
1602
1603static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1604 .name = "rfbi",
1605 .sysc = &omap44xx_rfbi_sysc,
1606};
1607
1608/* dss_rfbi */
1609static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1610static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1611 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
bc614958 1612 { .dma_req = -1 }
d63bd74f
BC		 1613};
1614
1615static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1616 {
1617 .pa_start = 0x58002000,
1618 .pa_end = 0x580020ff,
1619 .flags = ADDR_TYPE_RT
1620 },
78183f3f 1621 { }
d63bd74f
BC		 1622};
1623
1624/* l3_main_2 -> dss_rfbi */
1625static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1626 .master = &omap44xx_l3_main_2_hwmod,
1627 .slave = &omap44xx_dss_rfbi_hwmod,
da7cdfac 1628 .clk = "dss_fck",
d63bd74f 1629 .addr = omap44xx_dss_rfbi_dma_addrs,
d63bd74f
BC		 1630 .user = OCP_USER_SDMA,
1631};
1632
1633static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1634 {
1635 .pa_start = 0x48042000,
1636 .pa_end = 0x480420ff,
1637 .flags = ADDR_TYPE_RT
1638 },
78183f3f 1639 { }
d63bd74f
BC		 1640};
1641
1642/* l4_per -> dss_rfbi */
1643static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1644 .master = &omap44xx_l4_per_hwmod,
1645 .slave = &omap44xx_dss_rfbi_hwmod,
1646 .clk = "l4_div_ck",
1647 .addr = omap44xx_dss_rfbi_addrs,
d63bd74f
BC		 1648 .user = OCP_USER_MPU,
1649};
1650
1651/* dss_rfbi slave ports */
1652static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1653 &omap44xx_l3_main_2__dss_rfbi,
1654 &omap44xx_l4_per__dss_rfbi,
1655};
1656
3a23aafc
TV		 1657static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1658 { .role = "ick", .clk = "dss_fck" },
1659};
1660
d63bd74f
BC		 1661static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1662 .name = "dss_rfbi",
1663 .class = &omap44xx_rfbi_hwmod_class,
a5322c6f 1664 .clkdm_name = "l3_dss_clkdm",
d63bd74f 1665 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
da7cdfac 1666 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1667 .prcm = {
1668 .omap4 = {
1669 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1670 },
1671 },
3a23aafc
TV		 1672 .opt_clks = dss_rfbi_opt_clks,
1673 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
d63bd74f
BC		 1674 .slaves = omap44xx_dss_rfbi_slaves,
1675 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1676 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1677};
1678
1679/*
1680 * 'venc' class
1681 * video encoder
1682 */
1683
1684static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1685 .name = "venc",
1686};
1687
1688/* dss_venc */
1689static struct omap_hwmod omap44xx_dss_venc_hwmod;
1690static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1691 {
1692 .pa_start = 0x58003000,
1693 .pa_end = 0x580030ff,
1694 .flags = ADDR_TYPE_RT
1695 },
78183f3f 1696 { }
d63bd74f
BC		 1697};
1698
1699/* l3_main_2 -> dss_venc */
1700static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1701 .master = &omap44xx_l3_main_2_hwmod,
1702 .slave = &omap44xx_dss_venc_hwmod,
da7cdfac 1703 .clk = "dss_fck",
d63bd74f 1704 .addr = omap44xx_dss_venc_dma_addrs,
d63bd74f
BC		 1705 .user = OCP_USER_SDMA,
1706};
1707
1708static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1709 {
1710 .pa_start = 0x48043000,
1711 .pa_end = 0x480430ff,
1712 .flags = ADDR_TYPE_RT
1713 },
78183f3f 1714 { }
d63bd74f
BC		 1715};
1716
1717/* l4_per -> dss_venc */
1718static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1719 .master = &omap44xx_l4_per_hwmod,
1720 .slave = &omap44xx_dss_venc_hwmod,
1721 .clk = "l4_div_ck",
1722 .addr = omap44xx_dss_venc_addrs,
d63bd74f
BC		 1723 .user = OCP_USER_MPU,
1724};
1725
1726/* dss_venc slave ports */
1727static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1728 &omap44xx_l3_main_2__dss_venc,
1729 &omap44xx_l4_per__dss_venc,
1730};
1731
1732static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1733 .name = "dss_venc",
1734 .class = &omap44xx_venc_hwmod_class,
a5322c6f 1735 .clkdm_name = "l3_dss_clkdm",
da7cdfac 1736 .main_clk = "dss_dss_clk",
d63bd74f
BC		 1737 .prcm = {
1738 .omap4 = {
1739 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1740 },
1741 },
1742 .slaves = omap44xx_dss_venc_slaves,
1743 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1744 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1745};
1746
3b54baad
BC		 1747/*
1748 * 'gpio' class
1749 * general purpose io module
1750 */
1751
1752static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1753 .rev_offs = 0x0000,
f776471f 1754 .sysc_offs = 0x0010,
3b54baad 1755 .syss_offs = 0x0114,
0cfe8751
BC		 1756 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1757 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1758 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 1759 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1760 SIDLE_SMART_WKUP),
f776471f
BC		 1761 .sysc_fields = &omap_hwmod_sysc_type1,
1762};
1763
3b54baad 1764static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
fe13471c
BC		 1765 .name = "gpio",
1766 .sysc = &omap44xx_gpio_sysc,
1767 .rev = 2,
f776471f
BC		 1768};
1769
3b54baad
BC		 1770/* gpio dev_attr */
1771static struct omap_gpio_dev_attr gpio_dev_attr = {
fe13471c
BC		 1772 .bank_width = 32,
1773 .dbck_flag = true,
f776471f
BC		 1774};
1775
3b54baad
BC		 1776/* gpio1 */
1777static struct omap_hwmod omap44xx_gpio1_hwmod;
1778static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1779 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
212738a4 1780 { .irq = -1 }
f776471f
BC		 1781};
1782
3b54baad 1783static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
f776471f 1784 {
3b54baad
BC		 1785 .pa_start = 0x4a310000,
1786 .pa_end = 0x4a3101ff,
f776471f
BC		 1787 .flags = ADDR_TYPE_RT
1788 },
78183f3f 1789 { }
f776471f
BC		 1790};
1791
3b54baad
BC		 1792/* l4_wkup -> gpio1 */
1793static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1794 .master = &omap44xx_l4_wkup_hwmod,
1795 .slave = &omap44xx_gpio1_hwmod,
b399bca8 1796 .clk = "l4_wkup_clk_mux_ck",
3b54baad 1797 .addr = omap44xx_gpio1_addrs,
f776471f
BC		 1798 .user = OCP_USER_MPU | OCP_USER_SDMA,
1799};
1800
3b54baad
BC		 1801/* gpio1 slave ports */
1802static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1803 &omap44xx_l4_wkup__gpio1,
f776471f
BC		 1804};
1805
3b54baad 1806static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
b399bca8 1807 { .role = "dbclk", .clk = "gpio1_dbclk" },
3b54baad
BC		 1808};
1809
1810static struct omap_hwmod omap44xx_gpio1_hwmod = {
1811 .name = "gpio1",
1812 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 1813 .clkdm_name = "l4_wkup_clkdm",
3b54baad 1814 .mpu_irqs = omap44xx_gpio1_irqs,
3b54baad 1815 .main_clk = "gpio1_ick",
f776471f
BC		 1816 .prcm = {
1817 .omap4 = {
3b54baad 1818 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
f776471f
BC		 1819 },
1820 },
3b54baad
BC		 1821 .opt_clks = gpio1_opt_clks,
1822 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1823 .dev_attr = &gpio_dev_attr,
1824 .slaves = omap44xx_gpio1_slaves,
1825 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
f776471f
BC		 1826 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1827};
1828
3b54baad
BC		 1829/* gpio2 */
1830static struct omap_hwmod omap44xx_gpio2_hwmod;
1831static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1832 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
212738a4 1833 { .irq = -1 }
f776471f
BC		 1834};
1835
3b54baad 1836static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
f776471f 1837 {
3b54baad
BC		 1838 .pa_start = 0x48055000,
1839 .pa_end = 0x480551ff,
f776471f
BC		 1840 .flags = ADDR_TYPE_RT
1841 },
78183f3f 1842 { }
f776471f
BC		 1843};
1844
3b54baad
BC		 1845/* l4_per -> gpio2 */
1846static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
f776471f 1847 .master = &omap44xx_l4_per_hwmod,
3b54baad 1848 .slave = &omap44xx_gpio2_hwmod,
b399bca8 1849 .clk = "l4_div_ck",
3b54baad 1850 .addr = omap44xx_gpio2_addrs,
f776471f
BC		 1851 .user = OCP_USER_MPU | OCP_USER_SDMA,
1852};
1853
3b54baad
BC		 1854/* gpio2 slave ports */
1855static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1856 &omap44xx_l4_per__gpio2,
f776471f
BC		 1857};
1858
3b54baad 1859static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
b399bca8 1860 { .role = "dbclk", .clk = "gpio2_dbclk" },
3b54baad
BC		 1861};
1862
1863static struct omap_hwmod omap44xx_gpio2_hwmod = {
1864 .name = "gpio2",
1865 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 1866 .clkdm_name = "l4_per_clkdm",
b399bca8 1867 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1868 .mpu_irqs = omap44xx_gpio2_irqs,
3b54baad 1869 .main_clk = "gpio2_ick",
f776471f
BC		 1870 .prcm = {
1871 .omap4 = {
3b54baad 1872 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
f776471f
BC		 1873 },
1874 },
3b54baad
BC		 1875 .opt_clks = gpio2_opt_clks,
1876 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1877 .dev_attr = &gpio_dev_attr,
1878 .slaves = omap44xx_gpio2_slaves,
1879 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
f776471f
BC		 1880 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1881};
1882
3b54baad
BC		 1883/* gpio3 */
1884static struct omap_hwmod omap44xx_gpio3_hwmod;
1885static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1886 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
212738a4 1887 { .irq = -1 }
f776471f
BC		 1888};
1889
3b54baad 1890static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
f776471f 1891 {
3b54baad
BC		 1892 .pa_start = 0x48057000,
1893 .pa_end = 0x480571ff,
f776471f
BC		 1894 .flags = ADDR_TYPE_RT
1895 },
78183f3f 1896 { }
f776471f
BC		 1897};
1898
3b54baad
BC		 1899/* l4_per -> gpio3 */
1900static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
f776471f 1901 .master = &omap44xx_l4_per_hwmod,
3b54baad 1902 .slave = &omap44xx_gpio3_hwmod,
b399bca8 1903 .clk = "l4_div_ck",
3b54baad 1904 .addr = omap44xx_gpio3_addrs,
f776471f
BC		 1905 .user = OCP_USER_MPU | OCP_USER_SDMA,
1906};
1907
3b54baad
BC		 1908/* gpio3 slave ports */
1909static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1910 &omap44xx_l4_per__gpio3,
f776471f
BC		 1911};
1912
3b54baad 1913static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
b399bca8 1914 { .role = "dbclk", .clk = "gpio3_dbclk" },
3b54baad
BC		 1915};
1916
1917static struct omap_hwmod omap44xx_gpio3_hwmod = {
1918 .name = "gpio3",
1919 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 1920 .clkdm_name = "l4_per_clkdm",
b399bca8 1921 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1922 .mpu_irqs = omap44xx_gpio3_irqs,
3b54baad 1923 .main_clk = "gpio3_ick",
f776471f
BC		 1924 .prcm = {
1925 .omap4 = {
3b54baad 1926 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
f776471f
BC		 1927 },
1928 },
3b54baad
BC		 1929 .opt_clks = gpio3_opt_clks,
1930 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1931 .dev_attr = &gpio_dev_attr,
1932 .slaves = omap44xx_gpio3_slaves,
1933 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
f776471f
BC		 1934 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1935};
1936
3b54baad
BC		 1937/* gpio4 */
1938static struct omap_hwmod omap44xx_gpio4_hwmod;
1939static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1940 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
212738a4 1941 { .irq = -1 }
f776471f
BC		 1942};
1943
3b54baad 1944static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
f776471f 1945 {
3b54baad
BC		 1946 .pa_start = 0x48059000,
1947 .pa_end = 0x480591ff,
f776471f
BC		 1948 .flags = ADDR_TYPE_RT
1949 },
78183f3f 1950 { }
f776471f
BC		 1951};
1952
3b54baad
BC		 1953/* l4_per -> gpio4 */
1954static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
f776471f 1955 .master = &omap44xx_l4_per_hwmod,
3b54baad 1956 .slave = &omap44xx_gpio4_hwmod,
b399bca8 1957 .clk = "l4_div_ck",
3b54baad 1958 .addr = omap44xx_gpio4_addrs,
f776471f
BC		 1959 .user = OCP_USER_MPU | OCP_USER_SDMA,
1960};
1961
3b54baad
BC		 1962/* gpio4 slave ports */
1963static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1964 &omap44xx_l4_per__gpio4,
f776471f
BC		 1965};
1966
3b54baad 1967static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
b399bca8 1968 { .role = "dbclk", .clk = "gpio4_dbclk" },
3b54baad
BC		 1969};
1970
1971static struct omap_hwmod omap44xx_gpio4_hwmod = {
1972 .name = "gpio4",
1973 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 1974 .clkdm_name = "l4_per_clkdm",
b399bca8 1975 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 1976 .mpu_irqs = omap44xx_gpio4_irqs,
3b54baad 1977 .main_clk = "gpio4_ick",
f776471f
BC		 1978 .prcm = {
1979 .omap4 = {
3b54baad 1980 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
f776471f
BC		 1981 },
1982 },
3b54baad
BC		 1983 .opt_clks = gpio4_opt_clks,
1984 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1985 .dev_attr = &gpio_dev_attr,
1986 .slaves = omap44xx_gpio4_slaves,
1987 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
f776471f
BC		 1988 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1989};
1990
3b54baad
BC		 1991/* gpio5 */
1992static struct omap_hwmod omap44xx_gpio5_hwmod;
1993static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1994 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
212738a4 1995 { .irq = -1 }
55d2cb08
BC		 1996};
1997
3b54baad
BC		 1998static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1999 {
2000 .pa_start = 0x4805b000,
2001 .pa_end = 0x4805b1ff,
2002 .flags = ADDR_TYPE_RT
2003 },
78183f3f 2004 { }
55d2cb08
BC		 2005};
2006
3b54baad
BC		 2007/* l4_per -> gpio5 */
2008static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2009 .master = &omap44xx_l4_per_hwmod,
2010 .slave = &omap44xx_gpio5_hwmod,
b399bca8 2011 .clk = "l4_div_ck",
3b54baad 2012 .addr = omap44xx_gpio5_addrs,
3b54baad 2013 .user = OCP_USER_MPU | OCP_USER_SDMA,
55d2cb08
BC		 2014};
2015
3b54baad
BC		 2016/* gpio5 slave ports */
2017static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2018 &omap44xx_l4_per__gpio5,
55d2cb08
BC		 2019};
2020
3b54baad 2021static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
b399bca8 2022 { .role = "dbclk", .clk = "gpio5_dbclk" },
55d2cb08
BC		 2023};
2024
3b54baad
BC		 2025static struct omap_hwmod omap44xx_gpio5_hwmod = {
2026 .name = "gpio5",
2027 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 2028 .clkdm_name = "l4_per_clkdm",
b399bca8 2029 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 2030 .mpu_irqs = omap44xx_gpio5_irqs,
3b54baad 2031 .main_clk = "gpio5_ick",
55d2cb08
BC		 2032 .prcm = {
2033 .omap4 = {
3b54baad 2034 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
55d2cb08
BC		 2035 },
2036 },
3b54baad
BC		 2037 .opt_clks = gpio5_opt_clks,
2038 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2039 .dev_attr = &gpio_dev_attr,
2040 .slaves = omap44xx_gpio5_slaves,
2041 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
55d2cb08
BC		 2042 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2043};
2044
3b54baad
BC		 2045/* gpio6 */
2046static struct omap_hwmod omap44xx_gpio6_hwmod;
2047static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2048 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
212738a4 2049 { .irq = -1 }
92b18d1c
BC		 2050};
2051
3b54baad 2052static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
92b18d1c 2053 {
3b54baad
BC		 2054 .pa_start = 0x4805d000,
2055 .pa_end = 0x4805d1ff,
92b18d1c
BC		 2056 .flags = ADDR_TYPE_RT
2057 },
78183f3f 2058 { }
92b18d1c
BC		 2059};
2060
3b54baad
BC		 2061/* l4_per -> gpio6 */
2062static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2063 .master = &omap44xx_l4_per_hwmod,
2064 .slave = &omap44xx_gpio6_hwmod,
b399bca8 2065 .clk = "l4_div_ck",
3b54baad 2066 .addr = omap44xx_gpio6_addrs,
3b54baad 2067 .user = OCP_USER_MPU | OCP_USER_SDMA,
db12ba53
BC		 2068};
2069
3b54baad
BC		 2070/* gpio6 slave ports */
2071static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2072 &omap44xx_l4_per__gpio6,
db12ba53
BC		 2073};
2074
3b54baad 2075static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
b399bca8 2076 { .role = "dbclk", .clk = "gpio6_dbclk" },
db12ba53
BC		 2077};
2078
3b54baad
BC		 2079static struct omap_hwmod omap44xx_gpio6_hwmod = {
2080 .name = "gpio6",
2081 .class = &omap44xx_gpio_hwmod_class,
a5322c6f 2082 .clkdm_name = "l4_per_clkdm",
b399bca8 2083 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad 2084 .mpu_irqs = omap44xx_gpio6_irqs,
3b54baad
BC		 2085 .main_clk = "gpio6_ick",
2086 .prcm = {
2087 .omap4 = {
2088 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2089 },
db12ba53 2090 },
3b54baad
BC		 2091 .opt_clks = gpio6_opt_clks,
2092 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2093 .dev_attr = &gpio_dev_attr,
2094 .slaves = omap44xx_gpio6_slaves,
2095 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2096 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
db12ba53
BC		 2097};
2098
407a6888
BC		 2099/*
2100 * 'hsi' class
2101 * mipi high-speed synchronous serial interface (multichannel and full-duplex
2102 * serial if)
2103 */
2104
2105static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2106 .rev_offs = 0x0000,
2107 .sysc_offs = 0x0010,
2108 .syss_offs = 0x0014,
2109 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2110 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2111 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2112 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2113 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 2114 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 2115 .sysc_fields = &omap_hwmod_sysc_type1,
2116};
2117
2118static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2119 .name = "hsi",
2120 .sysc = &omap44xx_hsi_sysc,
2121};
2122
2123/* hsi */
2124static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2125 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2126 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2127 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
212738a4 2128 { .irq = -1 }
407a6888
BC		 2129};
2130
2131/* hsi master ports */
2132static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2133 &omap44xx_hsi__l3_main_2,
2134};
2135
2136static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2137 {
2138 .pa_start = 0x4a058000,
2139 .pa_end = 0x4a05bfff,
2140 .flags = ADDR_TYPE_RT
2141 },
78183f3f 2142 { }
407a6888
BC		 2143};
2144
2145/* l4_cfg -> hsi */
2146static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2147 .master = &omap44xx_l4_cfg_hwmod,
2148 .slave = &omap44xx_hsi_hwmod,
2149 .clk = "l4_div_ck",
2150 .addr = omap44xx_hsi_addrs,
407a6888
BC		 2151 .user = OCP_USER_MPU | OCP_USER_SDMA,
2152};
2153
2154/* hsi slave ports */
2155static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2156 &omap44xx_l4_cfg__hsi,
2157};
2158
2159static struct omap_hwmod omap44xx_hsi_hwmod = {
2160 .name = "hsi",
2161 .class = &omap44xx_hsi_hwmod_class,
a5322c6f 2162 .clkdm_name = "l3_init_clkdm",
407a6888 2163 .mpu_irqs = omap44xx_hsi_irqs,
407a6888 2164 .main_clk = "hsi_fck",
00fe610b 2165 .prcm = {
407a6888
BC		 2166 .omap4 = {
2167 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2168 },
2169 },
2170 .slaves = omap44xx_hsi_slaves,
2171 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2172 .masters = omap44xx_hsi_masters,
2173 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2175};
2176
3b54baad
BC		 2177/*
2178 * 'i2c' class
2179 * multimaster high-speed i2c controller
2180 */
db12ba53 2181
3b54baad
BC		 2182static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2183 .sysc_offs = 0x0010,
2184 .syss_offs = 0x0090,
2185 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2186 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
0cfe8751 2187 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 2188 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2189 SIDLE_SMART_WKUP),
3b54baad 2190 .sysc_fields = &omap_hwmod_sysc_type1,
db12ba53
BC		 2191};
2192
3b54baad 2193static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
fe13471c
BC		 2194 .name = "i2c",
2195 .sysc = &omap44xx_i2c_sysc,
db791a75 2196 .rev = OMAP_I2C_IP_VERSION_2,
6d3c55fd 2197 .reset = &omap_i2c_reset,
db12ba53
BC		 2198};
2199
4d4441a6
AG		 2200static struct omap_i2c_dev_attr i2c_dev_attr = {
2201 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2202};
2203
3b54baad
BC		 2204/* i2c1 */
2205static struct omap_hwmod omap44xx_i2c1_hwmod;
2206static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2207 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
212738a4 2208 { .irq = -1 }
db12ba53
BC		 2209};
2210
3b54baad
BC		 2211static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2212 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2213 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
bc614958 2214 { .dma_req = -1 }
db12ba53
BC		 2215};
2216
3b54baad 2217static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
db12ba53 2218 {
3b54baad
BC		 2219 .pa_start = 0x48070000,
2220 .pa_end = 0x480700ff,
db12ba53
BC		 2221 .flags = ADDR_TYPE_RT
2222 },
78183f3f 2223 { }
db12ba53
BC		 2224};
2225
3b54baad
BC		 2226/* l4_per -> i2c1 */
2227static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2228 .master = &omap44xx_l4_per_hwmod,
2229 .slave = &omap44xx_i2c1_hwmod,
2230 .clk = "l4_div_ck",
2231 .addr = omap44xx_i2c1_addrs,
92b18d1c
BC		 2232 .user = OCP_USER_MPU | OCP_USER_SDMA,
2233};
2234
3b54baad
BC		 2235/* i2c1 slave ports */
2236static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2237 &omap44xx_l4_per__i2c1,
92b18d1c
BC		 2238};
2239
3b54baad
BC		 2240static struct omap_hwmod omap44xx_i2c1_hwmod = {
2241 .name = "i2c1",
2242 .class = &omap44xx_i2c_hwmod_class,
a5322c6f 2243 .clkdm_name = "l4_per_clkdm",
6d3c55fd 2244 .flags = HWMOD_16BIT_REG,
3b54baad 2245 .mpu_irqs = omap44xx_i2c1_irqs,
3b54baad 2246 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
3b54baad 2247 .main_clk = "i2c1_fck",
92b18d1c
BC		 2248 .prcm = {
2249 .omap4 = {
3b54baad 2250 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
92b18d1c
BC		 2251 },
2252 },
3b54baad
BC		 2253 .slaves = omap44xx_i2c1_slaves,
2254 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
4d4441a6 2255 .dev_attr = &i2c_dev_attr,
92b18d1c
BC		 2256 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2257};
2258
3b54baad
BC		 2259/* i2c2 */
2260static struct omap_hwmod omap44xx_i2c2_hwmod;
2261static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2262 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
212738a4 2263 { .irq = -1 }
92b18d1c
BC		 2264};
2265
3b54baad
BC		 2266static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2267 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2268 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
bc614958 2269 { .dma_req = -1 }
3b54baad
BC		 2270};
2271
2272static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
92b18d1c 2273 {
3b54baad
BC		 2274 .pa_start = 0x48072000,
2275 .pa_end = 0x480720ff,
92b18d1c
BC		 2276 .flags = ADDR_TYPE_RT
2277 },
78183f3f 2278 { }
92b18d1c
BC		 2279};
2280
3b54baad
BC		 2281/* l4_per -> i2c2 */
2282static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
db12ba53 2283 .master = &omap44xx_l4_per_hwmod,
3b54baad 2284 .slave = &omap44xx_i2c2_hwmod,
db12ba53 2285 .clk = "l4_div_ck",
3b54baad 2286 .addr = omap44xx_i2c2_addrs,
db12ba53
BC		 2287 .user = OCP_USER_MPU | OCP_USER_SDMA,
2288};
2289
3b54baad
BC		 2290/* i2c2 slave ports */
2291static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2292 &omap44xx_l4_per__i2c2,
db12ba53
BC		 2293};
2294
3b54baad
BC		 2295static struct omap_hwmod omap44xx_i2c2_hwmod = {
2296 .name = "i2c2",
2297 .class = &omap44xx_i2c_hwmod_class,
a5322c6f 2298 .clkdm_name = "l4_per_clkdm",
6d3c55fd 2299 .flags = HWMOD_16BIT_REG,
3b54baad 2300 .mpu_irqs = omap44xx_i2c2_irqs,
3b54baad 2301 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
3b54baad 2302 .main_clk = "i2c2_fck",
db12ba53
BC		 2303 .prcm = {
2304 .omap4 = {
3b54baad 2305 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
db12ba53
BC		 2306 },
2307 },
3b54baad
BC		 2308 .slaves = omap44xx_i2c2_slaves,
2309 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
4d4441a6 2310 .dev_attr = &i2c_dev_attr,
db12ba53
BC		 2311 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2312};
2313
3b54baad
BC		 2314/* i2c3 */
2315static struct omap_hwmod omap44xx_i2c3_hwmod;
2316static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2317 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
212738a4 2318 { .irq = -1 }
db12ba53
BC		 2319};
2320
3b54baad
BC		 2321static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2322 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2323 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
bc614958 2324 { .dma_req = -1 }
92b18d1c
BC		 2325};
2326
3b54baad 2327static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
92b18d1c 2328 {
3b54baad
BC		 2329 .pa_start = 0x48060000,
2330 .pa_end = 0x480600ff,
92b18d1c
BC		 2331 .flags = ADDR_TYPE_RT
2332 },
78183f3f 2333 { }
92b18d1c
BC		 2334};
2335
3b54baad
BC		 2336/* l4_per -> i2c3 */
2337static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
db12ba53 2338 .master = &omap44xx_l4_per_hwmod,
3b54baad 2339 .slave = &omap44xx_i2c3_hwmod,
db12ba53 2340 .clk = "l4_div_ck",
3b54baad 2341 .addr = omap44xx_i2c3_addrs,
db12ba53
BC		 2342 .user = OCP_USER_MPU | OCP_USER_SDMA,
2343};
2344
3b54baad
BC		 2345/* i2c3 slave ports */
2346static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2347 &omap44xx_l4_per__i2c3,
db12ba53
BC		 2348};
2349
3b54baad
BC		 2350static struct omap_hwmod omap44xx_i2c3_hwmod = {
2351 .name = "i2c3",
2352 .class = &omap44xx_i2c_hwmod_class,
a5322c6f 2353 .clkdm_name = "l4_per_clkdm",
6d3c55fd 2354 .flags = HWMOD_16BIT_REG,
3b54baad 2355 .mpu_irqs = omap44xx_i2c3_irqs,
3b54baad 2356 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
3b54baad 2357 .main_clk = "i2c3_fck",
db12ba53
BC		 2358 .prcm = {
2359 .omap4 = {
3b54baad 2360 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
db12ba53
BC		 2361 },
2362 },
3b54baad
BC		 2363 .slaves = omap44xx_i2c3_slaves,
2364 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
4d4441a6 2365 .dev_attr = &i2c_dev_attr,
db12ba53
BC		 2366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2367};
2368
3b54baad
BC		 2369/* i2c4 */
2370static struct omap_hwmod omap44xx_i2c4_hwmod;
2371static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2372 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
212738a4 2373 { .irq = -1 }
db12ba53
BC		 2374};
2375
3b54baad
BC		 2376static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2377 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2378 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
bc614958 2379 { .dma_req = -1 }
db12ba53
BC		 2380};
2381
3b54baad 2382static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
db12ba53 2383 {
3b54baad
BC		 2384 .pa_start = 0x48350000,
2385 .pa_end = 0x483500ff,
db12ba53
BC		 2386 .flags = ADDR_TYPE_RT
2387 },
78183f3f 2388 { }
db12ba53
BC		 2389};
2390
3b54baad
BC		 2391/* l4_per -> i2c4 */
2392static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2393 .master = &omap44xx_l4_per_hwmod,
2394 .slave = &omap44xx_i2c4_hwmod,
2395 .clk = "l4_div_ck",
2396 .addr = omap44xx_i2c4_addrs,
3b54baad 2397 .user = OCP_USER_MPU | OCP_USER_SDMA,
92b18d1c
BC		 2398};
2399
3b54baad
BC		 2400/* i2c4 slave ports */
2401static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2402 &omap44xx_l4_per__i2c4,
92b18d1c
BC		 2403};
2404
3b54baad
BC		 2405static struct omap_hwmod omap44xx_i2c4_hwmod = {
2406 .name = "i2c4",
2407 .class = &omap44xx_i2c_hwmod_class,
a5322c6f 2408 .clkdm_name = "l4_per_clkdm",
6d3c55fd 2409 .flags = HWMOD_16BIT_REG,
3b54baad 2410 .mpu_irqs = omap44xx_i2c4_irqs,
3b54baad 2411 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
3b54baad 2412 .main_clk = "i2c4_fck",
92b18d1c
BC		 2413 .prcm = {
2414 .omap4 = {
3b54baad 2415 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
92b18d1c
BC		 2416 },
2417 },
3b54baad
BC		 2418 .slaves = omap44xx_i2c4_slaves,
2419 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
4d4441a6 2420 .dev_attr = &i2c_dev_attr,
92b18d1c
BC		 2421 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2422};
2423
407a6888
BC		 2424/*
2425 * 'ipu' class
2426 * imaging processor unit
2427 */
2428
2429static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2430 .name = "ipu",
2431};
2432
2433/* ipu */
2434static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2435 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
212738a4 2436 { .irq = -1 }
407a6888
BC		 2437};
2438
2439static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2440 { .name = "cpu0", .rst_shift = 0 },
2441};
2442
2443static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2444 { .name = "cpu1", .rst_shift = 1 },
2445};
2446
2447static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2448 { .name = "mmu_cache", .rst_shift = 2 },
2449};
2450
2451/* ipu master ports */
2452static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2453 &omap44xx_ipu__l3_main_2,
2454};
2455
2456/* l3_main_2 -> ipu */
2457static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2458 .master = &omap44xx_l3_main_2_hwmod,
2459 .slave = &omap44xx_ipu_hwmod,
2460 .clk = "l3_div_ck",
2461 .user = OCP_USER_MPU | OCP_USER_SDMA,
2462};
2463
2464/* ipu slave ports */
2465static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2466 &omap44xx_l3_main_2__ipu,
2467};
2468
2469/* Pseudo hwmod for reset control purpose only */
2470static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2471 .name = "ipu_c0",
2472 .class = &omap44xx_ipu_hwmod_class,
a5322c6f 2473 .clkdm_name = "ducati_clkdm",
407a6888
BC		 2474 .flags = HWMOD_INIT_NO_RESET,
2475 .rst_lines = omap44xx_ipu_c0_resets,
2476 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
00fe610b 2477 .prcm = {
407a6888
BC		 2478 .omap4 = {
2479 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2480 },
2481 },
2482 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2483};
2484
2485/* Pseudo hwmod for reset control purpose only */
2486static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2487 .name = "ipu_c1",
2488 .class = &omap44xx_ipu_hwmod_class,
a5322c6f 2489 .clkdm_name = "ducati_clkdm",
407a6888
BC		 2490 .flags = HWMOD_INIT_NO_RESET,
2491 .rst_lines = omap44xx_ipu_c1_resets,
2492 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
00fe610b 2493 .prcm = {
407a6888
BC		 2494 .omap4 = {
2495 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2496 },
2497 },
2498 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2499};
2500
2501static struct omap_hwmod omap44xx_ipu_hwmod = {
2502 .name = "ipu",
2503 .class = &omap44xx_ipu_hwmod_class,
a5322c6f 2504 .clkdm_name = "ducati_clkdm",
407a6888 2505 .mpu_irqs = omap44xx_ipu_irqs,
407a6888
BC		 2506 .rst_lines = omap44xx_ipu_resets,
2507 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2508 .main_clk = "ipu_fck",
00fe610b 2509 .prcm = {
407a6888
BC		 2510 .omap4 = {
2511 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2512 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2513 },
2514 },
2515 .slaves = omap44xx_ipu_slaves,
2516 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2517 .masters = omap44xx_ipu_masters,
2518 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2519 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2520};
2521
2522/*
2523 * 'iss' class
2524 * external images sensor pixel data processor
2525 */
2526
2527static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2528 .rev_offs = 0x0000,
2529 .sysc_offs = 0x0010,
2530 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2531 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2532 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2533 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 2534 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 2535 .sysc_fields = &omap_hwmod_sysc_type2,
2536};
2537
2538static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2539 .name = "iss",
2540 .sysc = &omap44xx_iss_sysc,
2541};
2542
2543/* iss */
2544static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2545 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
212738a4 2546 { .irq = -1 }
407a6888
BC		 2547};
2548
2549static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2550 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2551 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2552 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2553 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
bc614958 2554 { .dma_req = -1 }
407a6888
BC		 2555};
2556
2557/* iss master ports */
2558static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2559 &omap44xx_iss__l3_main_2,
2560};
2561
2562static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2563 {
2564 .pa_start = 0x52000000,
2565 .pa_end = 0x520000ff,
2566 .flags = ADDR_TYPE_RT
2567 },
78183f3f 2568 { }
407a6888
BC		 2569};
2570
2571/* l3_main_2 -> iss */
2572static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2573 .master = &omap44xx_l3_main_2_hwmod,
2574 .slave = &omap44xx_iss_hwmod,
2575 .clk = "l3_div_ck",
2576 .addr = omap44xx_iss_addrs,
407a6888
BC		 2577 .user = OCP_USER_MPU | OCP_USER_SDMA,
2578};
2579
2580/* iss slave ports */
2581static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2582 &omap44xx_l3_main_2__iss,
2583};
2584
2585static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2586 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2587};
2588
2589static struct omap_hwmod omap44xx_iss_hwmod = {
2590 .name = "iss",
2591 .class = &omap44xx_iss_hwmod_class,
a5322c6f 2592 .clkdm_name = "iss_clkdm",
407a6888 2593 .mpu_irqs = omap44xx_iss_irqs,
407a6888 2594 .sdma_reqs = omap44xx_iss_sdma_reqs,
407a6888 2595 .main_clk = "iss_fck",
00fe610b 2596 .prcm = {
407a6888
BC		 2597 .omap4 = {
2598 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2599 },
2600 },
2601 .opt_clks = iss_opt_clks,
2602 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2603 .slaves = omap44xx_iss_slaves,
2604 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2605 .masters = omap44xx_iss_masters,
2606 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2607 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2608};
2609
8f25bdc5
BC		 2610/*
2611 * 'iva' class
2612 * multi-standard video encoder/decoder hardware accelerator
2613 */
2614
2615static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
fe13471c 2616 .name = "iva",
8f25bdc5
BC		 2617};
2618
2619/* iva */
2620static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2621 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2622 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2623 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
212738a4 2624 { .irq = -1 }
8f25bdc5
BC		 2625};
2626
2627static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2628 { .name = "logic", .rst_shift = 2 },
2629};
2630
2631static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2632 { .name = "seq0", .rst_shift = 0 },
2633};
2634
2635static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2636 { .name = "seq1", .rst_shift = 1 },
2637};
2638
2639/* iva master ports */
2640static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2641 &omap44xx_iva__l3_main_2,
2642 &omap44xx_iva__l3_instr,
2643};
2644
2645static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2646 {
2647 .pa_start = 0x5a000000,
2648 .pa_end = 0x5a07ffff,
2649 .flags = ADDR_TYPE_RT
2650 },
78183f3f 2651 { }
8f25bdc5
BC		 2652};
2653
2654/* l3_main_2 -> iva */
2655static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2656 .master = &omap44xx_l3_main_2_hwmod,
2657 .slave = &omap44xx_iva_hwmod,
2658 .clk = "l3_div_ck",
2659 .addr = omap44xx_iva_addrs,
8f25bdc5
BC		 2660 .user = OCP_USER_MPU,
2661};
2662
2663/* iva slave ports */
2664static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2665 &omap44xx_dsp__iva,
2666 &omap44xx_l3_main_2__iva,
2667};
2668
2669/* Pseudo hwmod for reset control purpose only */
2670static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2671 .name = "iva_seq0",
2672 .class = &omap44xx_iva_hwmod_class,
a5322c6f 2673 .clkdm_name = "ivahd_clkdm",
8f25bdc5
BC		 2674 .flags = HWMOD_INIT_NO_RESET,
2675 .rst_lines = omap44xx_iva_seq0_resets,
2676 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2677 .prcm = {
2678 .omap4 = {
2679 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2680 },
2681 },
2682 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2683};
2684
2685/* Pseudo hwmod for reset control purpose only */
2686static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2687 .name = "iva_seq1",
2688 .class = &omap44xx_iva_hwmod_class,
a5322c6f 2689 .clkdm_name = "ivahd_clkdm",
8f25bdc5
BC		 2690 .flags = HWMOD_INIT_NO_RESET,
2691 .rst_lines = omap44xx_iva_seq1_resets,
2692 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2693 .prcm = {
2694 .omap4 = {
2695 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2696 },
2697 },
2698 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2699};
2700
2701static struct omap_hwmod omap44xx_iva_hwmod = {
2702 .name = "iva",
2703 .class = &omap44xx_iva_hwmod_class,
a5322c6f 2704 .clkdm_name = "ivahd_clkdm",
8f25bdc5 2705 .mpu_irqs = omap44xx_iva_irqs,
8f25bdc5
BC		 2706 .rst_lines = omap44xx_iva_resets,
2707 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2708 .main_clk = "iva_fck",
2709 .prcm = {
2710 .omap4 = {
2711 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2712 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2713 },
2714 },
2715 .slaves = omap44xx_iva_slaves,
2716 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2717 .masters = omap44xx_iva_masters,
2718 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2719 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2720};
2721
407a6888
BC		 2722/*
2723 * 'kbd' class
2724 * keyboard controller
2725 */
2726
2727static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2728 .rev_offs = 0x0000,
2729 .sysc_offs = 0x0010,
2730 .syss_offs = 0x0014,
2731 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2732 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2733 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2734 SYSS_HAS_RESET_STATUS),
2735 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2736 .sysc_fields = &omap_hwmod_sysc_type1,
2737};
2738
2739static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2740 .name = "kbd",
2741 .sysc = &omap44xx_kbd_sysc,
2742};
2743
2744/* kbd */
2745static struct omap_hwmod omap44xx_kbd_hwmod;
2746static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2747 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
212738a4 2748 { .irq = -1 }
407a6888
BC		 2749};
2750
2751static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2752 {
2753 .pa_start = 0x4a31c000,
2754 .pa_end = 0x4a31c07f,
2755 .flags = ADDR_TYPE_RT
2756 },
78183f3f 2757 { }
407a6888
BC		 2758};
2759
2760/* l4_wkup -> kbd */
2761static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2762 .master = &omap44xx_l4_wkup_hwmod,
2763 .slave = &omap44xx_kbd_hwmod,
2764 .clk = "l4_wkup_clk_mux_ck",
2765 .addr = omap44xx_kbd_addrs,
407a6888
BC		 2766 .user = OCP_USER_MPU | OCP_USER_SDMA,
2767};
2768
2769/* kbd slave ports */
2770static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2771 &omap44xx_l4_wkup__kbd,
2772};
2773
2774static struct omap_hwmod omap44xx_kbd_hwmod = {
2775 .name = "kbd",
2776 .class = &omap44xx_kbd_hwmod_class,
a5322c6f 2777 .clkdm_name = "l4_wkup_clkdm",
407a6888 2778 .mpu_irqs = omap44xx_kbd_irqs,
407a6888 2779 .main_clk = "kbd_fck",
00fe610b 2780 .prcm = {
407a6888
BC		 2781 .omap4 = {
2782 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2783 },
2784 },
2785 .slaves = omap44xx_kbd_slaves,
2786 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2787 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2788};
2789
ec5df927
BC		 2790/*
2791 * 'mailbox' class
2792 * mailbox module allowing communication between the on-chip processors using a
2793 * queued mailbox-interrupt mechanism.
2794 */
2795
2796static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2797 .rev_offs = 0x0000,
2798 .sysc_offs = 0x0010,
2799 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2800 SYSC_HAS_SOFTRESET),
2801 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2802 .sysc_fields = &omap_hwmod_sysc_type2,
2803};
2804
2805static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2806 .name = "mailbox",
2807 .sysc = &omap44xx_mailbox_sysc,
2808};
2809
2810/* mailbox */
2811static struct omap_hwmod omap44xx_mailbox_hwmod;
2812static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2813 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
212738a4 2814 { .irq = -1 }
ec5df927
BC		 2815};
2816
2817static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2818 {
2819 .pa_start = 0x4a0f4000,
2820 .pa_end = 0x4a0f41ff,
2821 .flags = ADDR_TYPE_RT
2822 },
78183f3f 2823 { }
ec5df927
BC		 2824};
2825
2826/* l4_cfg -> mailbox */
2827static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2828 .master = &omap44xx_l4_cfg_hwmod,
2829 .slave = &omap44xx_mailbox_hwmod,
2830 .clk = "l4_div_ck",
2831 .addr = omap44xx_mailbox_addrs,
ec5df927
BC		 2832 .user = OCP_USER_MPU | OCP_USER_SDMA,
2833};
2834
2835/* mailbox slave ports */
2836static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2837 &omap44xx_l4_cfg__mailbox,
2838};
2839
2840static struct omap_hwmod omap44xx_mailbox_hwmod = {
2841 .name = "mailbox",
2842 .class = &omap44xx_mailbox_hwmod_class,
a5322c6f 2843 .clkdm_name = "l4_cfg_clkdm",
ec5df927 2844 .mpu_irqs = omap44xx_mailbox_irqs,
00fe610b 2845 .prcm = {
ec5df927
BC		 2846 .omap4 = {
2847 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2848 },
2849 },
2850 .slaves = omap44xx_mailbox_slaves,
2851 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2852 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2853};
2854
4ddff493
BC		 2855/*
2856 * 'mcbsp' class
2857 * multi channel buffered serial port controller
2858 */
2859
2860static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2861 .sysc_offs = 0x008c,
2862 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2863 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2864 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2865 .sysc_fields = &omap_hwmod_sysc_type1,
2866};
2867
2868static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2869 .name = "mcbsp",
2870 .sysc = &omap44xx_mcbsp_sysc,
cb7e9ded 2871 .rev = MCBSP_CONFIG_TYPE4,
4ddff493
BC		 2872};
2873
2874/* mcbsp1 */
2875static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2876static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2877 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
212738a4 2878 { .irq = -1 }
4ddff493
BC		 2879};
2880
2881static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2882 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2883 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
bc614958 2884 { .dma_req = -1 }
4ddff493
BC		 2885};
2886
2887static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2888 {
cb7e9ded 2889 .name = "mpu",
4ddff493
BC		 2890 .pa_start = 0x40122000,
2891 .pa_end = 0x401220ff,
2892 .flags = ADDR_TYPE_RT
2893 },
78183f3f 2894 { }
4ddff493
BC		 2895};
2896
2897/* l4_abe -> mcbsp1 */
2898static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2899 .master = &omap44xx_l4_abe_hwmod,
2900 .slave = &omap44xx_mcbsp1_hwmod,
2901 .clk = "ocp_abe_iclk",
2902 .addr = omap44xx_mcbsp1_addrs,
4ddff493
BC		 2903 .user = OCP_USER_MPU,
2904};
2905
2906static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2907 {
cb7e9ded 2908 .name = "dma",
4ddff493
BC		 2909 .pa_start = 0x49022000,
2910 .pa_end = 0x490220ff,
2911 .flags = ADDR_TYPE_RT
2912 },
78183f3f 2913 { }
4ddff493
BC		 2914};
2915
2916/* l4_abe -> mcbsp1 (dma) */
2917static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2918 .master = &omap44xx_l4_abe_hwmod,
2919 .slave = &omap44xx_mcbsp1_hwmod,
2920 .clk = "ocp_abe_iclk",
2921 .addr = omap44xx_mcbsp1_dma_addrs,
4ddff493
BC		 2922 .user = OCP_USER_SDMA,
2923};
2924
2925/* mcbsp1 slave ports */
2926static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2927 &omap44xx_l4_abe__mcbsp1,
2928 &omap44xx_l4_abe__mcbsp1_dma,
2929};
2930
2931static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2932 .name = "mcbsp1",
2933 .class = &omap44xx_mcbsp_hwmod_class,
a5322c6f 2934 .clkdm_name = "abe_clkdm",
4ddff493 2935 .mpu_irqs = omap44xx_mcbsp1_irqs,
4ddff493 2936 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
4ddff493
BC		 2937 .main_clk = "mcbsp1_fck",
2938 .prcm = {
2939 .omap4 = {
2940 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2941 },
2942 },
2943 .slaves = omap44xx_mcbsp1_slaves,
2944 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2945 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2946};
2947
2948/* mcbsp2 */
2949static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2950static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2951 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
212738a4 2952 { .irq = -1 }
4ddff493
BC		 2953};
2954
2955static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2956 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2957 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
bc614958 2958 { .dma_req = -1 }
4ddff493
BC		 2959};
2960
2961static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2962 {
cb7e9ded 2963 .name = "mpu",
4ddff493
BC		 2964 .pa_start = 0x40124000,
2965 .pa_end = 0x401240ff,
2966 .flags = ADDR_TYPE_RT
2967 },
78183f3f 2968 { }
4ddff493
BC		 2969};
2970
2971/* l4_abe -> mcbsp2 */
2972static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2973 .master = &omap44xx_l4_abe_hwmod,
2974 .slave = &omap44xx_mcbsp2_hwmod,
2975 .clk = "ocp_abe_iclk",
2976 .addr = omap44xx_mcbsp2_addrs,
4ddff493
BC		 2977 .user = OCP_USER_MPU,
2978};
2979
2980static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2981 {
cb7e9ded 2982 .name = "dma",
4ddff493
BC		 2983 .pa_start = 0x49024000,
2984 .pa_end = 0x490240ff,
2985 .flags = ADDR_TYPE_RT
2986 },
78183f3f 2987 { }
4ddff493
BC		 2988};
2989
2990/* l4_abe -> mcbsp2 (dma) */
2991static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2992 .master = &omap44xx_l4_abe_hwmod,
2993 .slave = &omap44xx_mcbsp2_hwmod,
2994 .clk = "ocp_abe_iclk",
2995 .addr = omap44xx_mcbsp2_dma_addrs,
4ddff493
BC		 2996 .user = OCP_USER_SDMA,
2997};
2998
2999/* mcbsp2 slave ports */
3000static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3001 &omap44xx_l4_abe__mcbsp2,
3002 &omap44xx_l4_abe__mcbsp2_dma,
3003};
3004
3005static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3006 .name = "mcbsp2",
3007 .class = &omap44xx_mcbsp_hwmod_class,
a5322c6f 3008 .clkdm_name = "abe_clkdm",
4ddff493 3009 .mpu_irqs = omap44xx_mcbsp2_irqs,
4ddff493 3010 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
4ddff493
BC		 3011 .main_clk = "mcbsp2_fck",
3012 .prcm = {
3013 .omap4 = {
3014 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
3015 },
3016 },
3017 .slaves = omap44xx_mcbsp2_slaves,
3018 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3019 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3020};
3021
3022/* mcbsp3 */
3023static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3024static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3025 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
212738a4 3026 { .irq = -1 }
4ddff493
BC		 3027};
3028
3029static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3030 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3031 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
bc614958 3032 { .dma_req = -1 }
4ddff493
BC		 3033};
3034
3035static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3036 {
cb7e9ded 3037 .name = "mpu",
4ddff493
BC		 3038 .pa_start = 0x40126000,
3039 .pa_end = 0x401260ff,
3040 .flags = ADDR_TYPE_RT
3041 },
78183f3f 3042 { }
4ddff493
BC		 3043};
3044
3045/* l4_abe -> mcbsp3 */
3046static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3047 .master = &omap44xx_l4_abe_hwmod,
3048 .slave = &omap44xx_mcbsp3_hwmod,
3049 .clk = "ocp_abe_iclk",
3050 .addr = omap44xx_mcbsp3_addrs,
4ddff493
BC		 3051 .user = OCP_USER_MPU,
3052};
3053
3054static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3055 {
cb7e9ded 3056 .name = "dma",
4ddff493
BC		 3057 .pa_start = 0x49026000,
3058 .pa_end = 0x490260ff,
3059 .flags = ADDR_TYPE_RT
3060 },
78183f3f 3061 { }
4ddff493
BC		 3062};
3063
3064/* l4_abe -> mcbsp3 (dma) */
3065static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3066 .master = &omap44xx_l4_abe_hwmod,
3067 .slave = &omap44xx_mcbsp3_hwmod,
3068 .clk = "ocp_abe_iclk",
3069 .addr = omap44xx_mcbsp3_dma_addrs,
4ddff493
BC		 3070 .user = OCP_USER_SDMA,
3071};
3072
3073/* mcbsp3 slave ports */
3074static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3075 &omap44xx_l4_abe__mcbsp3,
3076 &omap44xx_l4_abe__mcbsp3_dma,
3077};
3078
3079static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3080 .name = "mcbsp3",
3081 .class = &omap44xx_mcbsp_hwmod_class,
a5322c6f 3082 .clkdm_name = "abe_clkdm",
4ddff493 3083 .mpu_irqs = omap44xx_mcbsp3_irqs,
4ddff493 3084 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
4ddff493
BC		 3085 .main_clk = "mcbsp3_fck",
3086 .prcm = {
3087 .omap4 = {
3088 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
3089 },
3090 },
3091 .slaves = omap44xx_mcbsp3_slaves,
3092 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3093 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3094};
3095
3096/* mcbsp4 */
3097static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3098static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3099 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
212738a4 3100 { .irq = -1 }
4ddff493
BC		 3101};
3102
3103static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3104 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3105 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
bc614958 3106 { .dma_req = -1 }
4ddff493
BC		 3107};
3108
3109static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3110 {
3111 .pa_start = 0x48096000,
3112 .pa_end = 0x480960ff,
3113 .flags = ADDR_TYPE_RT
3114 },
78183f3f 3115 { }
4ddff493
BC		 3116};
3117
3118/* l4_per -> mcbsp4 */
3119static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3120 .master = &omap44xx_l4_per_hwmod,
3121 .slave = &omap44xx_mcbsp4_hwmod,
3122 .clk = "l4_div_ck",
3123 .addr = omap44xx_mcbsp4_addrs,
4ddff493
BC		 3124 .user = OCP_USER_MPU | OCP_USER_SDMA,
3125};
3126
3127/* mcbsp4 slave ports */
3128static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3129 &omap44xx_l4_per__mcbsp4,
3130};
3131
3132static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3133 .name = "mcbsp4",
3134 .class = &omap44xx_mcbsp_hwmod_class,
a5322c6f 3135 .clkdm_name = "l4_per_clkdm",
4ddff493 3136 .mpu_irqs = omap44xx_mcbsp4_irqs,
4ddff493 3137 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
4ddff493
BC		 3138 .main_clk = "mcbsp4_fck",
3139 .prcm = {
3140 .omap4 = {
3141 .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3142 },
3143 },
3144 .slaves = omap44xx_mcbsp4_slaves,
3145 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3147};
3148
407a6888
BC		 3149/*
3150 * 'mcpdm' class
3151 * multi channel pdm controller (proprietary interface with phoenix power
3152 * ic)
3153 */
3154
3155static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3156 .rev_offs = 0x0000,
3157 .sysc_offs = 0x0010,
3158 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3159 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3160 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3161 SIDLE_SMART_WKUP),
3162 .sysc_fields = &omap_hwmod_sysc_type2,
3163};
3164
3165static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3166 .name = "mcpdm",
3167 .sysc = &omap44xx_mcpdm_sysc,
3168};
3169
3170/* mcpdm */
3171static struct omap_hwmod omap44xx_mcpdm_hwmod;
3172static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3173 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
212738a4 3174 { .irq = -1 }
407a6888
BC		 3175};
3176
3177static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3178 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3179 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
bc614958 3180 { .dma_req = -1 }
407a6888
BC		 3181};
3182
3183static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3184 {
3185 .pa_start = 0x40132000,
3186 .pa_end = 0x4013207f,
3187 .flags = ADDR_TYPE_RT
3188 },
78183f3f 3189 { }
407a6888
BC		 3190};
3191
3192/* l4_abe -> mcpdm */
3193static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3194 .master = &omap44xx_l4_abe_hwmod,
3195 .slave = &omap44xx_mcpdm_hwmod,
3196 .clk = "ocp_abe_iclk",
3197 .addr = omap44xx_mcpdm_addrs,
407a6888
BC		 3198 .user = OCP_USER_MPU,
3199};
3200
3201static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3202 {
3203 .pa_start = 0x49032000,
3204 .pa_end = 0x4903207f,
3205 .flags = ADDR_TYPE_RT
3206 },
78183f3f 3207 { }
407a6888
BC		 3208};
3209
3210/* l4_abe -> mcpdm (dma) */
3211static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3212 .master = &omap44xx_l4_abe_hwmod,
3213 .slave = &omap44xx_mcpdm_hwmod,
3214 .clk = "ocp_abe_iclk",
3215 .addr = omap44xx_mcpdm_dma_addrs,
407a6888
BC		 3216 .user = OCP_USER_SDMA,
3217};
3218
3219/* mcpdm slave ports */
3220static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3221 &omap44xx_l4_abe__mcpdm,
3222 &omap44xx_l4_abe__mcpdm_dma,
3223};
3224
3225static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3226 .name = "mcpdm",
3227 .class = &omap44xx_mcpdm_hwmod_class,
a5322c6f 3228 .clkdm_name = "abe_clkdm",
407a6888 3229 .mpu_irqs = omap44xx_mcpdm_irqs,
407a6888 3230 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
407a6888 3231 .main_clk = "mcpdm_fck",
00fe610b 3232 .prcm = {
407a6888
BC		 3233 .omap4 = {
3234 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3235 },
3236 },
3237 .slaves = omap44xx_mcpdm_slaves,
3238 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3240};
3241
9bcbd7f0
BC		 3242/*
3243 * 'mcspi' class
3244 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3245 * bus
3246 */
3247
3248static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3249 .rev_offs = 0x0000,
3250 .sysc_offs = 0x0010,
3251 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3252 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3253 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3254 SIDLE_SMART_WKUP),
3255 .sysc_fields = &omap_hwmod_sysc_type2,
3256};
3257
3258static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3259 .name = "mcspi",
3260 .sysc = &omap44xx_mcspi_sysc,
905a74d9 3261 .rev = OMAP4_MCSPI_REV,
9bcbd7f0
BC		 3262};
3263
3264/* mcspi1 */
3265static struct omap_hwmod omap44xx_mcspi1_hwmod;
3266static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3267 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
212738a4 3268 { .irq = -1 }
9bcbd7f0
BC		 3269};
3270
3271static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3272 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3273 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3274 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3275 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3276 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3277 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3278 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3279 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
bc614958 3280 { .dma_req = -1 }
9bcbd7f0
BC		 3281};
3282
3283static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3284 {
3285 .pa_start = 0x48098000,
3286 .pa_end = 0x480981ff,
3287 .flags = ADDR_TYPE_RT
3288 },
78183f3f 3289 { }
9bcbd7f0
BC		 3290};
3291
3292/* l4_per -> mcspi1 */
3293static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3294 .master = &omap44xx_l4_per_hwmod,
3295 .slave = &omap44xx_mcspi1_hwmod,
3296 .clk = "l4_div_ck",
3297 .addr = omap44xx_mcspi1_addrs,
9bcbd7f0
BC		 3298 .user = OCP_USER_MPU | OCP_USER_SDMA,
3299};
3300
3301/* mcspi1 slave ports */
3302static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3303 &omap44xx_l4_per__mcspi1,
3304};
3305
905a74d9
BC		 3306/* mcspi1 dev_attr */
3307static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3308 .num_chipselect = 4,
3309};
3310
9bcbd7f0
BC		 3311static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3312 .name = "mcspi1",
3313 .class = &omap44xx_mcspi_hwmod_class,
a5322c6f 3314 .clkdm_name = "l4_per_clkdm",
9bcbd7f0 3315 .mpu_irqs = omap44xx_mcspi1_irqs,
9bcbd7f0 3316 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
9bcbd7f0
BC		 3317 .main_clk = "mcspi1_fck",
3318 .prcm = {
3319 .omap4 = {
3320 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3321 },
3322 },
905a74d9 3323 .dev_attr = &mcspi1_dev_attr,
9bcbd7f0
BC		 3324 .slaves = omap44xx_mcspi1_slaves,
3325 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3326 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3327};
3328
3329/* mcspi2 */
3330static struct omap_hwmod omap44xx_mcspi2_hwmod;
3331static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3332 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
212738a4 3333 { .irq = -1 }
9bcbd7f0
BC		 3334};
3335
3336static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3337 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3338 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3339 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3340 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
bc614958 3341 { .dma_req = -1 }
9bcbd7f0
BC		 3342};
3343
3344static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3345 {
3346 .pa_start = 0x4809a000,
3347 .pa_end = 0x4809a1ff,
3348 .flags = ADDR_TYPE_RT
3349 },
78183f3f 3350 { }
9bcbd7f0
BC		 3351};
3352
3353/* l4_per -> mcspi2 */
3354static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3355 .master = &omap44xx_l4_per_hwmod,
3356 .slave = &omap44xx_mcspi2_hwmod,
3357 .clk = "l4_div_ck",
3358 .addr = omap44xx_mcspi2_addrs,
9bcbd7f0
BC		 3359 .user = OCP_USER_MPU | OCP_USER_SDMA,
3360};
3361
3362/* mcspi2 slave ports */
3363static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3364 &omap44xx_l4_per__mcspi2,
3365};
3366
905a74d9
BC		 3367/* mcspi2 dev_attr */
3368static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3369 .num_chipselect = 2,
3370};
3371
9bcbd7f0
BC		 3372static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3373 .name = "mcspi2",
3374 .class = &omap44xx_mcspi_hwmod_class,
a5322c6f 3375 .clkdm_name = "l4_per_clkdm",
9bcbd7f0 3376 .mpu_irqs = omap44xx_mcspi2_irqs,
9bcbd7f0 3377 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
9bcbd7f0
BC		 3378 .main_clk = "mcspi2_fck",
3379 .prcm = {
3380 .omap4 = {
3381 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3382 },
3383 },
905a74d9 3384 .dev_attr = &mcspi2_dev_attr,
9bcbd7f0
BC		 3385 .slaves = omap44xx_mcspi2_slaves,
3386 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3387 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3388};
3389
3390/* mcspi3 */
3391static struct omap_hwmod omap44xx_mcspi3_hwmod;
3392static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3393 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
212738a4 3394 { .irq = -1 }
9bcbd7f0
BC		 3395};
3396
3397static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3398 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3399 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3400 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3401 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
bc614958 3402 { .dma_req = -1 }
9bcbd7f0
BC		 3403};
3404
3405static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3406 {
3407 .pa_start = 0x480b8000,
3408 .pa_end = 0x480b81ff,
3409 .flags = ADDR_TYPE_RT
3410 },
78183f3f 3411 { }
9bcbd7f0
BC		 3412};
3413
3414/* l4_per -> mcspi3 */
3415static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3416 .master = &omap44xx_l4_per_hwmod,
3417 .slave = &omap44xx_mcspi3_hwmod,
3418 .clk = "l4_div_ck",
3419 .addr = omap44xx_mcspi3_addrs,
9bcbd7f0
BC		 3420 .user = OCP_USER_MPU | OCP_USER_SDMA,
3421};
3422
3423/* mcspi3 slave ports */
3424static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3425 &omap44xx_l4_per__mcspi3,
3426};
3427
905a74d9
BC		 3428/* mcspi3 dev_attr */
3429static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3430 .num_chipselect = 2,
3431};
3432
9bcbd7f0
BC		 3433static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3434 .name = "mcspi3",
3435 .class = &omap44xx_mcspi_hwmod_class,
a5322c6f 3436 .clkdm_name = "l4_per_clkdm",
9bcbd7f0 3437 .mpu_irqs = omap44xx_mcspi3_irqs,
9bcbd7f0 3438 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
9bcbd7f0
BC		 3439 .main_clk = "mcspi3_fck",
3440 .prcm = {
3441 .omap4 = {
3442 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3443 },
3444 },
905a74d9 3445 .dev_attr = &mcspi3_dev_attr,
9bcbd7f0
BC		 3446 .slaves = omap44xx_mcspi3_slaves,
3447 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3448 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3449};
3450
3451/* mcspi4 */
3452static struct omap_hwmod omap44xx_mcspi4_hwmod;
3453static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3454 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
212738a4 3455 { .irq = -1 }
9bcbd7f0
BC		 3456};
3457
3458static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3459 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3460 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
bc614958 3461 { .dma_req = -1 }
9bcbd7f0
BC		 3462};
3463
3464static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3465 {
3466 .pa_start = 0x480ba000,
3467 .pa_end = 0x480ba1ff,
3468 .flags = ADDR_TYPE_RT
3469 },
78183f3f 3470 { }
9bcbd7f0
BC		 3471};
3472
3473/* l4_per -> mcspi4 */
3474static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3475 .master = &omap44xx_l4_per_hwmod,
3476 .slave = &omap44xx_mcspi4_hwmod,
3477 .clk = "l4_div_ck",
3478 .addr = omap44xx_mcspi4_addrs,
9bcbd7f0
BC		 3479 .user = OCP_USER_MPU | OCP_USER_SDMA,
3480};
3481
3482/* mcspi4 slave ports */
3483static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3484 &omap44xx_l4_per__mcspi4,
3485};
3486
905a74d9
BC		 3487/* mcspi4 dev_attr */
3488static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3489 .num_chipselect = 1,
3490};
3491
9bcbd7f0
BC		 3492static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3493 .name = "mcspi4",
3494 .class = &omap44xx_mcspi_hwmod_class,
a5322c6f 3495 .clkdm_name = "l4_per_clkdm",
9bcbd7f0 3496 .mpu_irqs = omap44xx_mcspi4_irqs,
9bcbd7f0 3497 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
9bcbd7f0
BC		 3498 .main_clk = "mcspi4_fck",
3499 .prcm = {
3500 .omap4 = {
3501 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3502 },
3503 },
905a74d9 3504 .dev_attr = &mcspi4_dev_attr,
9bcbd7f0
BC		 3505 .slaves = omap44xx_mcspi4_slaves,
3506 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3507 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3508};
3509
407a6888
BC		 3510/*
3511 * 'mmc' class
3512 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3513 */
3514
3515static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3516 .rev_offs = 0x0000,
3517 .sysc_offs = 0x0010,
3518 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3519 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3520 SYSC_HAS_SOFTRESET),
3521 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3522 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
c614ebf6 3523 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
407a6888
BC		 3524 .sysc_fields = &omap_hwmod_sysc_type2,
3525};
3526
3527static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3528 .name = "mmc",
3529 .sysc = &omap44xx_mmc_sysc,
3530};
3531
3532/* mmc1 */
3533static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3534 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
212738a4 3535 { .irq = -1 }
407a6888
BC		 3536};
3537
3538static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3539 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3540 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
bc614958 3541 { .dma_req = -1 }
407a6888
BC		 3542};
3543
3544/* mmc1 master ports */
3545static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3546 &omap44xx_mmc1__l3_main_1,
3547};
3548
3549static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3550 {
3551 .pa_start = 0x4809c000,
3552 .pa_end = 0x4809c3ff,
3553 .flags = ADDR_TYPE_RT
3554 },
78183f3f 3555 { }
407a6888
BC		 3556};
3557
3558/* l4_per -> mmc1 */
3559static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3560 .master = &omap44xx_l4_per_hwmod,
3561 .slave = &omap44xx_mmc1_hwmod,
3562 .clk = "l4_div_ck",
3563 .addr = omap44xx_mmc1_addrs,
407a6888
BC		 3564 .user = OCP_USER_MPU | OCP_USER_SDMA,
3565};
3566
3567/* mmc1 slave ports */
3568static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3569 &omap44xx_l4_per__mmc1,
3570};
3571
6ab8946f
KK		 3572/* mmc1 dev_attr */
3573static struct omap_mmc_dev_attr mmc1_dev_attr = {
3574 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3575};
3576
407a6888
BC		 3577static struct omap_hwmod omap44xx_mmc1_hwmod = {
3578 .name = "mmc1",
3579 .class = &omap44xx_mmc_hwmod_class,
a5322c6f 3580 .clkdm_name = "l3_init_clkdm",
407a6888 3581 .mpu_irqs = omap44xx_mmc1_irqs,
407a6888 3582 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
407a6888 3583 .main_clk = "mmc1_fck",
00fe610b 3584 .prcm = {
407a6888
BC		 3585 .omap4 = {
3586 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3587 },
3588 },
6ab8946f 3589 .dev_attr = &mmc1_dev_attr,
407a6888
BC		 3590 .slaves = omap44xx_mmc1_slaves,
3591 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3592 .masters = omap44xx_mmc1_masters,
3593 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3594 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3595};
3596
3597/* mmc2 */
3598static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3599 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
212738a4 3600 { .irq = -1 }
407a6888
BC		 3601};
3602
3603static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3604 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3605 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
bc614958 3606 { .dma_req = -1 }
407a6888
BC		 3607};
3608
3609/* mmc2 master ports */
3610static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3611 &omap44xx_mmc2__l3_main_1,
3612};
3613
3614static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3615 {
3616 .pa_start = 0x480b4000,
3617 .pa_end = 0x480b43ff,
3618 .flags = ADDR_TYPE_RT
3619 },
78183f3f 3620 { }
407a6888
BC		 3621};
3622
3623/* l4_per -> mmc2 */
3624static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3625 .master = &omap44xx_l4_per_hwmod,
3626 .slave = &omap44xx_mmc2_hwmod,
3627 .clk = "l4_div_ck",
3628 .addr = omap44xx_mmc2_addrs,
407a6888
BC		 3629 .user = OCP_USER_MPU | OCP_USER_SDMA,
3630};
3631
3632/* mmc2 slave ports */
3633static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3634 &omap44xx_l4_per__mmc2,
3635};
3636
3637static struct omap_hwmod omap44xx_mmc2_hwmod = {
3638 .name = "mmc2",
3639 .class = &omap44xx_mmc_hwmod_class,
a5322c6f 3640 .clkdm_name = "l3_init_clkdm",
407a6888 3641 .mpu_irqs = omap44xx_mmc2_irqs,
407a6888 3642 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
407a6888 3643 .main_clk = "mmc2_fck",
00fe610b 3644 .prcm = {
407a6888
BC		 3645 .omap4 = {
3646 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3647 },
3648 },
3649 .slaves = omap44xx_mmc2_slaves,
3650 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3651 .masters = omap44xx_mmc2_masters,
3652 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3653 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3654};
3655
3656/* mmc3 */
3657static struct omap_hwmod omap44xx_mmc3_hwmod;
3658static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3659 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
212738a4 3660 { .irq = -1 }
407a6888
BC		 3661};
3662
3663static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3664 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3665 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
bc614958 3666 { .dma_req = -1 }
407a6888
BC		 3667};
3668
3669static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3670 {
3671 .pa_start = 0x480ad000,
3672 .pa_end = 0x480ad3ff,
3673 .flags = ADDR_TYPE_RT
3674 },
78183f3f 3675 { }
407a6888
BC		 3676};
3677
3678/* l4_per -> mmc3 */
3679static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3680 .master = &omap44xx_l4_per_hwmod,
3681 .slave = &omap44xx_mmc3_hwmod,
3682 .clk = "l4_div_ck",
3683 .addr = omap44xx_mmc3_addrs,
407a6888
BC		 3684 .user = OCP_USER_MPU | OCP_USER_SDMA,
3685};
3686
3687/* mmc3 slave ports */
3688static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3689 &omap44xx_l4_per__mmc3,
3690};
3691
3692static struct omap_hwmod omap44xx_mmc3_hwmod = {
3693 .name = "mmc3",
3694 .class = &omap44xx_mmc_hwmod_class,
a5322c6f 3695 .clkdm_name = "l4_per_clkdm",
407a6888 3696 .mpu_irqs = omap44xx_mmc3_irqs,
407a6888 3697 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
407a6888 3698 .main_clk = "mmc3_fck",
00fe610b 3699 .prcm = {
407a6888
BC		 3700 .omap4 = {
3701 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3702 },
3703 },
3704 .slaves = omap44xx_mmc3_slaves,
3705 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3706 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3707};
3708
3709/* mmc4 */
3710static struct omap_hwmod omap44xx_mmc4_hwmod;
3711static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3712 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
212738a4 3713 { .irq = -1 }
407a6888
BC		 3714};
3715
3716static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3717 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3718 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
bc614958 3719 { .dma_req = -1 }
407a6888
BC		 3720};
3721
3722static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3723 {
3724 .pa_start = 0x480d1000,
3725 .pa_end = 0x480d13ff,
3726 .flags = ADDR_TYPE_RT
3727 },
78183f3f 3728 { }
407a6888
BC		 3729};
3730
3731/* l4_per -> mmc4 */
3732static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3733 .master = &omap44xx_l4_per_hwmod,
3734 .slave = &omap44xx_mmc4_hwmod,
3735 .clk = "l4_div_ck",
3736 .addr = omap44xx_mmc4_addrs,
407a6888
BC		 3737 .user = OCP_USER_MPU | OCP_USER_SDMA,
3738};
3739
3740/* mmc4 slave ports */
3741static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3742 &omap44xx_l4_per__mmc4,
3743};
3744
3745static struct omap_hwmod omap44xx_mmc4_hwmod = {
3746 .name = "mmc4",
3747 .class = &omap44xx_mmc_hwmod_class,
a5322c6f 3748 .clkdm_name = "l4_per_clkdm",
407a6888 3749 .mpu_irqs = omap44xx_mmc4_irqs,
212738a4 3750
407a6888 3751 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
407a6888 3752 .main_clk = "mmc4_fck",
00fe610b 3753 .prcm = {
407a6888
BC		 3754 .omap4 = {
3755 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3756 },
3757 },
3758 .slaves = omap44xx_mmc4_slaves,
3759 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3760 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3761};
3762
3763/* mmc5 */
3764static struct omap_hwmod omap44xx_mmc5_hwmod;
3765static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3766 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
212738a4 3767 { .irq = -1 }
407a6888
BC		 3768};
3769
3770static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3771 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3772 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
bc614958 3773 { .dma_req = -1 }
407a6888
BC		 3774};
3775
3776static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3777 {
3778 .pa_start = 0x480d5000,
3779 .pa_end = 0x480d53ff,
3780 .flags = ADDR_TYPE_RT
3781 },
78183f3f 3782 { }
407a6888
BC		 3783};
3784
3785/* l4_per -> mmc5 */
3786static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3787 .master = &omap44xx_l4_per_hwmod,
3788 .slave = &omap44xx_mmc5_hwmod,
3789 .clk = "l4_div_ck",
3790 .addr = omap44xx_mmc5_addrs,
407a6888
BC		 3791 .user = OCP_USER_MPU | OCP_USER_SDMA,
3792};
3793
3794/* mmc5 slave ports */
3795static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3796 &omap44xx_l4_per__mmc5,
3797};
3798
3799static struct omap_hwmod omap44xx_mmc5_hwmod = {
3800 .name = "mmc5",
3801 .class = &omap44xx_mmc_hwmod_class,
a5322c6f 3802 .clkdm_name = "l4_per_clkdm",
407a6888 3803 .mpu_irqs = omap44xx_mmc5_irqs,
407a6888 3804 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
407a6888 3805 .main_clk = "mmc5_fck",
00fe610b 3806 .prcm = {
407a6888
BC		 3807 .omap4 = {
3808 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3809 },
3810 },
3811 .slaves = omap44xx_mmc5_slaves,
3812 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3813 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3814};
3815
3b54baad
BC		 3816/*
3817 * 'mpu' class
3818 * mpu sub-system
3819 */
3820
3821static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
fe13471c 3822 .name = "mpu",
db12ba53
BC		 3823};
3824
3b54baad
BC		 3825/* mpu */
3826static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3827 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3828 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3829 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
212738a4 3830 { .irq = -1 }
db12ba53
BC		 3831};
3832
3b54baad
BC		 3833/* mpu master ports */
3834static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3835 &omap44xx_mpu__l3_main_1,
3836 &omap44xx_mpu__l4_abe,
3837 &omap44xx_mpu__dmm,
3838};
3839
3840static struct omap_hwmod omap44xx_mpu_hwmod = {
3841 .name = "mpu",
3842 .class = &omap44xx_mpu_hwmod_class,
a5322c6f 3843 .clkdm_name = "mpuss_clkdm",
7ecc5373 3844 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3b54baad 3845 .mpu_irqs = omap44xx_mpu_irqs,
3b54baad 3846 .main_clk = "dpll_mpu_m2_ck",
db12ba53
BC		 3847 .prcm = {
3848 .omap4 = {
3b54baad 3849 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
db12ba53
BC		 3850 },
3851 },
3b54baad
BC		 3852 .masters = omap44xx_mpu_masters,
3853 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
db12ba53
BC		 3854 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3855};
3856
1f6a717f
BC		 3857/*
3858 * 'smartreflex' class
3859 * smartreflex module (monitor silicon performance and outputs a measure of
3860 * performance error)
3861 */
3862
3863/* The IP is not compliant to type1 / type2 scheme */
3864static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3865 .sidle_shift = 24,
3866 .enwkup_shift = 26,
3867};
3868
3869static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3870 .sysc_offs = 0x0038,
3871 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3872 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3873 SIDLE_SMART_WKUP),
3874 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3875};
3876
3877static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
fe13471c
BC		 3878 .name = "smartreflex",
3879 .sysc = &omap44xx_smartreflex_sysc,
3880 .rev = 2,
1f6a717f
BC		 3881};
3882
3883/* smartreflex_core */
3884static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3885static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3886 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
212738a4 3887 { .irq = -1 }
1f6a717f
BC		 3888};
3889
3890static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3891 {
3892 .pa_start = 0x4a0dd000,
3893 .pa_end = 0x4a0dd03f,
3894 .flags = ADDR_TYPE_RT
3895 },
78183f3f 3896 { }
1f6a717f
BC		 3897};
3898
3899/* l4_cfg -> smartreflex_core */
3900static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3901 .master = &omap44xx_l4_cfg_hwmod,
3902 .slave = &omap44xx_smartreflex_core_hwmod,
3903 .clk = "l4_div_ck",
3904 .addr = omap44xx_smartreflex_core_addrs,
1f6a717f
BC		 3905 .user = OCP_USER_MPU | OCP_USER_SDMA,
3906};
3907
3908/* smartreflex_core slave ports */
3909static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3910 &omap44xx_l4_cfg__smartreflex_core,
3911};
3912
3913static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3914 .name = "smartreflex_core",
3915 .class = &omap44xx_smartreflex_hwmod_class,
a5322c6f 3916 .clkdm_name = "l4_ao_clkdm",
1f6a717f 3917 .mpu_irqs = omap44xx_smartreflex_core_irqs,
212738a4 3918
1f6a717f
BC		 3919 .main_clk = "smartreflex_core_fck",
3920 .vdd_name = "core",
3921 .prcm = {
3922 .omap4 = {
3923 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3924 },
3925 },
3926 .slaves = omap44xx_smartreflex_core_slaves,
3927 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3928 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3929};
3930
3931/* smartreflex_iva */
3932static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3933static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3934 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
212738a4 3935 { .irq = -1 }
1f6a717f
BC		 3936};
3937
3938static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3939 {
3940 .pa_start = 0x4a0db000,
3941 .pa_end = 0x4a0db03f,
3942 .flags = ADDR_TYPE_RT
3943 },
78183f3f 3944 { }
1f6a717f
BC		 3945};
3946
3947/* l4_cfg -> smartreflex_iva */
3948static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3949 .master = &omap44xx_l4_cfg_hwmod,
3950 .slave = &omap44xx_smartreflex_iva_hwmod,
3951 .clk = "l4_div_ck",
3952 .addr = omap44xx_smartreflex_iva_addrs,
1f6a717f
BC		 3953 .user = OCP_USER_MPU | OCP_USER_SDMA,
3954};
3955
3956/* smartreflex_iva slave ports */
3957static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3958 &omap44xx_l4_cfg__smartreflex_iva,
3959};
3960
3961static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3962 .name = "smartreflex_iva",
3963 .class = &omap44xx_smartreflex_hwmod_class,
a5322c6f 3964 .clkdm_name = "l4_ao_clkdm",
1f6a717f 3965 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
1f6a717f
BC		 3966 .main_clk = "smartreflex_iva_fck",
3967 .vdd_name = "iva",
3968 .prcm = {
3969 .omap4 = {
3970 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3971 },
3972 },
3973 .slaves = omap44xx_smartreflex_iva_slaves,
3974 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3975 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3976};
3977
3978/* smartreflex_mpu */
3979static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3980static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3981 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
212738a4 3982 { .irq = -1 }
1f6a717f
BC		 3983};
3984
3985static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3986 {
3987 .pa_start = 0x4a0d9000,
3988 .pa_end = 0x4a0d903f,
3989 .flags = ADDR_TYPE_RT
3990 },
78183f3f 3991 { }
1f6a717f
BC		 3992};
3993
3994/* l4_cfg -> smartreflex_mpu */
3995static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3996 .master = &omap44xx_l4_cfg_hwmod,
3997 .slave = &omap44xx_smartreflex_mpu_hwmod,
3998 .clk = "l4_div_ck",
3999 .addr = omap44xx_smartreflex_mpu_addrs,
1f6a717f
BC		 4000 .user = OCP_USER_MPU | OCP_USER_SDMA,
4001};
4002
4003/* smartreflex_mpu slave ports */
4004static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4005 &omap44xx_l4_cfg__smartreflex_mpu,
4006};
4007
4008static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4009 .name = "smartreflex_mpu",
4010 .class = &omap44xx_smartreflex_hwmod_class,
a5322c6f 4011 .clkdm_name = "l4_ao_clkdm",
1f6a717f 4012 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
1f6a717f
BC		 4013 .main_clk = "smartreflex_mpu_fck",
4014 .vdd_name = "mpu",
4015 .prcm = {
4016 .omap4 = {
4017 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
4018 },
4019 },
4020 .slaves = omap44xx_smartreflex_mpu_slaves,
4021 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4022 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4023};
4024
d11c217f
BC		 4025/*
4026 * 'spinlock' class
4027 * spinlock provides hardware assistance for synchronizing the processes
4028 * running on multiple processors
4029 */
4030
4031static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4032 .rev_offs = 0x0000,
4033 .sysc_offs = 0x0010,
4034 .syss_offs = 0x0014,
4035 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4036 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4037 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4038 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4039 SIDLE_SMART_WKUP),
4040 .sysc_fields = &omap_hwmod_sysc_type1,
4041};
4042
4043static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4044 .name = "spinlock",
4045 .sysc = &omap44xx_spinlock_sysc,
4046};
4047
4048/* spinlock */
4049static struct omap_hwmod omap44xx_spinlock_hwmod;
4050static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4051 {
4052 .pa_start = 0x4a0f6000,
4053 .pa_end = 0x4a0f6fff,
4054 .flags = ADDR_TYPE_RT
4055 },
78183f3f 4056 { }
d11c217f
BC		 4057};
4058
4059/* l4_cfg -> spinlock */
4060static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4061 .master = &omap44xx_l4_cfg_hwmod,
4062 .slave = &omap44xx_spinlock_hwmod,
4063 .clk = "l4_div_ck",
4064 .addr = omap44xx_spinlock_addrs,
d11c217f
BC		 4065 .user = OCP_USER_MPU | OCP_USER_SDMA,
4066};
4067
4068/* spinlock slave ports */
4069static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4070 &omap44xx_l4_cfg__spinlock,
4071};
4072
4073static struct omap_hwmod omap44xx_spinlock_hwmod = {
4074 .name = "spinlock",
4075 .class = &omap44xx_spinlock_hwmod_class,
a5322c6f 4076 .clkdm_name = "l4_cfg_clkdm",
d11c217f
BC		 4077 .prcm = {
4078 .omap4 = {
4079 .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
4080 },
4081 },
4082 .slaves = omap44xx_spinlock_slaves,
4083 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4084 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4085};
4086
35d1a66a
BC		 4087/*
4088 * 'timer' class
4089 * general purpose timer module with accurate 1ms tick
4090 * This class contains several variants: ['timer_1ms', 'timer']
4091 */
4092
4093static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4094 .rev_offs = 0x0000,
4095 .sysc_offs = 0x0010,
4096 .syss_offs = 0x0014,
4097 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4098 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4099 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4100 SYSS_HAS_RESET_STATUS),
4101 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4102 .sysc_fields = &omap_hwmod_sysc_type1,
4103};
4104
4105static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4106 .name = "timer",
4107 .sysc = &omap44xx_timer_1ms_sysc,
4108};
4109
4110static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4111 .rev_offs = 0x0000,
4112 .sysc_offs = 0x0010,
4113 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4114 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4115 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4116 SIDLE_SMART_WKUP),
4117 .sysc_fields = &omap_hwmod_sysc_type2,
4118};
4119
4120static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4121 .name = "timer",
4122 .sysc = &omap44xx_timer_sysc,
4123};
4124
4125/* timer1 */
4126static struct omap_hwmod omap44xx_timer1_hwmod;
4127static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4128 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
212738a4 4129 { .irq = -1 }
35d1a66a
BC		 4130};
4131
4132static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4133 {
4134 .pa_start = 0x4a318000,
4135 .pa_end = 0x4a31807f,
4136 .flags = ADDR_TYPE_RT
4137 },
78183f3f 4138 { }
35d1a66a
BC		 4139};
4140
4141/* l4_wkup -> timer1 */
4142static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4143 .master = &omap44xx_l4_wkup_hwmod,
4144 .slave = &omap44xx_timer1_hwmod,
4145 .clk = "l4_wkup_clk_mux_ck",
4146 .addr = omap44xx_timer1_addrs,
35d1a66a
BC		 4147 .user = OCP_USER_MPU | OCP_USER_SDMA,
4148};
4149
4150/* timer1 slave ports */
4151static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4152 &omap44xx_l4_wkup__timer1,
4153};
4154
4155static struct omap_hwmod omap44xx_timer1_hwmod = {
4156 .name = "timer1",
4157 .class = &omap44xx_timer_1ms_hwmod_class,
a5322c6f 4158 .clkdm_name = "l4_wkup_clkdm",
35d1a66a 4159 .mpu_irqs = omap44xx_timer1_irqs,
35d1a66a
BC		 4160 .main_clk = "timer1_fck",
4161 .prcm = {
4162 .omap4 = {
4163 .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4164 },
4165 },
4166 .slaves = omap44xx_timer1_slaves,
4167 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4168 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4169};
4170
4171/* timer2 */
4172static struct omap_hwmod omap44xx_timer2_hwmod;
4173static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4174 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
212738a4 4175 { .irq = -1 }
35d1a66a
BC		 4176};
4177
4178static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4179 {
4180 .pa_start = 0x48032000,
4181 .pa_end = 0x4803207f,
4182 .flags = ADDR_TYPE_RT
4183 },
78183f3f 4184 { }
35d1a66a
BC		 4185};
4186
4187/* l4_per -> timer2 */
4188static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4189 .master = &omap44xx_l4_per_hwmod,
4190 .slave = &omap44xx_timer2_hwmod,
4191 .clk = "l4_div_ck",
4192 .addr = omap44xx_timer2_addrs,
35d1a66a
BC		 4193 .user = OCP_USER_MPU | OCP_USER_SDMA,
4194};
4195
4196/* timer2 slave ports */
4197static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4198 &omap44xx_l4_per__timer2,
4199};
4200
4201static struct omap_hwmod omap44xx_timer2_hwmod = {
4202 .name = "timer2",
4203 .class = &omap44xx_timer_1ms_hwmod_class,
a5322c6f 4204 .clkdm_name = "l4_per_clkdm",
35d1a66a 4205 .mpu_irqs = omap44xx_timer2_irqs,
35d1a66a
BC		 4206 .main_clk = "timer2_fck",
4207 .prcm = {
4208 .omap4 = {
4209 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4210 },
4211 },
4212 .slaves = omap44xx_timer2_slaves,
4213 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4214 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4215};
4216
4217/* timer3 */
4218static struct omap_hwmod omap44xx_timer3_hwmod;
4219static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4220 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
212738a4 4221 { .irq = -1 }
35d1a66a
BC		 4222};
4223
4224static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4225 {
4226 .pa_start = 0x48034000,
4227 .pa_end = 0x4803407f,
4228 .flags = ADDR_TYPE_RT
4229 },
78183f3f 4230 { }
35d1a66a
BC		 4231};
4232
4233/* l4_per -> timer3 */
4234static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4235 .master = &omap44xx_l4_per_hwmod,
4236 .slave = &omap44xx_timer3_hwmod,
4237 .clk = "l4_div_ck",
4238 .addr = omap44xx_timer3_addrs,
35d1a66a
BC		 4239 .user = OCP_USER_MPU | OCP_USER_SDMA,
4240};
4241
4242/* timer3 slave ports */
4243static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4244 &omap44xx_l4_per__timer3,
4245};
4246
4247static struct omap_hwmod omap44xx_timer3_hwmod = {
4248 .name = "timer3",
4249 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4250 .clkdm_name = "l4_per_clkdm",
35d1a66a 4251 .mpu_irqs = omap44xx_timer3_irqs,
35d1a66a
BC		 4252 .main_clk = "timer3_fck",
4253 .prcm = {
4254 .omap4 = {
4255 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4256 },
4257 },
4258 .slaves = omap44xx_timer3_slaves,
4259 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4260 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4261};
4262
4263/* timer4 */
4264static struct omap_hwmod omap44xx_timer4_hwmod;
4265static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4266 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
212738a4 4267 { .irq = -1 }
35d1a66a
BC		 4268};
4269
4270static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4271 {
4272 .pa_start = 0x48036000,
4273 .pa_end = 0x4803607f,
4274 .flags = ADDR_TYPE_RT
4275 },
78183f3f 4276 { }
35d1a66a
BC		 4277};
4278
4279/* l4_per -> timer4 */
4280static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4281 .master = &omap44xx_l4_per_hwmod,
4282 .slave = &omap44xx_timer4_hwmod,
4283 .clk = "l4_div_ck",
4284 .addr = omap44xx_timer4_addrs,
35d1a66a
BC		 4285 .user = OCP_USER_MPU | OCP_USER_SDMA,
4286};
4287
4288/* timer4 slave ports */
4289static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4290 &omap44xx_l4_per__timer4,
4291};
4292
4293static struct omap_hwmod omap44xx_timer4_hwmod = {
4294 .name = "timer4",
4295 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4296 .clkdm_name = "l4_per_clkdm",
35d1a66a 4297 .mpu_irqs = omap44xx_timer4_irqs,
35d1a66a
BC		 4298 .main_clk = "timer4_fck",
4299 .prcm = {
4300 .omap4 = {
4301 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4302 },
4303 },
4304 .slaves = omap44xx_timer4_slaves,
4305 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4306 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4307};
4308
4309/* timer5 */
4310static struct omap_hwmod omap44xx_timer5_hwmod;
4311static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4312 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
212738a4 4313 { .irq = -1 }
35d1a66a
BC		 4314};
4315
4316static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4317 {
4318 .pa_start = 0x40138000,
4319 .pa_end = 0x4013807f,
4320 .flags = ADDR_TYPE_RT
4321 },
78183f3f 4322 { }
35d1a66a
BC		 4323};
4324
4325/* l4_abe -> timer5 */
4326static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4327 .master = &omap44xx_l4_abe_hwmod,
4328 .slave = &omap44xx_timer5_hwmod,
4329 .clk = "ocp_abe_iclk",
4330 .addr = omap44xx_timer5_addrs,
35d1a66a
BC		 4331 .user = OCP_USER_MPU,
4332};
4333
4334static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4335 {
4336 .pa_start = 0x49038000,
4337 .pa_end = 0x4903807f,
4338 .flags = ADDR_TYPE_RT
4339 },
78183f3f 4340 { }
35d1a66a
BC		 4341};
4342
4343/* l4_abe -> timer5 (dma) */
4344static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4345 .master = &omap44xx_l4_abe_hwmod,
4346 .slave = &omap44xx_timer5_hwmod,
4347 .clk = "ocp_abe_iclk",
4348 .addr = omap44xx_timer5_dma_addrs,
35d1a66a
BC		 4349 .user = OCP_USER_SDMA,
4350};
4351
4352/* timer5 slave ports */
4353static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4354 &omap44xx_l4_abe__timer5,
4355 &omap44xx_l4_abe__timer5_dma,
4356};
4357
4358static struct omap_hwmod omap44xx_timer5_hwmod = {
4359 .name = "timer5",
4360 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4361 .clkdm_name = "abe_clkdm",
35d1a66a 4362 .mpu_irqs = omap44xx_timer5_irqs,
35d1a66a
BC		 4363 .main_clk = "timer5_fck",
4364 .prcm = {
4365 .omap4 = {
4366 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4367 },
4368 },
4369 .slaves = omap44xx_timer5_slaves,
4370 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4371 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4372};
4373
4374/* timer6 */
4375static struct omap_hwmod omap44xx_timer6_hwmod;
4376static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4377 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
212738a4 4378 { .irq = -1 }
35d1a66a
BC		 4379};
4380
4381static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4382 {
4383 .pa_start = 0x4013a000,
4384 .pa_end = 0x4013a07f,
4385 .flags = ADDR_TYPE_RT
4386 },
78183f3f 4387 { }
35d1a66a
BC		 4388};
4389
4390/* l4_abe -> timer6 */
4391static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4392 .master = &omap44xx_l4_abe_hwmod,
4393 .slave = &omap44xx_timer6_hwmod,
4394 .clk = "ocp_abe_iclk",
4395 .addr = omap44xx_timer6_addrs,
35d1a66a
BC		 4396 .user = OCP_USER_MPU,
4397};
4398
4399static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4400 {
4401 .pa_start = 0x4903a000,
4402 .pa_end = 0x4903a07f,
4403 .flags = ADDR_TYPE_RT
4404 },
78183f3f 4405 { }
35d1a66a
BC		 4406};
4407
4408/* l4_abe -> timer6 (dma) */
4409static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4410 .master = &omap44xx_l4_abe_hwmod,
4411 .slave = &omap44xx_timer6_hwmod,
4412 .clk = "ocp_abe_iclk",
4413 .addr = omap44xx_timer6_dma_addrs,
35d1a66a
BC		 4414 .user = OCP_USER_SDMA,
4415};
4416
4417/* timer6 slave ports */
4418static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4419 &omap44xx_l4_abe__timer6,
4420 &omap44xx_l4_abe__timer6_dma,
4421};
4422
4423static struct omap_hwmod omap44xx_timer6_hwmod = {
4424 .name = "timer6",
4425 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4426 .clkdm_name = "abe_clkdm",
35d1a66a 4427 .mpu_irqs = omap44xx_timer6_irqs,
212738a4 4428
35d1a66a
BC		 4429 .main_clk = "timer6_fck",
4430 .prcm = {
4431 .omap4 = {
4432 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4433 },
4434 },
4435 .slaves = omap44xx_timer6_slaves,
4436 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4437 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4438};
4439
4440/* timer7 */
4441static struct omap_hwmod omap44xx_timer7_hwmod;
4442static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4443 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
212738a4 4444 { .irq = -1 }
35d1a66a
BC		 4445};
4446
4447static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4448 {
4449 .pa_start = 0x4013c000,
4450 .pa_end = 0x4013c07f,
4451 .flags = ADDR_TYPE_RT
4452 },
78183f3f 4453 { }
35d1a66a
BC		 4454};
4455
4456/* l4_abe -> timer7 */
4457static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4458 .master = &omap44xx_l4_abe_hwmod,
4459 .slave = &omap44xx_timer7_hwmod,
4460 .clk = "ocp_abe_iclk",
4461 .addr = omap44xx_timer7_addrs,
35d1a66a
BC		 4462 .user = OCP_USER_MPU,
4463};
4464
4465static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4466 {
4467 .pa_start = 0x4903c000,
4468 .pa_end = 0x4903c07f,
4469 .flags = ADDR_TYPE_RT
4470 },
78183f3f 4471 { }
35d1a66a
BC		 4472};
4473
4474/* l4_abe -> timer7 (dma) */
4475static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4476 .master = &omap44xx_l4_abe_hwmod,
4477 .slave = &omap44xx_timer7_hwmod,
4478 .clk = "ocp_abe_iclk",
4479 .addr = omap44xx_timer7_dma_addrs,
35d1a66a
BC		 4480 .user = OCP_USER_SDMA,
4481};
4482
4483/* timer7 slave ports */
4484static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4485 &omap44xx_l4_abe__timer7,
4486 &omap44xx_l4_abe__timer7_dma,
4487};
4488
4489static struct omap_hwmod omap44xx_timer7_hwmod = {
4490 .name = "timer7",
4491 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4492 .clkdm_name = "abe_clkdm",
35d1a66a 4493 .mpu_irqs = omap44xx_timer7_irqs,
35d1a66a
BC		 4494 .main_clk = "timer7_fck",
4495 .prcm = {
4496 .omap4 = {
4497 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4498 },
4499 },
4500 .slaves = omap44xx_timer7_slaves,
4501 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4502 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4503};
4504
4505/* timer8 */
4506static struct omap_hwmod omap44xx_timer8_hwmod;
4507static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4508 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
212738a4 4509 { .irq = -1 }
35d1a66a
BC		 4510};
4511
4512static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4513 {
4514 .pa_start = 0x4013e000,
4515 .pa_end = 0x4013e07f,
4516 .flags = ADDR_TYPE_RT
4517 },
78183f3f 4518 { }
35d1a66a
BC		 4519};
4520
4521/* l4_abe -> timer8 */
4522static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4523 .master = &omap44xx_l4_abe_hwmod,
4524 .slave = &omap44xx_timer8_hwmod,
4525 .clk = "ocp_abe_iclk",
4526 .addr = omap44xx_timer8_addrs,
35d1a66a
BC		 4527 .user = OCP_USER_MPU,
4528};
4529
4530static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4531 {
4532 .pa_start = 0x4903e000,
4533 .pa_end = 0x4903e07f,
4534 .flags = ADDR_TYPE_RT
4535 },
78183f3f 4536 { }
35d1a66a
BC		 4537};
4538
4539/* l4_abe -> timer8 (dma) */
4540static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4541 .master = &omap44xx_l4_abe_hwmod,
4542 .slave = &omap44xx_timer8_hwmod,
4543 .clk = "ocp_abe_iclk",
4544 .addr = omap44xx_timer8_dma_addrs,
35d1a66a
BC		 4545 .user = OCP_USER_SDMA,
4546};
4547
4548/* timer8 slave ports */
4549static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4550 &omap44xx_l4_abe__timer8,
4551 &omap44xx_l4_abe__timer8_dma,
4552};
4553
4554static struct omap_hwmod omap44xx_timer8_hwmod = {
4555 .name = "timer8",
4556 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4557 .clkdm_name = "abe_clkdm",
35d1a66a 4558 .mpu_irqs = omap44xx_timer8_irqs,
35d1a66a
BC		 4559 .main_clk = "timer8_fck",
4560 .prcm = {
4561 .omap4 = {
4562 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4563 },
4564 },
4565 .slaves = omap44xx_timer8_slaves,
4566 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4567 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4568};
4569
4570/* timer9 */
4571static struct omap_hwmod omap44xx_timer9_hwmod;
4572static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4573 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
212738a4 4574 { .irq = -1 }
35d1a66a
BC		 4575};
4576
4577static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4578 {
4579 .pa_start = 0x4803e000,
4580 .pa_end = 0x4803e07f,
4581 .flags = ADDR_TYPE_RT
4582 },
78183f3f 4583 { }
35d1a66a
BC		 4584};
4585
4586/* l4_per -> timer9 */
4587static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4588 .master = &omap44xx_l4_per_hwmod,
4589 .slave = &omap44xx_timer9_hwmod,
4590 .clk = "l4_div_ck",
4591 .addr = omap44xx_timer9_addrs,
35d1a66a
BC		 4592 .user = OCP_USER_MPU | OCP_USER_SDMA,
4593};
4594
4595/* timer9 slave ports */
4596static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4597 &omap44xx_l4_per__timer9,
4598};
4599
4600static struct omap_hwmod omap44xx_timer9_hwmod = {
4601 .name = "timer9",
4602 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4603 .clkdm_name = "l4_per_clkdm",
35d1a66a 4604 .mpu_irqs = omap44xx_timer9_irqs,
35d1a66a
BC		 4605 .main_clk = "timer9_fck",
4606 .prcm = {
4607 .omap4 = {
4608 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4609 },
4610 },
4611 .slaves = omap44xx_timer9_slaves,
4612 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4613 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4614};
4615
4616/* timer10 */
4617static struct omap_hwmod omap44xx_timer10_hwmod;
4618static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4619 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
212738a4 4620 { .irq = -1 }
35d1a66a
BC		 4621};
4622
4623static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4624 {
4625 .pa_start = 0x48086000,
4626 .pa_end = 0x4808607f,
4627 .flags = ADDR_TYPE_RT
4628 },
78183f3f 4629 { }
35d1a66a
BC		 4630};
4631
4632/* l4_per -> timer10 */
4633static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4634 .master = &omap44xx_l4_per_hwmod,
4635 .slave = &omap44xx_timer10_hwmod,
4636 .clk = "l4_div_ck",
4637 .addr = omap44xx_timer10_addrs,
35d1a66a
BC		 4638 .user = OCP_USER_MPU | OCP_USER_SDMA,
4639};
4640
4641/* timer10 slave ports */
4642static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4643 &omap44xx_l4_per__timer10,
4644};
4645
4646static struct omap_hwmod omap44xx_timer10_hwmod = {
4647 .name = "timer10",
4648 .class = &omap44xx_timer_1ms_hwmod_class,
a5322c6f 4649 .clkdm_name = "l4_per_clkdm",
35d1a66a 4650 .mpu_irqs = omap44xx_timer10_irqs,
35d1a66a
BC		 4651 .main_clk = "timer10_fck",
4652 .prcm = {
4653 .omap4 = {
4654 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4655 },
4656 },
4657 .slaves = omap44xx_timer10_slaves,
4658 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4660};
4661
4662/* timer11 */
4663static struct omap_hwmod omap44xx_timer11_hwmod;
4664static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4665 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
212738a4 4666 { .irq = -1 }
35d1a66a
BC		 4667};
4668
4669static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4670 {
4671 .pa_start = 0x48088000,
4672 .pa_end = 0x4808807f,
4673 .flags = ADDR_TYPE_RT
4674 },
78183f3f 4675 { }
35d1a66a
BC		 4676};
4677
4678/* l4_per -> timer11 */
4679static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4680 .master = &omap44xx_l4_per_hwmod,
4681 .slave = &omap44xx_timer11_hwmod,
4682 .clk = "l4_div_ck",
4683 .addr = omap44xx_timer11_addrs,
35d1a66a
BC		 4684 .user = OCP_USER_MPU | OCP_USER_SDMA,
4685};
4686
4687/* timer11 slave ports */
4688static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4689 &omap44xx_l4_per__timer11,
4690};
4691
4692static struct omap_hwmod omap44xx_timer11_hwmod = {
4693 .name = "timer11",
4694 .class = &omap44xx_timer_hwmod_class,
a5322c6f 4695 .clkdm_name = "l4_per_clkdm",
35d1a66a 4696 .mpu_irqs = omap44xx_timer11_irqs,
35d1a66a
BC		 4697 .main_clk = "timer11_fck",
4698 .prcm = {
4699 .omap4 = {
4700 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4701 },
4702 },
4703 .slaves = omap44xx_timer11_slaves,
4704 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4705 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4706};
4707
9780a9cf 4708/*
3b54baad
BC		 4709 * 'uart' class
4710 * universal asynchronous receiver/transmitter (uart)
9780a9cf
BC		 4711 */
4712
3b54baad
BC		 4713static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4714 .rev_offs = 0x0050,
4715 .sysc_offs = 0x0054,
4716 .syss_offs = 0x0058,
4717 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
0cfe8751
BC		 4718 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4719 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 4720 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4721 SIDLE_SMART_WKUP),
9780a9cf
BC		 4722 .sysc_fields = &omap_hwmod_sysc_type1,
4723};
4724
3b54baad 4725static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
fe13471c
BC		 4726 .name = "uart",
4727 .sysc = &omap44xx_uart_sysc,
9780a9cf
BC		 4728};
4729
3b54baad
BC		 4730/* uart1 */
4731static struct omap_hwmod omap44xx_uart1_hwmod;
4732static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4733 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
212738a4 4734 { .irq = -1 }
9780a9cf
BC		 4735};
4736
3b54baad
BC		 4737static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4738 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4739 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
bc614958 4740 { .dma_req = -1 }
9780a9cf
BC		 4741};
4742
3b54baad 4743static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
9780a9cf 4744 {
3b54baad
BC		 4745 .pa_start = 0x4806a000,
4746 .pa_end = 0x4806a0ff,
9780a9cf
BC		 4747 .flags = ADDR_TYPE_RT
4748 },
78183f3f 4749 { }
9780a9cf
BC		 4750};
4751
3b54baad
BC		 4752/* l4_per -> uart1 */
4753static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4754 .master = &omap44xx_l4_per_hwmod,
4755 .slave = &omap44xx_uart1_hwmod,
4756 .clk = "l4_div_ck",
4757 .addr = omap44xx_uart1_addrs,
9780a9cf
BC		 4758 .user = OCP_USER_MPU | OCP_USER_SDMA,
4759};
4760
3b54baad
BC		 4761/* uart1 slave ports */
4762static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4763 &omap44xx_l4_per__uart1,
9780a9cf
BC		 4764};
4765
3b54baad
BC		 4766static struct omap_hwmod omap44xx_uart1_hwmod = {
4767 .name = "uart1",
4768 .class = &omap44xx_uart_hwmod_class,
a5322c6f 4769 .clkdm_name = "l4_per_clkdm",
3b54baad 4770 .mpu_irqs = omap44xx_uart1_irqs,
3b54baad 4771 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3b54baad 4772 .main_clk = "uart1_fck",
9780a9cf
BC		 4773 .prcm = {
4774 .omap4 = {
3b54baad 4775 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
9780a9cf
BC		 4776 },
4777 },
3b54baad
BC		 4778 .slaves = omap44xx_uart1_slaves,
4779 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
9780a9cf
BC		 4780 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4781};
4782
3b54baad
BC		 4783/* uart2 */
4784static struct omap_hwmod omap44xx_uart2_hwmod;
4785static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4786 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
212738a4 4787 { .irq = -1 }
9780a9cf
BC		 4788};
4789
3b54baad
BC		 4790static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4791 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4792 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
bc614958 4793 { .dma_req = -1 }
3b54baad
BC		 4794};
4795
4796static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
9780a9cf 4797 {
3b54baad
BC		 4798 .pa_start = 0x4806c000,
4799 .pa_end = 0x4806c0ff,
9780a9cf
BC		 4800 .flags = ADDR_TYPE_RT
4801 },
78183f3f 4802 { }
9780a9cf
BC		 4803};
4804
3b54baad
BC		 4805/* l4_per -> uart2 */
4806static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
9780a9cf 4807 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4808 .slave = &omap44xx_uart2_hwmod,
4809 .clk = "l4_div_ck",
4810 .addr = omap44xx_uart2_addrs,
9780a9cf
BC		 4811 .user = OCP_USER_MPU | OCP_USER_SDMA,
4812};
4813
3b54baad
BC		 4814/* uart2 slave ports */
4815static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4816 &omap44xx_l4_per__uart2,
9780a9cf
BC		 4817};
4818
3b54baad
BC		 4819static struct omap_hwmod omap44xx_uart2_hwmod = {
4820 .name = "uart2",
4821 .class = &omap44xx_uart_hwmod_class,
a5322c6f 4822 .clkdm_name = "l4_per_clkdm",
3b54baad 4823 .mpu_irqs = omap44xx_uart2_irqs,
3b54baad 4824 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3b54baad 4825 .main_clk = "uart2_fck",
9780a9cf
BC		 4826 .prcm = {
4827 .omap4 = {
3b54baad 4828 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
9780a9cf
BC		 4829 },
4830 },
3b54baad
BC		 4831 .slaves = omap44xx_uart2_slaves,
4832 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
9780a9cf
BC		 4833 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4834};
4835
3b54baad
BC		 4836/* uart3 */
4837static struct omap_hwmod omap44xx_uart3_hwmod;
4838static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4839 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
212738a4 4840 { .irq = -1 }
9780a9cf
BC		 4841};
4842
3b54baad
BC		 4843static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4844 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4845 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
bc614958 4846 { .dma_req = -1 }
3b54baad
BC		 4847};
4848
4849static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
9780a9cf 4850 {
3b54baad
BC		 4851 .pa_start = 0x48020000,
4852 .pa_end = 0x480200ff,
9780a9cf
BC		 4853 .flags = ADDR_TYPE_RT
4854 },
78183f3f 4855 { }
9780a9cf
BC		 4856};
4857
3b54baad
BC		 4858/* l4_per -> uart3 */
4859static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
9780a9cf 4860 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4861 .slave = &omap44xx_uart3_hwmod,
4862 .clk = "l4_div_ck",
4863 .addr = omap44xx_uart3_addrs,
9780a9cf
BC		 4864 .user = OCP_USER_MPU | OCP_USER_SDMA,
4865};
4866
3b54baad
BC		 4867/* uart3 slave ports */
4868static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4869 &omap44xx_l4_per__uart3,
4870};
4871
4872static struct omap_hwmod omap44xx_uart3_hwmod = {
4873 .name = "uart3",
4874 .class = &omap44xx_uart_hwmod_class,
a5322c6f 4875 .clkdm_name = "l4_per_clkdm",
7ecc5373 4876 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3b54baad 4877 .mpu_irqs = omap44xx_uart3_irqs,
3b54baad 4878 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3b54baad 4879 .main_clk = "uart3_fck",
9780a9cf
BC		 4880 .prcm = {
4881 .omap4 = {
3b54baad 4882 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
9780a9cf
BC		 4883 },
4884 },
3b54baad
BC		 4885 .slaves = omap44xx_uart3_slaves,
4886 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
9780a9cf
BC		 4887 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4888};
4889
3b54baad
BC		 4890/* uart4 */
4891static struct omap_hwmod omap44xx_uart4_hwmod;
4892static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4893 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
212738a4 4894 { .irq = -1 }
9780a9cf
BC		 4895};
4896
3b54baad
BC		 4897static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4898 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4899 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
bc614958 4900 { .dma_req = -1 }
3b54baad
BC		 4901};
4902
4903static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
9780a9cf 4904 {
3b54baad
BC		 4905 .pa_start = 0x4806e000,
4906 .pa_end = 0x4806e0ff,
9780a9cf
BC		 4907 .flags = ADDR_TYPE_RT
4908 },
78183f3f 4909 { }
9780a9cf
BC		 4910};
4911
3b54baad
BC		 4912/* l4_per -> uart4 */
4913static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
9780a9cf 4914 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 4915 .slave = &omap44xx_uart4_hwmod,
4916 .clk = "l4_div_ck",
4917 .addr = omap44xx_uart4_addrs,
9780a9cf
BC		 4918 .user = OCP_USER_MPU | OCP_USER_SDMA,
4919};
4920
3b54baad
BC		 4921/* uart4 slave ports */
4922static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4923 &omap44xx_l4_per__uart4,
9780a9cf
BC		 4924};
4925
3b54baad
BC		 4926static struct omap_hwmod omap44xx_uart4_hwmod = {
4927 .name = "uart4",
4928 .class = &omap44xx_uart_hwmod_class,
a5322c6f 4929 .clkdm_name = "l4_per_clkdm",
3b54baad 4930 .mpu_irqs = omap44xx_uart4_irqs,
3b54baad 4931 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3b54baad 4932 .main_clk = "uart4_fck",
9780a9cf
BC		 4933 .prcm = {
4934 .omap4 = {
3b54baad 4935 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
9780a9cf
BC		 4936 },
4937 },
3b54baad
BC		 4938 .slaves = omap44xx_uart4_slaves,
4939 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
9780a9cf
BC		 4940 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4941};
4942
5844c4ea
BC		 4943/*
4944 * 'usb_otg_hs' class
4945 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4946 */
4947
4948static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4949 .rev_offs = 0x0400,
4950 .sysc_offs = 0x0404,
4951 .syss_offs = 0x0408,
4952 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4953 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4954 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4955 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4956 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4957 MSTANDBY_SMART),
4958 .sysc_fields = &omap_hwmod_sysc_type1,
4959};
4960
4961static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
00fe610b
BC		 4962 .name = "usb_otg_hs",
4963 .sysc = &omap44xx_usb_otg_hs_sysc,
5844c4ea
BC		 4964};
4965
4966/* usb_otg_hs */
4967static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4968 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4969 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
212738a4 4970 { .irq = -1 }
5844c4ea
BC		 4971};
4972
4973/* usb_otg_hs master ports */
4974static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4975 &omap44xx_usb_otg_hs__l3_main_2,
4976};
4977
4978static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4979 {
4980 .pa_start = 0x4a0ab000,
4981 .pa_end = 0x4a0ab003,
4982 .flags = ADDR_TYPE_RT
4983 },
78183f3f 4984 { }
5844c4ea
BC		 4985};
4986
4987/* l4_cfg -> usb_otg_hs */
4988static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4989 .master = &omap44xx_l4_cfg_hwmod,
4990 .slave = &omap44xx_usb_otg_hs_hwmod,
4991 .clk = "l4_div_ck",
4992 .addr = omap44xx_usb_otg_hs_addrs,
5844c4ea
BC		 4993 .user = OCP_USER_MPU | OCP_USER_SDMA,
4994};
4995
4996/* usb_otg_hs slave ports */
4997static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4998 &omap44xx_l4_cfg__usb_otg_hs,
4999};
5000
5001static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5002 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5003};
5004
5005static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5006 .name = "usb_otg_hs",
5007 .class = &omap44xx_usb_otg_hs_hwmod_class,
a5322c6f 5008 .clkdm_name = "l3_init_clkdm",
5844c4ea
BC		 5009 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5010 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
5844c4ea
BC		 5011 .main_clk = "usb_otg_hs_ick",
5012 .prcm = {
5013 .omap4 = {
5014 .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
5015 },
5016 },
5017 .opt_clks = usb_otg_hs_opt_clks,
00fe610b 5018 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5844c4ea
BC		 5019 .slaves = omap44xx_usb_otg_hs_slaves,
5020 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5021 .masters = omap44xx_usb_otg_hs_masters,
5022 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5023 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5024};
5025
3b54baad
BC		 5026/*
5027 * 'wd_timer' class
5028 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5029 * overflow condition
5030 */
5031
5032static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5033 .rev_offs = 0x0000,
5034 .sysc_offs = 0x0010,
5035 .syss_offs = 0x0014,
5036 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
0cfe8751 5037 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 5038 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5039 SIDLE_SMART_WKUP),
3b54baad 5040 .sysc_fields = &omap_hwmod_sysc_type1,
9780a9cf
BC		 5041};
5042
3b54baad
BC		 5043static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5044 .name = "wd_timer",
5045 .sysc = &omap44xx_wd_timer_sysc,
fe13471c 5046 .pre_shutdown = &omap2_wd_timer_disable,
3b54baad
BC		 5047};
5048
5049/* wd_timer2 */
5050static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5051static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5052 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
212738a4 5053 { .irq = -1 }
3b54baad
BC		 5054};
5055
5056static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
9780a9cf 5057 {
3b54baad
BC		 5058 .pa_start = 0x4a314000,
5059 .pa_end = 0x4a31407f,
9780a9cf
BC		 5060 .flags = ADDR_TYPE_RT
5061 },
78183f3f 5062 { }
9780a9cf
BC		 5063};
5064
3b54baad
BC		 5065/* l4_wkup -> wd_timer2 */
5066static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5067 .master = &omap44xx_l4_wkup_hwmod,
5068 .slave = &omap44xx_wd_timer2_hwmod,
5069 .clk = "l4_wkup_clk_mux_ck",
5070 .addr = omap44xx_wd_timer2_addrs,
9780a9cf
BC		 5071 .user = OCP_USER_MPU | OCP_USER_SDMA,
5072};
5073
3b54baad
BC		 5074/* wd_timer2 slave ports */
5075static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5076 &omap44xx_l4_wkup__wd_timer2,
9780a9cf
BC		 5077};
5078
3b54baad
BC		 5079static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5080 .name = "wd_timer2",
5081 .class = &omap44xx_wd_timer_hwmod_class,
a5322c6f 5082 .clkdm_name = "l4_wkup_clkdm",
3b54baad 5083 .mpu_irqs = omap44xx_wd_timer2_irqs,
3b54baad 5084 .main_clk = "wd_timer2_fck",
9780a9cf
BC		 5085 .prcm = {
5086 .omap4 = {
3b54baad 5087 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
9780a9cf
BC		 5088 },
5089 },
3b54baad
BC		 5090 .slaves = omap44xx_wd_timer2_slaves,
5091 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
9780a9cf
BC		 5092 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5093};
5094
3b54baad
BC		 5095/* wd_timer3 */
5096static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5097static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5098 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
212738a4 5099 { .irq = -1 }
9780a9cf
BC		 5100};
5101
3b54baad 5102static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
9780a9cf 5103 {
3b54baad
BC		 5104 .pa_start = 0x40130000,
5105 .pa_end = 0x4013007f,
9780a9cf
BC		 5106 .flags = ADDR_TYPE_RT
5107 },
78183f3f 5108 { }
9780a9cf
BC		 5109};
5110
3b54baad
BC		 5111/* l4_abe -> wd_timer3 */
5112static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5113 .master = &omap44xx_l4_abe_hwmod,
5114 .slave = &omap44xx_wd_timer3_hwmod,
5115 .clk = "ocp_abe_iclk",
5116 .addr = omap44xx_wd_timer3_addrs,
3b54baad 5117 .user = OCP_USER_MPU,
9780a9cf
BC		 5118};
5119
3b54baad
BC		 5120static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5121 {
5122 .pa_start = 0x49030000,
5123 .pa_end = 0x4903007f,
5124 .flags = ADDR_TYPE_RT
5125 },
78183f3f 5126 { }
9780a9cf
BC		 5127};
5128
3b54baad
BC		 5129/* l4_abe -> wd_timer3 (dma) */
5130static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5131 .master = &omap44xx_l4_abe_hwmod,
5132 .slave = &omap44xx_wd_timer3_hwmod,
5133 .clk = "ocp_abe_iclk",
5134 .addr = omap44xx_wd_timer3_dma_addrs,
3b54baad 5135 .user = OCP_USER_SDMA,
9780a9cf
BC		 5136};
5137
3b54baad
BC		 5138/* wd_timer3 slave ports */
5139static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5140 &omap44xx_l4_abe__wd_timer3,
5141 &omap44xx_l4_abe__wd_timer3_dma,
5142};
5143
5144static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5145 .name = "wd_timer3",
5146 .class = &omap44xx_wd_timer_hwmod_class,
a5322c6f 5147 .clkdm_name = "abe_clkdm",
3b54baad 5148 .mpu_irqs = omap44xx_wd_timer3_irqs,
3b54baad 5149 .main_clk = "wd_timer3_fck",
9780a9cf
BC		 5150 .prcm = {
5151 .omap4 = {
3b54baad 5152 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
9780a9cf
BC		 5153 },
5154 },
3b54baad
BC		 5155 .slaves = omap44xx_wd_timer3_slaves,
5156 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
9780a9cf
BC		 5157 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5158};
531ce0d5 5159
55d2cb08 5160static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
fe13471c 5161
55d2cb08
BC		 5162 /* dmm class */
5163 &omap44xx_dmm_hwmod,
3b54baad 5164
55d2cb08
BC		 5165 /* emif_fw class */
5166 &omap44xx_emif_fw_hwmod,
3b54baad 5167
55d2cb08
BC		 5168 /* l3 class */
5169 &omap44xx_l3_instr_hwmod,
5170 &omap44xx_l3_main_1_hwmod,
5171 &omap44xx_l3_main_2_hwmod,
5172 &omap44xx_l3_main_3_hwmod,
3b54baad 5173
55d2cb08
BC		 5174 /* l4 class */
5175 &omap44xx_l4_abe_hwmod,
5176 &omap44xx_l4_cfg_hwmod,
5177 &omap44xx_l4_per_hwmod,
5178 &omap44xx_l4_wkup_hwmod,
531ce0d5 5179
55d2cb08
BC		 5180 /* mpu_bus class */
5181 &omap44xx_mpu_private_hwmod,
5182
407a6888
BC		 5183 /* aess class */
5184/* &omap44xx_aess_hwmod, */
5185
5186 /* bandgap class */
5187 &omap44xx_bandgap_hwmod,
5188
5189 /* counter class */
5190/* &omap44xx_counter_32k_hwmod, */
5191
d7cf5f33
BC		 5192 /* dma class */
5193 &omap44xx_dma_system_hwmod,
5194
8ca476da
BC		 5195 /* dmic class */
5196 &omap44xx_dmic_hwmod,
5197
8f25bdc5
BC		 5198 /* dsp class */
5199 &omap44xx_dsp_hwmod,
5200 &omap44xx_dsp_c0_hwmod,
5201
d63bd74f
BC		 5202 /* dss class */
5203 &omap44xx_dss_hwmod,
5204 &omap44xx_dss_dispc_hwmod,
5205 &omap44xx_dss_dsi1_hwmod,
5206 &omap44xx_dss_dsi2_hwmod,
5207 &omap44xx_dss_hdmi_hwmod,
5208 &omap44xx_dss_rfbi_hwmod,
5209 &omap44xx_dss_venc_hwmod,
5210
9780a9cf
BC		 5211 /* gpio class */
5212 &omap44xx_gpio1_hwmod,
5213 &omap44xx_gpio2_hwmod,
5214 &omap44xx_gpio3_hwmod,
5215 &omap44xx_gpio4_hwmod,
5216 &omap44xx_gpio5_hwmod,
5217 &omap44xx_gpio6_hwmod,
5218
407a6888
BC		 5219 /* hsi class */
5220/* &omap44xx_hsi_hwmod, */
5221
3b54baad
BC		 5222 /* i2c class */
5223 &omap44xx_i2c1_hwmod,
5224 &omap44xx_i2c2_hwmod,
5225 &omap44xx_i2c3_hwmod,
5226 &omap44xx_i2c4_hwmod,
5227
407a6888
BC		 5228 /* ipu class */
5229 &omap44xx_ipu_hwmod,
5230 &omap44xx_ipu_c0_hwmod,
5231 &omap44xx_ipu_c1_hwmod,
5232
5233 /* iss class */
5234/* &omap44xx_iss_hwmod, */
5235
8f25bdc5
BC		 5236 /* iva class */
5237 &omap44xx_iva_hwmod,
5238 &omap44xx_iva_seq0_hwmod,
5239 &omap44xx_iva_seq1_hwmod,
5240
407a6888 5241 /* kbd class */
4998b245 5242 &omap44xx_kbd_hwmod,
407a6888 5243
ec5df927
BC		 5244 /* mailbox class */
5245 &omap44xx_mailbox_hwmod,
5246
4ddff493
BC		 5247 /* mcbsp class */
5248 &omap44xx_mcbsp1_hwmod,
5249 &omap44xx_mcbsp2_hwmod,
5250 &omap44xx_mcbsp3_hwmod,
5251 &omap44xx_mcbsp4_hwmod,
5252
407a6888
BC		 5253 /* mcpdm class */
5254/* &omap44xx_mcpdm_hwmod, */
5255
9bcbd7f0
BC		 5256 /* mcspi class */
5257 &omap44xx_mcspi1_hwmod,
5258 &omap44xx_mcspi2_hwmod,
5259 &omap44xx_mcspi3_hwmod,
5260 &omap44xx_mcspi4_hwmod,
5261
407a6888 5262 /* mmc class */
17203bda
AG		 5263 &omap44xx_mmc1_hwmod,
5264 &omap44xx_mmc2_hwmod,
5265 &omap44xx_mmc3_hwmod,
5266 &omap44xx_mmc4_hwmod,
5267 &omap44xx_mmc5_hwmod,
407a6888 5268
55d2cb08
BC		 5269 /* mpu class */
5270 &omap44xx_mpu_hwmod,
db12ba53 5271
1f6a717f
BC		 5272 /* smartreflex class */
5273 &omap44xx_smartreflex_core_hwmod,
5274 &omap44xx_smartreflex_iva_hwmod,
5275 &omap44xx_smartreflex_mpu_hwmod,
5276
d11c217f
BC		 5277 /* spinlock class */
5278 &omap44xx_spinlock_hwmod,
5279
35d1a66a
BC		 5280 /* timer class */
5281 &omap44xx_timer1_hwmod,
5282 &omap44xx_timer2_hwmod,
5283 &omap44xx_timer3_hwmod,
5284 &omap44xx_timer4_hwmod,
5285 &omap44xx_timer5_hwmod,
5286 &omap44xx_timer6_hwmod,
5287 &omap44xx_timer7_hwmod,
5288 &omap44xx_timer8_hwmod,
5289 &omap44xx_timer9_hwmod,
5290 &omap44xx_timer10_hwmod,
5291 &omap44xx_timer11_hwmod,
5292
db12ba53
BC		 5293 /* uart class */
5294 &omap44xx_uart1_hwmod,
5295 &omap44xx_uart2_hwmod,
5296 &omap44xx_uart3_hwmod,
5297 &omap44xx_uart4_hwmod,
3b54baad 5298
5844c4ea
BC		 5299 /* usb_otg_hs class */
5300 &omap44xx_usb_otg_hs_hwmod,
5301
3b54baad
BC		 5302 /* wd_timer class */
5303 &omap44xx_wd_timer2_hwmod,
5304 &omap44xx_wd_timer3_hwmod,
5305
55d2cb08
BC		 5306 NULL,
5307};
5308
5309int __init omap44xx_hwmod_init(void)
5310{
550c8092 5311 return omap_hwmod_register(omap44xx_hwmods);
55d2cb08
BC		 5312}
5313
kernel source for telekom puls (alcatel/mediatek)