[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / omap_hwmod_2xxx_ipblock_data.c

/*
 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
 *
 * Copyright (C) 2011 Nokia Corporation
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include <plat/gpio.h>
#include <plat/dma.h>
#include <plat/dmtimer.h>
#include <plat/mcspi.h>

#include <mach/irqs.h>

#include "omap_hwmod_common_data.h"
#include "cm-regbits-24xx.h"
#include "prm-regbits-24xx.h"
#include "wd_timer.h"

struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
	{ .irq = 48, },
	{ .irq = -1 }
};

struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
	{ .name = "dispc", .dma_req = 5 },
	{ .dma_req = -1 }
};

/*
 * 'dispc' class
 * display controller
 */

static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_dispc_hwmod_class = {
	.name	= "dispc",
	.sysc	= &omap2_dispc_sysc,
};

/* OMAP2xxx Timer Common */
static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
			   SYSC_HAS_AUTOIDLE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
	.name	= "timer",
	.sysc	= &omap2xxx_timer_sysc,
	.rev	= OMAP_TIMER_IP_VERSION_1,
};

/*
 * 'wd_timer' class
 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 * overflow condition
 */

static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
	.name		= "wd_timer",
	.sysc		= &omap2xxx_wd_timer_sysc,
	.pre_shutdown	= &omap2_wd_timer_disable,
	.reset		= &omap2_wd_timer_reset,
};

/*
 * 'gpio' class
 * general purpose io module
 */
static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
	.name = "gpio",
	.sysc = &omap2xxx_gpio_sysc,
	.rev = 0,
};

/* system dma */
static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x002c,
	.syss_offs	= 0x0028,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
	.name	= "dma",
	.sysc	= &omap2xxx_dma_sysc,
};

/*
 * 'mailbox' class
 * mailbox module allowing communication between the on-chip processors
 * using a queued mailbox-interrupt mechanism.
 */

static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
	.rev_offs	= 0x000,
	.sysc_offs	= 0x010,
	.syss_offs	= 0x014,
	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
	.name	= "mailbox",
	.sysc	= &omap2xxx_mailbox_sysc,
};

/*
 * 'mcspi' class
 * multichannel serial port interface (mcspi) / master/slave synchronous serial
 * bus
 */

static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_mcspi_class = {
	.name	= "mcspi",
	.sysc	= &omap2xxx_mcspi_sysc,
	.rev	= OMAP2_MCSPI_REV,
};

/*
 * IP blocks
 */

/* L3 */
struct omap_hwmod omap2xxx_l3_main_hwmod = {
	.name		= "l3_main",
	.class		= &l3_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

/* L4 CORE */
struct omap_hwmod omap2xxx_l4_core_hwmod = {
	.name		= "l4_core",
	.class		= &l4_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

/* L4 WKUP */
struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
	.name		= "l4_wkup",
	.class		= &l4_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

/* MPU */
struct omap_hwmod omap2xxx_mpu_hwmod = {
	.name		= "mpu",
	.class		= &mpu_hwmod_class,
	.main_clk	= "mpu_ck",
};

/* IVA2 */
struct omap_hwmod omap2xxx_iva_hwmod = {
	.name		= "iva",
	.class		= &iva_hwmod_class,
};

/* always-on timers dev attribute */
static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
	.timer_capability       = OMAP_TIMER_ALWON,
};

/* pwm timers dev attribute */
static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
	.timer_capability       = OMAP_TIMER_HAS_PWM,
};

/* timer1 */

struct omap_hwmod omap2xxx_timer1_hwmod = {
	.name		= "timer1",
	.mpu_irqs	= omap2_timer1_mpu_irqs,
	.main_clk	= "gpt1_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT1_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
		},
	},
	.dev_attr	= &capability_alwon_dev_attr,
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer2 */

struct omap_hwmod omap2xxx_timer2_hwmod = {
	.name		= "timer2",
	.mpu_irqs	= omap2_timer2_mpu_irqs,
	.main_clk	= "gpt2_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT2_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer3 */

struct omap_hwmod omap2xxx_timer3_hwmod = {
	.name		= "timer3",
	.mpu_irqs	= omap2_timer3_mpu_irqs,
	.main_clk	= "gpt3_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT3_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer4 */

struct omap_hwmod omap2xxx_timer4_hwmod = {
	.name		= "timer4",
	.mpu_irqs	= omap2_timer4_mpu_irqs,
	.main_clk	= "gpt4_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT4_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer5 */

struct omap_hwmod omap2xxx_timer5_hwmod = {
	.name		= "timer5",
	.mpu_irqs	= omap2_timer5_mpu_irqs,
	.main_clk	= "gpt5_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT5_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer6 */

struct omap_hwmod omap2xxx_timer6_hwmod = {
	.name		= "timer6",
	.mpu_irqs	= omap2_timer6_mpu_irqs,
	.main_clk	= "gpt6_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT6_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer7 */

struct omap_hwmod omap2xxx_timer7_hwmod = {
	.name		= "timer7",
	.mpu_irqs	= omap2_timer7_mpu_irqs,
	.main_clk	= "gpt7_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT7_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer8 */

struct omap_hwmod omap2xxx_timer8_hwmod = {
	.name		= "timer8",
	.mpu_irqs	= omap2_timer8_mpu_irqs,
	.main_clk	= "gpt8_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT8_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer9 */

struct omap_hwmod omap2xxx_timer9_hwmod = {
	.name		= "timer9",
	.mpu_irqs	= omap2_timer9_mpu_irqs,
	.main_clk	= "gpt9_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT9_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
		},
	},
	.dev_attr	= &capability_pwm_dev_attr,
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer10 */

struct omap_hwmod omap2xxx_timer10_hwmod = {
	.name		= "timer10",
	.mpu_irqs	= omap2_timer10_mpu_irqs,
	.main_clk	= "gpt10_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT10_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
		},
	},
	.dev_attr	= &capability_pwm_dev_attr,
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer11 */

struct omap_hwmod omap2xxx_timer11_hwmod = {
	.name		= "timer11",
	.mpu_irqs	= omap2_timer11_mpu_irqs,
	.main_clk	= "gpt11_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT11_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
		},
	},
	.dev_attr	= &capability_pwm_dev_attr,
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer12 */

struct omap_hwmod omap2xxx_timer12_hwmod = {
	.name		= "timer12",
	.mpu_irqs	= omap2xxx_timer12_mpu_irqs,
	.main_clk	= "gpt12_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT12_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
		},
	},
	.dev_attr	= &capability_pwm_dev_attr,
	.class		= &omap2xxx_timer_hwmod_class,
};

/* wd_timer2 */
struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
	.name		= "wd_timer2",
	.class		= &omap2xxx_wd_timer_hwmod_class,
	.main_clk	= "mpu_wdt_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
		},
	},
};

/* UART1 */

struct omap_hwmod omap2xxx_uart1_hwmod = {
	.name		= "uart1",
	.mpu_irqs	= omap2_uart1_mpu_irqs,
	.sdma_reqs	= omap2_uart1_sdma_reqs,
	.main_clk	= "uart1_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_UART1_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
		},
	},
	.class		= &omap2_uart_class,
};

/* UART2 */

struct omap_hwmod omap2xxx_uart2_hwmod = {
	.name		= "uart2",
	.mpu_irqs	= omap2_uart2_mpu_irqs,
	.sdma_reqs	= omap2_uart2_sdma_reqs,
	.main_clk	= "uart2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_UART2_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
		},
	},
	.class		= &omap2_uart_class,
};

/* UART3 */

struct omap_hwmod omap2xxx_uart3_hwmod = {
	.name		= "uart3",
	.mpu_irqs	= omap2_uart3_mpu_irqs,
	.sdma_reqs	= omap2_uart3_sdma_reqs,
	.main_clk	= "uart3_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 2,
			.module_bit = OMAP24XX_EN_UART3_SHIFT,
			.idlest_reg_id = 2,
			.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
		},
	},
	.class		= &omap2_uart_class,
};

/* dss */

static struct omap_hwmod_opt_clk dss_opt_clks[] = {
	/*
	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
	 * driver does not use these clocks.
	 */
	{ .role = "tv_clk", .clk = "dss_54m_fck" },
	{ .role = "sys_clk", .clk = "dss2_fck" },
};

struct omap_hwmod omap2xxx_dss_core_hwmod = {
	.name		= "dss_core",
	.class		= &omap2_dss_hwmod_class,
	.main_clk	= "dss1_fck", /* instead of dss_fck */
	.sdma_reqs	= omap2xxx_dss_sdma_chs,
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
		},
	},
	.opt_clks	= dss_opt_clks,
	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
	.flags		= HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
};

struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
	.name		= "dss_dispc",
	.class		= &omap2_dispc_hwmod_class,
	.mpu_irqs	= omap2_dispc_irqs,
	.main_clk	= "dss1_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
		},
	},
	.flags		= HWMOD_NO_IDLEST,
	.dev_attr	= &omap2_3_dss_dispc_dev_attr
};

static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
	{ .role = "ick", .clk = "dss_ick" },
};

struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
	.name		= "dss_rfbi",
	.class		= &omap2_rfbi_hwmod_class,
	.main_clk	= "dss1_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
			.module_offs = CORE_MOD,
		},
	},
	.opt_clks	= dss_rfbi_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
	.flags		= HWMOD_NO_IDLEST,
};

struct omap_hwmod omap2xxx_dss_venc_hwmod = {
	.name		= "dss_venc",
	.class		= &omap2_venc_hwmod_class,
	.main_clk	= "dss_54m_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
			.module_offs = CORE_MOD,
		},
	},
	.flags		= HWMOD_NO_IDLEST,
};

/* gpio dev_attr */
struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
	.bank_width = 32,
	.dbck_flag = false,
};

/* gpio1 */
struct omap_hwmod omap2xxx_gpio1_hwmod = {
	.name		= "gpio1",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= omap2_gpio1_irqs,
	.main_clk	= "gpios_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
		},
	},
	.class		= &omap2xxx_gpio_hwmod_class,
	.dev_attr	= &omap2xxx_gpio_dev_attr,
};

/* gpio2 */
struct omap_hwmod omap2xxx_gpio2_hwmod = {
	.name		= "gpio2",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= omap2_gpio2_irqs,
	.main_clk	= "gpios_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
		},
	},
	.class		= &omap2xxx_gpio_hwmod_class,
	.dev_attr	= &omap2xxx_gpio_dev_attr,
};

/* gpio3 */
struct omap_hwmod omap2xxx_gpio3_hwmod = {
	.name		= "gpio3",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= omap2_gpio3_irqs,
	.main_clk	= "gpios_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
		},
	},
	.class		= &omap2xxx_gpio_hwmod_class,
	.dev_attr	= &omap2xxx_gpio_dev_attr,
};

/* gpio4 */
struct omap_hwmod omap2xxx_gpio4_hwmod = {
	.name		= "gpio4",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= omap2_gpio4_irqs,
	.main_clk	= "gpios_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
		},
	},
	.class		= &omap2xxx_gpio_hwmod_class,
	.dev_attr	= &omap2xxx_gpio_dev_attr,
};

/* mcspi1 */
static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
	.num_chipselect = 4,
};

struct omap_hwmod omap2xxx_mcspi1_hwmod = {
	.name		= "mcspi1",
	.mpu_irqs	= omap2_mcspi1_mpu_irqs,
	.sdma_reqs	= omap2_mcspi1_sdma_reqs,
	.main_clk	= "mcspi1_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
		},
	},
	.class		= &omap2xxx_mcspi_class,
	.dev_attr	= &omap_mcspi1_dev_attr,
};

/* mcspi2 */
static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
	.num_chipselect = 2,
};

struct omap_hwmod omap2xxx_mcspi2_hwmod = {
	.name		= "mcspi2",
	.mpu_irqs	= omap2_mcspi2_mpu_irqs,
	.sdma_reqs	= omap2_mcspi2_sdma_reqs,
	.main_clk	= "mcspi2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
		},
	},
	.class		= &omap2xxx_mcspi_class,
	.dev_attr	= &omap_mcspi2_dev_attr,
};


static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
	.name	= "counter",
};

struct omap_hwmod omap2xxx_counter_32k_hwmod = {
	.name		= "counter_32k",
	.main_clk	= "func_32k_ck",
	.prcm		= {
		.omap2	= {
			.module_offs = WKUP_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
		},
	},
	.class		= &omap2xxx_counter_hwmod_class,
};
Commit	Line	Data
0d619a89 PW	1	/*
	2	* omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
	3	*
	4	* Copyright (C) 2011 Nokia Corporation
	5	* Paul Walmsley
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <plat/omap_hwmod.h>
	12	#include <plat/serial.h>
cb48427e	13	#include <plat/gpio.h>
d826ebfa	14	#include <plat/dma.h>
273b9465 PW	15	#include <plat/dmtimer.h>
273b9465 PW	16	#include <plat/mcspi.h>
0d619a89 PW	17
	18	#include <mach/irqs.h>
	19
	20	#include "omap_hwmod_common_data.h"
cb48427e PW	21	#include "cm-regbits-24xx.h"
cb48427e PW	22	#include "prm-regbits-24xx.h"
273b9465	23	#include "wd_timer.h"
0d619a89 PW	24
	25	struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
	26	{ .irq = 48, },
	27	{ .irq = -1 }
	28	};
d826ebfa PW	29
	30	struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
	31	{ .name = "dispc", .dma_req = 5 },
	32	{ .dma_req = -1 }
	33	};
1ac6d46e TV	34
	35	/*
	36	* 'dispc' class
	37	* display controller
	38	*/
	39
	40	static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
	41	.rev_offs = 0x0000,
	42	.sysc_offs = 0x0010,
	43	.syss_offs = 0x0014,
	44	.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_MIDLEMODE \|
	45	SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE),
	46	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
	47	MSTANDBY_FORCE \| MSTANDBY_NO \| MSTANDBY_SMART),
	48	.sysc_fields = &omap_hwmod_sysc_type1,
	49	};
	50
	51	struct omap_hwmod_class omap2_dispc_hwmod_class = {
	52	.name = "dispc",
	53	.sysc = &omap2_dispc_sysc,
	54	};
	55
273b9465 PW	56	/* OMAP2xxx Timer Common */
	57	static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
	58	.rev_offs = 0x0000,
	59	.sysc_offs = 0x0010,
	60	.syss_offs = 0x0014,
	61	.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_CLOCKACTIVITY \|
	62	SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SOFTRESET \|
	63	SYSC_HAS_AUTOIDLE),
	64	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
	65	.sysc_fields = &omap_hwmod_sysc_type1,
	66	};
	67
	68	struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
	69	.name = "timer",
	70	.sysc = &omap2xxx_timer_sysc,
	71	.rev = OMAP_TIMER_IP_VERSION_1,
	72	};
	73
	74	/*
	75	* 'wd_timer' class
	76	* 32-bit watchdog upward counter that generates a pulse on the reset pin on
	77	* overflow condition
	78	*/
	79
	80	static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
	81	.rev_offs = 0x0000,
	82	.sysc_offs = 0x0010,
	83	.syss_offs = 0x0014,
	84	.sysc_flags = (SYSC_HAS_EMUFREE \| SYSC_HAS_SOFTRESET \|
	85	SYSC_HAS_AUTOIDLE \| SYSS_HAS_RESET_STATUS),
	86	.sysc_fields = &omap_hwmod_sysc_type1,
	87	};
	88
	89	struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
	90	.name = "wd_timer",
	91	.sysc = &omap2xxx_wd_timer_sysc,
414e4128 KH	92	.pre_shutdown = &omap2_wd_timer_disable,
414e4128 KH	93	.reset = &omap2_wd_timer_reset,
273b9465 PW	94	};
	95
	96	/*
	97	* 'gpio' class
	98	* general purpose io module
	99	*/
	100	static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
	101	.rev_offs = 0x0000,
	102	.sysc_offs = 0x0010,
	103	.syss_offs = 0x0014,
	104	.sysc_flags = (SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SIDLEMODE \|
	105	SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE \|
	106	SYSS_HAS_RESET_STATUS),
	107	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
	108	.sysc_fields = &omap_hwmod_sysc_type1,
	109	};
	110
	111	struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
	112	.name = "gpio",
	113	.sysc = &omap2xxx_gpio_sysc,
	114	.rev = 0,
	115	};
	116
	117	/* system dma */
	118	static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
	119	.rev_offs = 0x0000,
	120	.sysc_offs = 0x002c,
	121	.syss_offs = 0x0028,
	122	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSC_HAS_MIDLEMODE \|
	123	SYSC_HAS_CLOCKACTIVITY \| SYSC_HAS_EMUFREE \|
	124	SYSC_HAS_AUTOIDLE \| SYSS_HAS_RESET_STATUS),
	125	.idlemodes = (MSTANDBY_FORCE \| MSTANDBY_NO \| MSTANDBY_SMART),
	126	.sysc_fields = &omap_hwmod_sysc_type1,
	127	};
	128
	129	struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
	130	.name = "dma",
	131	.sysc = &omap2xxx_dma_sysc,
	132	};
	133
	134	/*
	135	* 'mailbox' class
	136	* mailbox module allowing communication between the on-chip processors
	137	* using a queued mailbox-interrupt mechanism.
	138	*/
	139
	140	static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
	141	.rev_offs = 0x000,
	142	.sysc_offs = 0x010,
	143	.syss_offs = 0x014,
	144	.sysc_flags = (SYSC_HAS_CLOCKACTIVITY \| SYSC_HAS_SIDLEMODE \|
	145	SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE),
	146	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
	147	.sysc_fields = &omap_hwmod_sysc_type1,
	148	};
	149
	150	struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
	151	.name = "mailbox",
	152	.sysc = &omap2xxx_mailbox_sysc,
	153	};
	154
	155	/*
	156	* 'mcspi' class
	157	* multichannel serial port interface (mcspi) / master/slave synchronous serial
158	* bus
159	*/
160
161	static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
162	.rev_offs = 0x0000,
163	.sysc_offs = 0x0010,
164	.syss_offs = 0x0014,
165	.sysc_flags = (SYSC_HAS_CLOCKACTIVITY \| SYSC_HAS_SIDLEMODE \|
166	SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SOFTRESET \|
167	SYSC_HAS_AUTOIDLE \| SYSS_HAS_RESET_STATUS),
168	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
169	.sysc_fields = &omap_hwmod_sysc_type1,
170	};
171
172	struct omap_hwmod_class omap2xxx_mcspi_class = {
173	.name = "mcspi",
174	.sysc = &omap2xxx_mcspi_sysc,
175	.rev = OMAP2_MCSPI_REV,
176	};
cb48427e PW	177
	178	/*
	179	* IP blocks
	180	*/
	181
	182	/* L3 */
	183	struct omap_hwmod omap2xxx_l3_main_hwmod = {
	184	.name = "l3_main",
	185	.class = &l3_hwmod_class,
	186	.flags = HWMOD_NO_IDLEST,
	187	};
	188
	189	/* L4 CORE */
	190	struct omap_hwmod omap2xxx_l4_core_hwmod = {
	191	.name = "l4_core",
	192	.class = &l4_hwmod_class,
	193	.flags = HWMOD_NO_IDLEST,
	194	};
	195
	196	/* L4 WKUP */
	197	struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
	198	.name = "l4_wkup",
	199	.class = &l4_hwmod_class,
	200	.flags = HWMOD_NO_IDLEST,
	201	};
	202
	203	/* MPU */
	204	struct omap_hwmod omap2xxx_mpu_hwmod = {
	205	.name = "mpu",
	206	.class = &mpu_hwmod_class,
	207	.main_clk = "mpu_ck",
	208	};
	209
	210	/* IVA2 */
	211	struct omap_hwmod omap2xxx_iva_hwmod = {
	212	.name = "iva",
	213	.class = &iva_hwmod_class,
	214	};
	215
	216	/* always-on timers dev attribute */
	217	static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
	218	.timer_capability = OMAP_TIMER_ALWON,
	219	};
	220
	221	/* pwm timers dev attribute */
	222	static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
	223	.timer_capability = OMAP_TIMER_HAS_PWM,
	224	};
	225
	226	/* timer1 */
	227
	228	struct omap_hwmod omap2xxx_timer1_hwmod = {
	229	.name = "timer1",
	230	.mpu_irqs = omap2_timer1_mpu_irqs,
	231	.main_clk = "gpt1_fck",
	232	.prcm = {
	233	.omap2 = {
	234	.prcm_reg_id = 1,
	235	.module_bit = OMAP24XX_EN_GPT1_SHIFT,
	236	.module_offs = WKUP_MOD,
	237	.idlest_reg_id = 1,
	238	.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
	239	},
	240	},
241	.dev_attr = &capability_alwon_dev_attr,
242	.class = &omap2xxx_timer_hwmod_class,
243	};
244
245	/* timer2 */
246
247	struct omap_hwmod omap2xxx_timer2_hwmod = {
248	.name = "timer2",
249	.mpu_irqs = omap2_timer2_mpu_irqs,
250	.main_clk = "gpt2_fck",
251	.prcm = {
252	.omap2 = {
253	.prcm_reg_id = 1,
254	.module_bit = OMAP24XX_EN_GPT2_SHIFT,
255	.module_offs = CORE_MOD,
256	.idlest_reg_id = 1,
257	.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
258	},
259	},
cb48427e PW	260	.class = &omap2xxx_timer_hwmod_class,
	261	};
	262
	263	/* timer3 */
	264
	265	struct omap_hwmod omap2xxx_timer3_hwmod = {
	266	.name = "timer3",
	267	.mpu_irqs = omap2_timer3_mpu_irqs,
	268	.main_clk = "gpt3_fck",
	269	.prcm = {
	270	.omap2 = {
	271	.prcm_reg_id = 1,
	272	.module_bit = OMAP24XX_EN_GPT3_SHIFT,
	273	.module_offs = CORE_MOD,
	274	.idlest_reg_id = 1,
	275	.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
	276	},
	277	},
cb48427e PW	278	.class = &omap2xxx_timer_hwmod_class,
	279	};
	280
	281	/* timer4 */
	282
	283	struct omap_hwmod omap2xxx_timer4_hwmod = {
	284	.name = "timer4",
	285	.mpu_irqs = omap2_timer4_mpu_irqs,
	286	.main_clk = "gpt4_fck",
	287	.prcm = {
	288	.omap2 = {
	289	.prcm_reg_id = 1,
	290	.module_bit = OMAP24XX_EN_GPT4_SHIFT,
	291	.module_offs = CORE_MOD,
	292	.idlest_reg_id = 1,
	293	.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
	294	},
	295	},
cb48427e PW	296	.class = &omap2xxx_timer_hwmod_class,
	297	};
	298
	299	/* timer5 */
	300
	301	struct omap_hwmod omap2xxx_timer5_hwmod = {
	302	.name = "timer5",
	303	.mpu_irqs = omap2_timer5_mpu_irqs,
	304	.main_clk = "gpt5_fck",
	305	.prcm = {
	306	.omap2 = {
	307	.prcm_reg_id = 1,
	308	.module_bit = OMAP24XX_EN_GPT5_SHIFT,
	309	.module_offs = CORE_MOD,
	310	.idlest_reg_id = 1,
	311	.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
	312	},
	313	},
cb48427e PW	314	.class = &omap2xxx_timer_hwmod_class,
	315	};
	316
	317	/* timer6 */
	318
	319	struct omap_hwmod omap2xxx_timer6_hwmod = {
	320	.name = "timer6",
	321	.mpu_irqs = omap2_timer6_mpu_irqs,
	322	.main_clk = "gpt6_fck",
	323	.prcm = {
	324	.omap2 = {
	325	.prcm_reg_id = 1,
	326	.module_bit = OMAP24XX_EN_GPT6_SHIFT,
	327	.module_offs = CORE_MOD,
	328	.idlest_reg_id = 1,
	329	.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
	330	},
	331	},
cb48427e PW	332	.class = &omap2xxx_timer_hwmod_class,
	333	};
	334
	335	/* timer7 */
	336
	337	struct omap_hwmod omap2xxx_timer7_hwmod = {
	338	.name = "timer7",
	339	.mpu_irqs = omap2_timer7_mpu_irqs,
	340	.main_clk = "gpt7_fck",
	341	.prcm = {
	342	.omap2 = {
	343	.prcm_reg_id = 1,
	344	.module_bit = OMAP24XX_EN_GPT7_SHIFT,
	345	.module_offs = CORE_MOD,
	346	.idlest_reg_id = 1,
	347	.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
	348	},
	349	},
cb48427e PW	350	.class = &omap2xxx_timer_hwmod_class,
	351	};
	352
	353	/* timer8 */
	354
	355	struct omap_hwmod omap2xxx_timer8_hwmod = {
	356	.name = "timer8",
	357	.mpu_irqs = omap2_timer8_mpu_irqs,
	358	.main_clk = "gpt8_fck",
	359	.prcm = {
	360	.omap2 = {
	361	.prcm_reg_id = 1,
	362	.module_bit = OMAP24XX_EN_GPT8_SHIFT,
	363	.module_offs = CORE_MOD,
	364	.idlest_reg_id = 1,
	365	.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
	366	},
	367	},
cb48427e PW	368	.class = &omap2xxx_timer_hwmod_class,
	369	};
	370
	371	/* timer9 */
	372
	373	struct omap_hwmod omap2xxx_timer9_hwmod = {
	374	.name = "timer9",
	375	.mpu_irqs = omap2_timer9_mpu_irqs,
	376	.main_clk = "gpt9_fck",
	377	.prcm = {
	378	.omap2 = {
	379	.prcm_reg_id = 1,
	380	.module_bit = OMAP24XX_EN_GPT9_SHIFT,
	381	.module_offs = CORE_MOD,
	382	.idlest_reg_id = 1,
	383	.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
	384	},
	385	},
	386	.dev_attr = &capability_pwm_dev_attr,
	387	.class = &omap2xxx_timer_hwmod_class,
	388	};
	389
	390	/* timer10 */
	391
	392	struct omap_hwmod omap2xxx_timer10_hwmod = {
	393	.name = "timer10",
	394	.mpu_irqs = omap2_timer10_mpu_irqs,
	395	.main_clk = "gpt10_fck",
	396	.prcm = {
	397	.omap2 = {
	398	.prcm_reg_id = 1,
	399	.module_bit = OMAP24XX_EN_GPT10_SHIFT,
	400	.module_offs = CORE_MOD,
	401	.idlest_reg_id = 1,
	402	.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
	403	},
	404	},
	405	.dev_attr = &capability_pwm_dev_attr,
	406	.class = &omap2xxx_timer_hwmod_class,
	407	};
	408
	409	/* timer11 */
	410
	411	struct omap_hwmod omap2xxx_timer11_hwmod = {
	412	.name = "timer11",
	413	.mpu_irqs = omap2_timer11_mpu_irqs,
	414	.main_clk = "gpt11_fck",
	415	.prcm = {
	416	.omap2 = {
	417	.prcm_reg_id = 1,
	418	.module_bit = OMAP24XX_EN_GPT11_SHIFT,
	419	.module_offs = CORE_MOD,
	420	.idlest_reg_id = 1,
	421	.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
	422	},
	423	},
	424	.dev_attr = &capability_pwm_dev_attr,
	425	.class = &omap2xxx_timer_hwmod_class,
	426	};
	427
	428	/* timer12 */
	429
	430	struct omap_hwmod omap2xxx_timer12_hwmod = {
	431	.name = "timer12",
432	.mpu_irqs = omap2xxx_timer12_mpu_irqs,
433	.main_clk = "gpt12_fck",
434	.prcm = {
435	.omap2 = {
436	.prcm_reg_id = 1,
437	.module_bit = OMAP24XX_EN_GPT12_SHIFT,
438	.module_offs = CORE_MOD,
439	.idlest_reg_id = 1,
440	.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
441	},
442	},
443	.dev_attr = &capability_pwm_dev_attr,
444	.class = &omap2xxx_timer_hwmod_class,
445	};
446
447	/* wd_timer2 */
448	struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
449	.name = "wd_timer2",
450	.class = &omap2xxx_wd_timer_hwmod_class,
451	.main_clk = "mpu_wdt_fck",
452	.prcm = {
453	.omap2 = {
454	.prcm_reg_id = 1,
455	.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
456	.module_offs = WKUP_MOD,
457	.idlest_reg_id = 1,
458	.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
459	},
460	},
461	};
462
463	/* UART1 */
464
465	struct omap_hwmod omap2xxx_uart1_hwmod = {
466	.name = "uart1",
467	.mpu_irqs = omap2_uart1_mpu_irqs,
468	.sdma_reqs = omap2_uart1_sdma_reqs,
469	.main_clk = "uart1_fck",
470	.prcm = {
471	.omap2 = {
472	.module_offs = CORE_MOD,
473	.prcm_reg_id = 1,
474	.module_bit = OMAP24XX_EN_UART1_SHIFT,
475	.idlest_reg_id = 1,
476	.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
477	},
478	},
479	.class = &omap2_uart_class,
480	};
481
482	/* UART2 */
483
484	struct omap_hwmod omap2xxx_uart2_hwmod = {
485	.name = "uart2",
486	.mpu_irqs = omap2_uart2_mpu_irqs,
487	.sdma_reqs = omap2_uart2_sdma_reqs,
488	.main_clk = "uart2_fck",
489	.prcm = {
490	.omap2 = {
491	.module_offs = CORE_MOD,
492	.prcm_reg_id = 1,
493	.module_bit = OMAP24XX_EN_UART2_SHIFT,
494	.idlest_reg_id = 1,
495	.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
496	},
497	},
498	.class = &omap2_uart_class,
499	};
500
501	/* UART3 */
502
503	struct omap_hwmod omap2xxx_uart3_hwmod = {
504	.name = "uart3",
505	.mpu_irqs = omap2_uart3_mpu_irqs,
506	.sdma_reqs = omap2_uart3_sdma_reqs,
507	.main_clk = "uart3_fck",
508	.prcm = {
509	.omap2 = {
510	.module_offs = CORE_MOD,
511	.prcm_reg_id = 2,
512	.module_bit = OMAP24XX_EN_UART3_SHIFT,
513	.idlest_reg_id = 2,
514	.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
515	},
516	},
517	.class = &omap2_uart_class,
518	};
519
520	/* dss */
521
522	static struct omap_hwmod_opt_clk dss_opt_clks[] = {
523	/*
524	* The DSS HW needs all DSS clocks enabled during reset. The dss_core
525	* driver does not use these clocks.
526	*/
527	{ .role = "tv_clk", .clk = "dss_54m_fck" },
528	{ .role = "sys_clk", .clk = "dss2_fck" },
529	};
530
531	struct omap_hwmod omap2xxx_dss_core_hwmod = {
532	.name = "dss_core",
533	.class = &omap2_dss_hwmod_class,
534	.main_clk = "dss1_fck", /* instead of dss_fck */
535	.sdma_reqs = omap2xxx_dss_sdma_chs,
536	.prcm = {
537	.omap2 = {
538	.prcm_reg_id = 1,
539	.module_bit = OMAP24XX_EN_DSS1_SHIFT,
540	.module_offs = CORE_MOD,
541	.idlest_reg_id = 1,
542	.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
543	},
544	},
545	.opt_clks = dss_opt_clks,
546	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
547	.flags = HWMOD_NO_IDLEST \| HWMOD_CONTROL_OPT_CLKS_IN_RESET,
548	};
549
550	struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
551	.name = "dss_dispc",
552	.class = &omap2_dispc_hwmod_class,
553	.mpu_irqs = omap2_dispc_irqs,
554	.main_clk = "dss1_fck",
555	.prcm = {
556	.omap2 = {
557	.prcm_reg_id = 1,
558	.module_bit = OMAP24XX_EN_DSS1_SHIFT,
559	.module_offs = CORE_MOD,
560	.idlest_reg_id = 1,
561	.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
562	},
563	},
564	.flags = HWMOD_NO_IDLEST,
565	.dev_attr = &omap2_3_dss_dispc_dev_attr
566	};
567
568	static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
569	{ .role = "ick", .clk = "dss_ick" },
570	};
571
572	struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
573	.name = "dss_rfbi",
574	.class = &omap2_rfbi_hwmod_class,
575	.main_clk = "dss1_fck",
576	.prcm = {
577	.omap2 = {
578	.prcm_reg_id = 1,
579	.module_bit = OMAP24XX_EN_DSS1_SHIFT,
580	.module_offs = CORE_MOD,
581	},
582	},
583	.opt_clks = dss_rfbi_opt_clks,
584	.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
585	.flags = HWMOD_NO_IDLEST,
586	};
587
588	struct omap_hwmod omap2xxx_dss_venc_hwmod = {
589	.name = "dss_venc",
590	.class = &omap2_venc_hwmod_class,
591	.main_clk = "dss_54m_fck",
592	.prcm = {
593	.omap2 = {
594	.prcm_reg_id = 1,
595	.module_bit = OMAP24XX_EN_DSS1_SHIFT,
596	.module_offs = CORE_MOD,
597	},
598	},
599	.flags = HWMOD_NO_IDLEST,
600	};
601
602	/* gpio dev_attr */
603	struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
604	.bank_width = 32,
605	.dbck_flag = false,
606	};
607
608	/* gpio1 */
609	struct omap_hwmod omap2xxx_gpio1_hwmod = {
610	.name = "gpio1",
611	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
612	.mpu_irqs = omap2_gpio1_irqs,
613	.main_clk = "gpios_fck",
614	.prcm = {
615	.omap2 = {
616	.prcm_reg_id = 1,
617	.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
618	.module_offs = WKUP_MOD,
619	.idlest_reg_id = 1,
620	.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
621	},
622	},
623	.class = &omap2xxx_gpio_hwmod_class,
624	.dev_attr = &omap2xxx_gpio_dev_attr,
625	};
626
627	/* gpio2 */
628	struct omap_hwmod omap2xxx_gpio2_hwmod = {
629	.name = "gpio2",
630	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
631	.mpu_irqs = omap2_gpio2_irqs,
632	.main_clk = "gpios_fck",
633	.prcm = {
634	.omap2 = {
635	.prcm_reg_id = 1,
636	.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
637	.module_offs = WKUP_MOD,
638	.idlest_reg_id = 1,
639	.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
640	},
641	},
642	.class = &omap2xxx_gpio_hwmod_class,
643	.dev_attr = &omap2xxx_gpio_dev_attr,
644	};
645
646	/* gpio3 */
647	struct omap_hwmod omap2xxx_gpio3_hwmod = {
648	.name = "gpio3",
649	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
650	.mpu_irqs = omap2_gpio3_irqs,
651	.main_clk = "gpios_fck",
652	.prcm = {
653	.omap2 = {
654	.prcm_reg_id = 1,
655	.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
656	.module_offs = WKUP_MOD,
657	.idlest_reg_id = 1,
658	.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
659	},
660	},
661	.class = &omap2xxx_gpio_hwmod_class,
662	.dev_attr = &omap2xxx_gpio_dev_attr,
663	};
664
665	/* gpio4 */
666	struct omap_hwmod omap2xxx_gpio4_hwmod = {
667	.name = "gpio4",
668	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
669	.mpu_irqs = omap2_gpio4_irqs,
670	.main_clk = "gpios_fck",
671	.prcm = {
672	.omap2 = {
673	.prcm_reg_id = 1,
674	.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
675	.module_offs = WKUP_MOD,
676	.idlest_reg_id = 1,
677	.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
678	},
679	},
680	.class = &omap2xxx_gpio_hwmod_class,
681	.dev_attr = &omap2xxx_gpio_dev_attr,
682	};
683
684	/* mcspi1 */
685	static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
686	.num_chipselect = 4,
687	};
688
689	struct omap_hwmod omap2xxx_mcspi1_hwmod = {
690	.name = "mcspi1",
691	.mpu_irqs = omap2_mcspi1_mpu_irqs,
692	.sdma_reqs = omap2_mcspi1_sdma_reqs,
693	.main_clk = "mcspi1_fck",
694	.prcm = {
695	.omap2 = {
696	.module_offs = CORE_MOD,
697	.prcm_reg_id = 1,
698	.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
699	.idlest_reg_id = 1,
700	.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
701	},
702	},
703	.class = &omap2xxx_mcspi_class,
704	.dev_attr = &omap_mcspi1_dev_attr,
705	};
706
707	/* mcspi2 */
708	static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
709	.num_chipselect = 2,
710	};
711
712	struct omap_hwmod omap2xxx_mcspi2_hwmod = {
713	.name = "mcspi2",
714	.mpu_irqs = omap2_mcspi2_mpu_irqs,
715	.sdma_reqs = omap2_mcspi2_sdma_reqs,
716	.main_clk = "mcspi2_fck",
717	.prcm = {
718	.omap2 = {
719	.module_offs = CORE_MOD,
720	.prcm_reg_id = 1,
721	.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
722	.idlest_reg_id = 1,
723	.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
724	},
725	},
726	.class = &omap2xxx_mcspi_class,
727	.dev_attr = &omap_mcspi2_dev_attr,
728	};
c8d82ff6 VH	729
	730
	731	static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
	732	.name = "counter",
	733	};
	734
	735	struct omap_hwmod omap2xxx_counter_32k_hwmod = {
	736	.name = "counter_32k",
	737	.main_clk = "func_32k_ck",
	738	.prcm = {
	739	.omap2 = {
	740	.module_offs = WKUP_MOD,
	741	.prcm_reg_id = 1,
	742	.module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
	743	.idlest_reg_id = 1,
	744	.idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
	745	},
	746	},
	747	.class = &omap2xxx_counter_hwmod_class,
	748	};