projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 501f0c75 SS |
1 | /* |
| 2 | * omap4-sar-layout.h: OMAP4 SAR RAM layout header file | |
| 3 | * | |
| 4 | * Copyright (C) 2011 Texas Instruments, Inc. | |
| 5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | #ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H | |
| 12 | #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H | |
| 13 | ||
| 14 | /* | |
| 247c445c | 15 | * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE |
| 501f0c75 SS |
16 | */ |
| 17 | #define SAR_BANK1_OFFSET 0x0000 | |
| 18 | #define SAR_BANK2_OFFSET 0x1000 | |
| 19 | #define SAR_BANK3_OFFSET 0x2000 | |
| 20 | #define SAR_BANK4_OFFSET 0x3000 | |
| 21 | ||
| b2b9762f | 22 | /* Scratch pad memory offsets from SAR_BANK1 */ |
| f98d5fe8 TK |
23 | #define SCU_OFFSET0 0xfe4 |
| 24 | #define SCU_OFFSET1 0xfe8 | |
| 25 | #define OMAP_TYPE_OFFSET 0xfec | |
| 26 | #define L2X0_SAVE_OFFSET0 0xff0 | |
| 27 | #define L2X0_SAVE_OFFSET1 0xff4 | |
| 28 | #define L2X0_AUXCTRL_OFFSET 0xff8 | |
| 29 | #define L2X0_PREFETCH_CTRL_OFFSET 0xffc | |
| b2b9762f SS |
30 | |
| 31 | /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */ | |
| 32 | #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 | |
| 33 | #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08 | |
| 34 | ||
| 0f3cf2ec SS |
35 | #define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500) |
| 36 | #define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504) | |
| 37 | #define SAR_SECRAM_SAVED_AT_OFFSET (SAR_BANK3_OFFSET + 0x508) | |
| 38 | ||
| 39 | /* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */ | |
| 40 | #define WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x684) | |
| 41 | #define WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x694) | |
| 42 | #define WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6a4) | |
| 43 | #define WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6b4) | |
| 44 | #define AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x6c4) | |
| 45 | #define AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x6c8) | |
| 46 | #define PTMSYNCREQ_MASK_OFFSET (SAR_BANK3_OFFSET + 0x6cc) | |
| 47 | #define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0) | |
| 48 | #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 | |
| 49 | ||
| 247c445c | 50 | /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ |
| 13fcef94 SS |
51 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) |
| 52 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) | |
| 53 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) | |
| 54 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) | |
| 55 | #define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) | |
| 56 | #define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) | |
| 57 | #define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) | |
| 247c445c SS |
58 | #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) |
| 59 | ||
| 501f0c75 | 60 | #endif |