Commit | Line | Data |
---|---|---|
340a614a HD |
1 | /* |
2 | * Mailbox reservation modules for OMAP2 | |
3 | * | |
4 | * Copyright (C) 2006 Nokia Corporation | |
5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | |
6 | * and Paul Mundt <paul.mundt@nokia.com> | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <asm/arch/mailbox.h> | |
18 | #include <asm/arch/irqs.h> | |
19 | #include <asm/io.h> | |
20 | ||
21 | #define MAILBOX_REVISION 0x00 | |
22 | #define MAILBOX_SYSCONFIG 0x10 | |
23 | #define MAILBOX_SYSSTATUS 0x14 | |
24 | #define MAILBOX_MESSAGE_0 0x40 | |
25 | #define MAILBOX_MESSAGE_1 0x44 | |
26 | #define MAILBOX_MESSAGE_2 0x48 | |
27 | #define MAILBOX_MESSAGE_3 0x4c | |
28 | #define MAILBOX_MESSAGE_4 0x50 | |
29 | #define MAILBOX_MESSAGE_5 0x54 | |
30 | #define MAILBOX_FIFOSTATUS_0 0x80 | |
31 | #define MAILBOX_FIFOSTATUS_1 0x84 | |
32 | #define MAILBOX_FIFOSTATUS_2 0x88 | |
33 | #define MAILBOX_FIFOSTATUS_3 0x8c | |
34 | #define MAILBOX_FIFOSTATUS_4 0x90 | |
35 | #define MAILBOX_FIFOSTATUS_5 0x94 | |
36 | #define MAILBOX_MSGSTATUS_0 0xc0 | |
37 | #define MAILBOX_MSGSTATUS_1 0xc4 | |
38 | #define MAILBOX_MSGSTATUS_2 0xc8 | |
39 | #define MAILBOX_MSGSTATUS_3 0xcc | |
40 | #define MAILBOX_MSGSTATUS_4 0xd0 | |
41 | #define MAILBOX_MSGSTATUS_5 0xd4 | |
42 | #define MAILBOX_IRQSTATUS_0 0x100 | |
43 | #define MAILBOX_IRQENABLE_0 0x104 | |
44 | #define MAILBOX_IRQSTATUS_1 0x108 | |
45 | #define MAILBOX_IRQENABLE_1 0x10c | |
46 | #define MAILBOX_IRQSTATUS_2 0x110 | |
47 | #define MAILBOX_IRQENABLE_2 0x114 | |
48 | #define MAILBOX_IRQSTATUS_3 0x118 | |
49 | #define MAILBOX_IRQENABLE_3 0x11c | |
50 | ||
51 | static unsigned long mbox_base; | |
52 | ||
53 | #define MAILBOX_IRQ_NOTFULL(n) (1 << (2 * (n) + 1)) | |
54 | #define MAILBOX_IRQ_NEWMSG(n) (1 << (2 * (n))) | |
55 | ||
56 | struct omap_mbox2_fifo { | |
57 | unsigned long msg; | |
58 | unsigned long fifo_stat; | |
59 | unsigned long msg_stat; | |
60 | }; | |
61 | ||
62 | struct omap_mbox2_priv { | |
63 | struct omap_mbox2_fifo tx_fifo; | |
64 | struct omap_mbox2_fifo rx_fifo; | |
65 | unsigned long irqenable; | |
66 | unsigned long irqstatus; | |
67 | u32 newmsg_bit; | |
68 | u32 notfull_bit; | |
69 | }; | |
70 | ||
71 | static struct clk *mbox_ick_handle; | |
72 | ||
73 | static inline unsigned int mbox_read_reg(unsigned int reg) | |
74 | { | |
75 | return __raw_readl(mbox_base + reg); | |
76 | } | |
77 | ||
78 | static inline void mbox_write_reg(unsigned int val, unsigned int reg) | |
79 | { | |
80 | __raw_writel(val, mbox_base + reg); | |
81 | } | |
82 | ||
83 | /* Mailbox H/W preparations */ | |
84 | static inline int omap2_mbox_startup(struct omap_mbox *mbox) | |
85 | { | |
86 | unsigned int l; | |
87 | ||
88 | mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); | |
89 | if (IS_ERR(mbox_ick_handle)) { | |
90 | printk("Could not get mailboxes_ick\n"); | |
91 | return -ENODEV; | |
92 | } | |
93 | clk_enable(mbox_ick_handle); | |
94 | ||
95 | /* set smart-idle & autoidle */ | |
96 | l = mbox_read_reg(MAILBOX_SYSCONFIG); | |
97 | l |= 0x00000011; | |
98 | mbox_write_reg(l, MAILBOX_SYSCONFIG); | |
99 | ||
100 | return 0; | |
101 | } | |
102 | ||
103 | static inline void omap2_mbox_shutdown(struct omap_mbox *mbox) | |
104 | { | |
105 | clk_disable(mbox_ick_handle); | |
106 | clk_put(mbox_ick_handle); | |
107 | } | |
108 | ||
109 | /* Mailbox FIFO handle functions */ | |
110 | static inline mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox) | |
111 | { | |
112 | struct omap_mbox2_fifo *fifo = | |
113 | &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo; | |
114 | return (mbox_msg_t) mbox_read_reg(fifo->msg); | |
115 | } | |
116 | ||
117 | static inline void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) | |
118 | { | |
119 | struct omap_mbox2_fifo *fifo = | |
120 | &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo; | |
121 | mbox_write_reg(msg, fifo->msg); | |
122 | } | |
123 | ||
124 | static inline int omap2_mbox_fifo_empty(struct omap_mbox *mbox) | |
125 | { | |
126 | struct omap_mbox2_fifo *fifo = | |
127 | &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo; | |
128 | return (mbox_read_reg(fifo->msg_stat) == 0); | |
129 | } | |
130 | ||
131 | static inline int omap2_mbox_fifo_full(struct omap_mbox *mbox) | |
132 | { | |
133 | struct omap_mbox2_fifo *fifo = | |
134 | &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo; | |
135 | return (mbox_read_reg(fifo->fifo_stat)); | |
136 | } | |
137 | ||
138 | /* Mailbox IRQ handle functions */ | |
139 | static inline void omap2_mbox_enable_irq(struct omap_mbox *mbox, | |
140 | omap_mbox_type_t irq) | |
141 | { | |
142 | struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; | |
143 | u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; | |
144 | ||
145 | l = mbox_read_reg(p->irqenable); | |
146 | l |= bit; | |
147 | mbox_write_reg(l, p->irqenable); | |
148 | } | |
149 | ||
150 | static inline void omap2_mbox_disable_irq(struct omap_mbox *mbox, | |
151 | omap_mbox_type_t irq) | |
152 | { | |
153 | struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; | |
154 | u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; | |
155 | ||
156 | l = mbox_read_reg(p->irqenable); | |
157 | l &= ~bit; | |
158 | mbox_write_reg(l, p->irqenable); | |
159 | } | |
160 | ||
161 | static inline void omap2_mbox_ack_irq(struct omap_mbox *mbox, | |
162 | omap_mbox_type_t irq) | |
163 | { | |
164 | struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; | |
165 | u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; | |
166 | ||
167 | mbox_write_reg(bit, p->irqstatus); | |
168 | } | |
169 | ||
170 | static inline int omap2_mbox_is_irq(struct omap_mbox *mbox, | |
171 | omap_mbox_type_t irq) | |
172 | { | |
173 | struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; | |
174 | u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; | |
175 | u32 enable = mbox_read_reg(p->irqenable); | |
176 | u32 status = mbox_read_reg(p->irqstatus); | |
177 | ||
178 | return (enable & status & bit); | |
179 | } | |
180 | ||
181 | static struct omap_mbox_ops omap2_mbox_ops = { | |
182 | .type = OMAP_MBOX_TYPE2, | |
183 | .startup = omap2_mbox_startup, | |
184 | .shutdown = omap2_mbox_shutdown, | |
185 | .fifo_read = omap2_mbox_fifo_read, | |
186 | .fifo_write = omap2_mbox_fifo_write, | |
187 | .fifo_empty = omap2_mbox_fifo_empty, | |
188 | .fifo_full = omap2_mbox_fifo_full, | |
189 | .enable_irq = omap2_mbox_enable_irq, | |
190 | .disable_irq = omap2_mbox_disable_irq, | |
191 | .ack_irq = omap2_mbox_ack_irq, | |
192 | .is_irq = omap2_mbox_is_irq, | |
193 | }; | |
194 | ||
195 | /* | |
196 | * MAILBOX 0: ARM -> DSP, | |
197 | * MAILBOX 1: ARM <- DSP. | |
198 | * MAILBOX 2: ARM -> IVA, | |
199 | * MAILBOX 3: ARM <- IVA. | |
200 | */ | |
201 | ||
202 | /* FIXME: the following structs should be filled automatically by the user id */ | |
203 | ||
204 | /* DSP */ | |
205 | static struct omap_mbox2_priv omap2_mbox_dsp_priv = { | |
206 | .tx_fifo = { | |
207 | .msg = MAILBOX_MESSAGE_0, | |
208 | .fifo_stat = MAILBOX_FIFOSTATUS_0, | |
209 | }, | |
210 | .rx_fifo = { | |
211 | .msg = MAILBOX_MESSAGE_1, | |
212 | .msg_stat = MAILBOX_MSGSTATUS_1, | |
213 | }, | |
214 | .irqenable = MAILBOX_IRQENABLE_0, | |
215 | .irqstatus = MAILBOX_IRQSTATUS_0, | |
216 | .notfull_bit = MAILBOX_IRQ_NOTFULL(0), | |
217 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(1), | |
218 | }; | |
219 | ||
220 | struct omap_mbox mbox_dsp_info = { | |
221 | .name = "dsp", | |
222 | .ops = &omap2_mbox_ops, | |
223 | .priv = &omap2_mbox_dsp_priv, | |
224 | }; | |
225 | EXPORT_SYMBOL(mbox_dsp_info); | |
226 | ||
227 | /* IVA */ | |
228 | static struct omap_mbox2_priv omap2_mbox_iva_priv = { | |
229 | .tx_fifo = { | |
230 | .msg = MAILBOX_MESSAGE_2, | |
231 | .fifo_stat = MAILBOX_FIFOSTATUS_2, | |
232 | }, | |
233 | .rx_fifo = { | |
234 | .msg = MAILBOX_MESSAGE_3, | |
235 | .msg_stat = MAILBOX_MSGSTATUS_3, | |
236 | }, | |
237 | .irqenable = MAILBOX_IRQENABLE_3, | |
238 | .irqstatus = MAILBOX_IRQSTATUS_3, | |
239 | .notfull_bit = MAILBOX_IRQ_NOTFULL(2), | |
240 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), | |
241 | }; | |
242 | ||
243 | static struct omap_mbox mbox_iva_info = { | |
244 | .name = "iva", | |
245 | .ops = &omap2_mbox_ops, | |
246 | .priv = &omap2_mbox_iva_priv, | |
247 | }; | |
248 | ||
249 | static int __init omap2_mbox_probe(struct platform_device *pdev) | |
250 | { | |
251 | struct resource *res; | |
252 | int ret = 0; | |
253 | ||
254 | if (pdev->num_resources != 3) { | |
255 | dev_err(&pdev->dev, "invalid number of resources: %d\n", | |
256 | pdev->num_resources); | |
257 | return -ENODEV; | |
258 | } | |
259 | ||
260 | /* MBOX base */ | |
261 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
262 | if (unlikely(!res)) { | |
263 | dev_err(&pdev->dev, "invalid mem resource\n"); | |
264 | return -ENODEV; | |
265 | } | |
266 | mbox_base = res->start; | |
267 | ||
268 | /* DSP IRQ */ | |
269 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
270 | if (unlikely(!res)) { | |
271 | dev_err(&pdev->dev, "invalid irq resource\n"); | |
272 | return -ENODEV; | |
273 | } | |
274 | mbox_dsp_info.irq = res->start; | |
275 | ||
276 | ret = omap_mbox_register(&mbox_dsp_info); | |
277 | ||
278 | /* IVA IRQ */ | |
279 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | |
280 | if (unlikely(!res)) { | |
281 | dev_err(&pdev->dev, "invalid irq resource\n"); | |
282 | return -ENODEV; | |
283 | } | |
284 | mbox_iva_info.irq = res->start; | |
285 | ||
286 | ret = omap_mbox_register(&mbox_iva_info); | |
287 | ||
288 | return ret; | |
289 | } | |
290 | ||
291 | static int omap2_mbox_remove(struct platform_device *pdev) | |
292 | { | |
293 | omap_mbox_unregister(&mbox_dsp_info); | |
294 | return 0; | |
295 | } | |
296 | ||
297 | static struct platform_driver omap2_mbox_driver = { | |
298 | .probe = omap2_mbox_probe, | |
299 | .remove = omap2_mbox_remove, | |
300 | .driver = { | |
301 | .name = "mailbox", | |
302 | }, | |
303 | }; | |
304 | ||
305 | static int __init omap2_mbox_init(void) | |
306 | { | |
307 | return platform_driver_register(&omap2_mbox_driver); | |
308 | } | |
309 | ||
310 | static void __exit omap2_mbox_exit(void) | |
311 | { | |
312 | platform_driver_unregister(&omap2_mbox_driver); | |
313 | } | |
314 | ||
315 | module_init(omap2_mbox_init); | |
316 | module_exit(omap2_mbox_exit); | |
317 | ||
318 | MODULE_LICENSE("GPL"); |