[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / hsmmc.c

/*
 * linux/arch/arm/mach-omap2/hsmmc.c
 *
 * Copyright (C) 2007-2008 Texas Instruments
 * Copyright (C) 2008 Nokia Corporation
 * Author: Texas Instruments
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <plat/mmc.h>
#include <plat/omap-pm.h>
#include <plat/mux.h>
#include <plat/omap_device.h>

#include "mux.h"
#include "hsmmc.h"
#include "control.h"

#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)

static u16 control_pbias_offset;
static u16 control_devconf1_offset;
static u16 control_mmc1;

#define HSMMC_NAME_LEN	9

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)

static int hsmmc_get_context_loss(struct device *dev)
{
	return omap_pm_get_dev_context_loss_count(dev);
}

#else
#define hsmmc_get_context_loss NULL
#endif

static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
				  int power_on, int vdd)
{
	u32 reg, prog_io;
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (mmc->slots[0].remux)
		mmc->slots[0].remux(dev, slot, power_on);

	/*
	 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
	 * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
	 * 1.8V and 3.0V modes, controlled by the PBIAS register.
	 *
	 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
	 * is most naturally TWL VSIM; those pins also use PBIAS.
	 *
	 * FIXME handle VMMC1A as needed ...
	 */
	if (power_on) {
		if (cpu_is_omap2430()) {
			reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
			if ((1 << vdd) >= MMC_VDD_30_31)
				reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
			else
				reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
			omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
		}

		if (mmc->slots[0].internal_clock) {
			reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
			reg |= OMAP2_MMCSDIO1ADPCLKISEL;
			omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
		}

		reg = omap_ctrl_readl(control_pbias_offset);
		if (cpu_is_omap3630()) {
			/* Set MMC I/O to 52Mhz */
			prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
			prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
			omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
		} else {
			reg |= OMAP2_PBIASSPEEDCTRL0;
		}
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	} else {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	}
}

static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
				 int power_on, int vdd)
{
	u32 reg;

	/* 100ms delay required for PBIAS configuration */
	msleep(100);

	if (power_on) {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
		if ((1 << vdd) <= MMC_VDD_165_195)
			reg &= ~OMAP2_PBIASLITEVMODE0;
		else
			reg |= OMAP2_PBIASLITEVMODE0;
		omap_ctrl_writel(reg, control_pbias_offset);
	} else {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
			OMAP2_PBIASLITEVMODE0);
		omap_ctrl_writel(reg, control_pbias_offset);
	}
}

static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
				  int power_on, int vdd)
{
	u32 reg;

	/*
	 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
	 * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
	 * 1.8V and 3.0V modes, controlled by the PBIAS register.
	 */
	reg = omap4_ctrl_pad_readl(control_pbias_offset);
	reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
		OMAP4_MMC1_PWRDNZ_MASK |
		OMAP4_MMC1_PBIASLITE_VMODE_MASK);
	omap4_ctrl_pad_writel(reg, control_pbias_offset);
}

static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
				 int power_on, int vdd)
{
	u32 reg;
	unsigned long timeout;

	if (power_on) {
		reg = omap4_ctrl_pad_readl(control_pbias_offset);
		reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
		if ((1 << vdd) <= MMC_VDD_165_195)
			reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
		else
			reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
		reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
			OMAP4_MMC1_PWRDNZ_MASK);
		omap4_ctrl_pad_writel(reg, control_pbias_offset);

		timeout = jiffies + msecs_to_jiffies(5);
		do {
			reg = omap4_ctrl_pad_readl(control_pbias_offset);
			if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
				break;
			usleep_range(100, 200);
		} while (!time_after(jiffies, timeout));

		if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
			pr_err("Pbias Voltage is not same as LDO\n");
			/* Caution : On VMODE_ERROR Power Down MMC IO */
			reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
			omap4_ctrl_pad_writel(reg, control_pbias_offset);
		}
	}
}

static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
{
	u32 reg;

	reg = omap_ctrl_readl(control_devconf1_offset);
	if (mmc->slots[0].internal_clock)
		reg |= OMAP2_MMCSDIO2ADPCLKISEL;
	else
		reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
	omap_ctrl_writel(reg, control_devconf1_offset);
}

static void hsmmc2_before_set_reg(struct device *dev, int slot,
				   int power_on, int vdd)
{
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (mmc->slots[0].remux)
		mmc->slots[0].remux(dev, slot, power_on);

	if (power_on)
		hsmmc2_select_input_clk_src(mmc);
}

static int am35x_hsmmc2_set_power(struct device *dev, int slot,
				  int power_on, int vdd)
{
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (power_on)
		hsmmc2_select_input_clk_src(mmc);

	return 0;
}

static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
							int vdd)
{
	return 0;
}

static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
			int controller_nr)
{
	if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
		(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
		omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
					OMAP_PIN_INPUT_PULLUP);
	if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
		(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
		omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
					OMAP_PIN_INPUT_PULLUP);
	if (cpu_is_omap34xx()) {
		if (controller_nr == 0) {
			omap_mux_init_signal("sdmmc1_clk",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc1_cmd",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc1_dat0",
				OMAP_PIN_INPUT_PULLUP);
			if (mmc_controller->slots[0].caps &
				(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
				omap_mux_init_signal("sdmmc1_dat1",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat2",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat3",
					OMAP_PIN_INPUT_PULLUP);
			}
			if (mmc_controller->slots[0].caps &
						MMC_CAP_8_BIT_DATA) {
				omap_mux_init_signal("sdmmc1_dat4",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat5",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat6",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc1_dat7",
					OMAP_PIN_INPUT_PULLUP);
			}
		}
		if (controller_nr == 1) {
			/* MMC2 */
			omap_mux_init_signal("sdmmc2_clk",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc2_cmd",
				OMAP_PIN_INPUT_PULLUP);
			omap_mux_init_signal("sdmmc2_dat0",
				OMAP_PIN_INPUT_PULLUP);

			/*
			 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
			 * need to be muxed in the board-*.c files
			 */
			if (mmc_controller->slots[0].caps &
				(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
				omap_mux_init_signal("sdmmc2_dat1",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat2",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat3",
					OMAP_PIN_INPUT_PULLUP);
			}
			if (mmc_controller->slots[0].caps &
							MMC_CAP_8_BIT_DATA) {
				omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
					OMAP_PIN_INPUT_PULLUP);
				omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
					OMAP_PIN_INPUT_PULLUP);
			}
		}

		/*
		 * For MMC3 the pins need to be muxed in the board-*.c files
		 */
	}
}

static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
					struct omap_mmc_platform_data *mmc)
{
	char *hc_name;

	hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
	if (!hc_name) {
		pr_err("Cannot allocate memory for controller slot name\n");
		kfree(hc_name);
		return -ENOMEM;
	}

	if (c->name)
		strncpy(hc_name, c->name, HSMMC_NAME_LEN);
	else
		snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
								c->mmc, 1);
	mmc->slots[0].name = hc_name;
	mmc->nr_slots = 1;
	mmc->slots[0].caps = c->caps;
	mmc->slots[0].pm_caps = c->pm_caps;
	mmc->slots[0].internal_clock = !c->ext_clock;
	mmc->dma_mask = 0xffffffff;
	mmc->max_freq = c->max_freq;
	if (cpu_is_omap44xx())
		mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
	else
		mmc->reg_offset = 0;

	mmc->get_context_loss_count = hsmmc_get_context_loss;

	mmc->slots[0].switch_pin = c->gpio_cd;
	mmc->slots[0].gpio_wp = c->gpio_wp;

	mmc->slots[0].remux = c->remux;
	mmc->slots[0].init_card = c->init_card;

	if (c->cover_only)
		mmc->slots[0].cover = 1;

	if (c->nonremovable)
		mmc->slots[0].nonremovable = 1;

	if (c->power_saving)
		mmc->slots[0].power_saving = 1;

	if (c->no_off)
		mmc->slots[0].no_off = 1;

	if (c->no_off_init)
		mmc->slots[0].no_regulator_off_init = c->no_off_init;

	if (c->vcc_aux_disable_is_sleep)
		mmc->slots[0].vcc_aux_disable_is_sleep = 1;

	/*
	 * NOTE:  MMC slots should have a Vcc regulator set up.
	 * This may be from a TWL4030-family chip, another
	 * controllable regulator, or a fixed supply.
	 *
	 * temporary HACK: ocr_mask instead of fixed supply
	 */
	if (cpu_is_omap3505() || cpu_is_omap3517())
		mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
					 MMC_VDD_26_27 |
					 MMC_VDD_27_28 |
					 MMC_VDD_29_30 |
					 MMC_VDD_30_31 |
					 MMC_VDD_31_32;
	else
		mmc->slots[0].ocr_mask = c->ocr_mask;

	if (!cpu_is_omap3517() && !cpu_is_omap3505())
		mmc->slots[0].features |= HSMMC_HAS_PBIAS;

	if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
		mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;

	switch (c->mmc) {
	case 1:
		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
			/* on-chip level shifting via PBIAS0/PBIAS1 */
			if (cpu_is_omap44xx()) {
				mmc->slots[0].before_set_reg =
						omap4_hsmmc1_before_set_reg;
				mmc->slots[0].after_set_reg =
						omap4_hsmmc1_after_set_reg;
			} else {
				mmc->slots[0].before_set_reg =
						omap_hsmmc1_before_set_reg;
				mmc->slots[0].after_set_reg =
						omap_hsmmc1_after_set_reg;
			}
		}

		if (cpu_is_omap3517() || cpu_is_omap3505())
			mmc->slots[0].set_power = nop_mmc_set_power;

		/* OMAP3630 HSMMC1 supports only 4-bit */
		if (cpu_is_omap3630() &&
				(c->caps & MMC_CAP_8_BIT_DATA)) {
			c->caps &= ~MMC_CAP_8_BIT_DATA;
			c->caps |= MMC_CAP_4_BIT_DATA;
			mmc->slots[0].caps = c->caps;
		}
		break;
	case 2:
		if (cpu_is_omap3517() || cpu_is_omap3505())
			mmc->slots[0].set_power = am35x_hsmmc2_set_power;

		if (c->ext_clock)
			c->transceiver = 1;
		if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
			c->caps &= ~MMC_CAP_8_BIT_DATA;
			c->caps |= MMC_CAP_4_BIT_DATA;
		}
		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
			/* off-chip level shifting, or none */
			mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
			mmc->slots[0].after_set_reg = NULL;
		}
		break;
	case 3:
	case 4:
	case 5:
		mmc->slots[0].before_set_reg = NULL;
		mmc->slots[0].after_set_reg = NULL;
		break;
	default:
		pr_err("MMC%d configuration not supported!\n", c->mmc);
		kfree(hc_name);
		return -ENODEV;
	}
	return 0;
}

static int omap_hsmmc_done;

void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
{
	struct platform_device *pdev;
	struct omap_mmc_platform_data *mmc_pdata;
	int res;

	if (omap_hsmmc_done != 1)
		return;

	omap_hsmmc_done++;

	for (; c->mmc; c++) {
		if (!c->deferred)
			continue;

		pdev = c->pdev;
		if (!pdev)
			continue;

		mmc_pdata = pdev->dev.platform_data;
		if (!mmc_pdata)
			continue;

		mmc_pdata->slots[0].switch_pin = c->gpio_cd;
		mmc_pdata->slots[0].gpio_wp = c->gpio_wp;

		res = omap_device_register(pdev);
		if (res)
			pr_err("Could not late init MMC %s\n",
			       c->name);
	}
}

#define MAX_OMAP_MMC_HWMOD_NAME_LEN		16

static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
					int ctrl_nr)
{
	struct omap_hwmod *oh;
	struct omap_hwmod *ohs[1];
	struct omap_device *od;
	struct platform_device *pdev;
	char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
	struct omap_mmc_platform_data *mmc_data;
	struct omap_mmc_dev_attr *mmc_dev_attr;
	char *name;
	int res;

	mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
	if (!mmc_data) {
		pr_err("Cannot allocate memory for mmc device!\n");
		return;
	}

	res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
	if (res < 0)
		goto free_mmc;

	omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));

	name = "omap_hsmmc";
	res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
		     "mmc%d", ctrl_nr);
	WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
	     "String buffer overflow in MMC%d device setup\n", ctrl_nr);

	oh = omap_hwmod_lookup(oh_name);
	if (!oh) {
		pr_err("Could not look up %s\n", oh_name);
		goto free_name;
	}
	ohs[0] = oh;
	if (oh->dev_attr != NULL) {
		mmc_dev_attr = oh->dev_attr;
		mmc_data->controller_flags = mmc_dev_attr->flags;
		/*
		 * erratum 2.1.1.128 doesn't apply if board has
		 * a transceiver is attached
		 */
		if (hsmmcinfo->transceiver)
			mmc_data->controller_flags &=
				~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
	}

	pdev = platform_device_alloc(name, ctrl_nr - 1);
	if (!pdev) {
		pr_err("Could not allocate pdev for %s\n", name);
		goto free_name;
	}
	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);

	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
	if (!od) {
		pr_err("Could not allocate od for %s\n", name);
		goto put_pdev;
	}

	res = platform_device_add_data(pdev, mmc_data,
			      sizeof(struct omap_mmc_platform_data));
	if (res) {
		pr_err("Could not add pdata for %s\n", name);
		goto put_pdev;
	}

	hsmmcinfo->pdev = pdev;

	if (hsmmcinfo->deferred)
		goto free_mmc;

	res = omap_device_register(pdev);
	if (res) {
		pr_err("Could not register od for %s\n", name);
		goto free_od;
	}

	goto free_mmc;

free_od:
	omap_device_delete(od);

put_pdev:
	platform_device_put(pdev);

free_name:
	kfree(mmc_data->slots[0].name);

free_mmc:
	kfree(mmc_data);
}

void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	u32 reg;

	if (omap_hsmmc_done)
		return;

	omap_hsmmc_done = 1;

	if (!cpu_is_omap44xx()) {
		if (cpu_is_omap2430()) {
			control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
		} else {
			control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
		}
	} else {
		control_pbias_offset =
			OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
		control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
		reg = omap4_ctrl_pad_readl(control_mmc1);
		reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
		reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
		reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
			OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
			OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
		omap4_ctrl_pad_writel(reg, control_mmc1);
	}

	for (; controllers->mmc; controllers++)
		omap_hsmmc_init_one(controllers, controllers->mmc);

}

#endif
Commit	Line	Data
90c62bf0	1	/*
d02a900b	2	* linux/arch/arm/mach-omap2/hsmmc.c
90c62bf0 TL	3	*
	4	* Copyright (C) 2007-2008 Texas Instruments
	5	* Copyright (C) 2008 Nokia Corporation
	6	* Author: Texas Instruments
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
db0fefc5 AH	12	#include <linux/kernel.h>
	13	#include <linux/slab.h>
	14	#include <linux/string.h>
90c62bf0	15	#include <linux/delay.h>
5e4698fc	16	#include <linux/gpio.h>
90c62bf0	17	#include <mach/hardware.h>
ce491cf8	18	#include <plat/mmc.h>
e3df0fb4	19	#include <plat/omap-pm.h>
d8d0a61c	20	#include <plat/mux.h>
4621d5f8	21	#include <plat/omap_device.h>
90c62bf0	22
d8d0a61c	23	#include "mux.h"
d02a900b	24	#include "hsmmc.h"
4814ced5	25	#include "control.h"
90c62bf0	26
db0fefc5	27	#if defined(CONFIG_MMC_OMAP_HS) \|\| defined(CONFIG_MMC_OMAP_HS_MODULE)
90c62bf0 TL	28
	29	static u16 control_pbias_offset;
	30	static u16 control_devconf1_offset;
c83c8e6c	31	static u16 control_mmc1;
90c62bf0 TL	32
	33	#define HSMMC_NAME_LEN 9
	34
1887bde3 DK	35	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
1887bde3 DK	36
68ff0423	37	static int hsmmc_get_context_loss(struct device *dev)
1887bde3	38	{
e3df0fb4	39	return omap_pm_get_dev_context_loss_count(dev);
1887bde3 DK	40	}
	41
	42	#else
68ff0423	43	#define hsmmc_get_context_loss NULL
1887bde3 DK	44	#endif
1887bde3 DK	45
c83c8e6c	46	static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
db0fefc5	47	int power_on, int vdd)
90c62bf0	48	{
555d503f	49	u32 reg, prog_io;
90c62bf0 TL	50	struct omap_mmc_platform_data *mmc = dev->platform_data;
90c62bf0 TL	51
ce6f0016 AH	52	if (mmc->slots[0].remux)
	53	mmc->slots[0].remux(dev, slot, power_on);
	54
0329c377 DB	55	/*
0329c377 DB	56	* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
b583f26d	57	* card with Vcc regulator (from twl4030 or whatever). OMAP has both
0329c377 DB	58	* 1.8V and 3.0V modes, controlled by the PBIAS register.
	59	*
	60	* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
	61	* is most naturally TWL VSIM; those pins also use PBIAS.
b583f26d DB	62	*
b583f26d DB	63	* FIXME handle VMMC1A as needed ...
0329c377	64	*/
90c62bf0 TL	65	if (power_on) {
	66	if (cpu_is_omap2430()) {
	67	reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
	68	if ((1 << vdd) >= MMC_VDD_30_31)
	69	reg \|= OMAP243X_MMC1_ACTIVE_OVERWRITE;
	70	else
	71	reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
	72	omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
	73	}
	74
	75	if (mmc->slots[0].internal_clock) {
	76	reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
	77	reg \|= OMAP2_MMCSDIO1ADPCLKISEL;
	78	omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
	79	}
	80
	81	reg = omap_ctrl_readl(control_pbias_offset);
555d503f M	82	if (cpu_is_omap3630()) {
	83	/* Set MMC I/O to 52Mhz */
	84	prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
	85	prog_io \|= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
	86	omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
	87	} else {
	88	reg \|= OMAP2_PBIASSPEEDCTRL0;
	89	}
90c62bf0 TL	90	reg &= ~OMAP2_PBIASLITEPWRDNZ0;
90c62bf0 TL	91	omap_ctrl_writel(reg, control_pbias_offset);
db0fefc5 AH	92	} else {
	93	reg = omap_ctrl_readl(control_pbias_offset);
	94	reg &= ~OMAP2_PBIASLITEPWRDNZ0;
	95	omap_ctrl_writel(reg, control_pbias_offset);
	96	}
	97	}
	98
c83c8e6c	99	static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
db0fefc5 AH	100	int power_on, int vdd)
	101	{
	102	u32 reg;
90c62bf0	103
db0fefc5 AH	104	/* 100ms delay required for PBIAS configuration */
db0fefc5 AH	105	msleep(100);
90c62bf0	106
db0fefc5	107	if (power_on) {
90c62bf0 TL	108	reg = omap_ctrl_readl(control_pbias_offset);
	109	reg \|= (OMAP2_PBIASLITEPWRDNZ0 \| OMAP2_PBIASSPEEDCTRL0);
	110	if ((1 << vdd) <= MMC_VDD_165_195)
	111	reg &= ~OMAP2_PBIASLITEVMODE0;
	112	else
	113	reg \|= OMAP2_PBIASLITEVMODE0;
	114	omap_ctrl_writel(reg, control_pbias_offset);
	115	} else {
90c62bf0 TL	116	reg = omap_ctrl_readl(control_pbias_offset);
	117	reg \|= (OMAP2_PBIASSPEEDCTRL0 \| OMAP2_PBIASLITEPWRDNZ0 \|
	118	OMAP2_PBIASLITEVMODE0);
	119	omap_ctrl_writel(reg, control_pbias_offset);
	120	}
90c62bf0 TL	121	}
90c62bf0 TL	122
c83c8e6c	123	static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
	124	int power_on, int vdd)
	125	{
	126	u32 reg;
	127
	128	/*
	129	* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
	130	* card with Vcc regulator (from twl4030 or whatever). OMAP has both
	131	* 1.8V and 3.0V modes, controlled by the PBIAS register.
c83c8e6c	132	*/
dcf5ef3f SS	133	reg = omap4_ctrl_pad_readl(control_pbias_offset);
dcf5ef3f SS	134	reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK \|
ff2beb1d B	135	OMAP4_MMC1_PWRDNZ_MASK \|
ff2beb1d B	136	OMAP4_MMC1_PBIASLITE_VMODE_MASK);
dcf5ef3f	137	omap4_ctrl_pad_writel(reg, control_pbias_offset);
c83c8e6c	138	}
	139
	140	static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
	141	int power_on, int vdd)
	142	{
	143	u32 reg;
1fcecf28	144	unsigned long timeout;
c83c8e6c	145
c83c8e6c	146	if (power_on) {
dcf5ef3f SS	147	reg = omap4_ctrl_pad_readl(control_pbias_offset);
dcf5ef3f SS	148	reg \|= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
c83c8e6c	149	if ((1 << vdd) <= MMC_VDD_165_195)
dcf5ef3f	150	reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
c83c8e6c	151	else
dcf5ef3f SS	152	reg \|= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
dcf5ef3f SS	153	reg \|= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK \|
3696d303	154	OMAP4_MMC1_PWRDNZ_MASK);
dcf5ef3f	155	omap4_ctrl_pad_writel(reg, control_pbias_offset);
1fcecf28 B	156
	157	timeout = jiffies + msecs_to_jiffies(5);
	158	do {
	159	reg = omap4_ctrl_pad_readl(control_pbias_offset);
	160	if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
	161	break;
	162	usleep_range(100, 200);
	163	} while (!time_after(jiffies, timeout));
	164
dcf5ef3f	165	if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
c83c8e6c	166	pr_err("Pbias Voltage is not same as LDO\n");
c83c8e6c	167	/* Caution : On VMODE_ERROR Power Down MMC IO */
3696d303	168	reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
dcf5ef3f	169	omap4_ctrl_pad_writel(reg, control_pbias_offset);
c83c8e6c	170	}
c83c8e6c	171	}
	172	}
	173
e62245ba IG	174	static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
	175	{
	176	u32 reg;
	177
d82e5190 GI	178	reg = omap_ctrl_readl(control_devconf1_offset);
d82e5190 GI	179	if (mmc->slots[0].internal_clock)
e62245ba	180	reg \|= OMAP2_MMCSDIO2ADPCLKISEL;
d82e5190 GI	181	else
	182	reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
	183	omap_ctrl_writel(reg, control_devconf1_offset);
e62245ba IG	184	}
e62245ba IG	185
ffa1e4ed	186	static void hsmmc2_before_set_reg(struct device *dev, int slot,
db0fefc5	187	int power_on, int vdd)
90c62bf0	188	{
90c62bf0	189	struct omap_mmc_platform_data *mmc = dev->platform_data;
b583f26d	190
ce6f0016 AH	191	if (mmc->slots[0].remux)
	192	mmc->slots[0].remux(dev, slot, power_on);
	193
e62245ba IG	194	if (power_on)
	195	hsmmc2_select_input_clk_src(mmc);
	196	}
90c62bf0	197
e62245ba IG	198	static int am35x_hsmmc2_set_power(struct device *dev, int slot,
	199	int power_on, int vdd)
	200	{
	201	struct omap_mmc_platform_data *mmc = dev->platform_data;
	202
	203	if (power_on)
	204	hsmmc2_select_input_clk_src(mmc);
	205
	206	return 0;
9b7c18e0 AH	207	}
9b7c18e0 AH	208
03e7e170	209	static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
	210	int vdd)
	211	{
	212	return 0;
	213	}
	214
d8d0a61c KK	215	static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
	216	int controller_nr)
	217	{
a15164f1 TW	218	if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
a15164f1 TW	219	(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
d8d0a61c KK	220	omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
d8d0a61c KK	221	OMAP_PIN_INPUT_PULLUP);
a15164f1 TW	222	if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
a15164f1 TW	223	(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
d8d0a61c KK	224	omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
	225	OMAP_PIN_INPUT_PULLUP);
	226	if (cpu_is_omap34xx()) {
	227	if (controller_nr == 0) {
	228	omap_mux_init_signal("sdmmc1_clk",
	229	OMAP_PIN_INPUT_PULLUP);
	230	omap_mux_init_signal("sdmmc1_cmd",
	231	OMAP_PIN_INPUT_PULLUP);
	232	omap_mux_init_signal("sdmmc1_dat0",
	233	OMAP_PIN_INPUT_PULLUP);
	234	if (mmc_controller->slots[0].caps &
	235	(MMC_CAP_4_BIT_DATA \| MMC_CAP_8_BIT_DATA)) {
	236	omap_mux_init_signal("sdmmc1_dat1",
	237	OMAP_PIN_INPUT_PULLUP);
	238	omap_mux_init_signal("sdmmc1_dat2",
	239	OMAP_PIN_INPUT_PULLUP);
	240	omap_mux_init_signal("sdmmc1_dat3",
	241	OMAP_PIN_INPUT_PULLUP);
	242	}
	243	if (mmc_controller->slots[0].caps &
	244	MMC_CAP_8_BIT_DATA) {
	245	omap_mux_init_signal("sdmmc1_dat4",
	246	OMAP_PIN_INPUT_PULLUP);
	247	omap_mux_init_signal("sdmmc1_dat5",
	248	OMAP_PIN_INPUT_PULLUP);
	249	omap_mux_init_signal("sdmmc1_dat6",
	250	OMAP_PIN_INPUT_PULLUP);
	251	omap_mux_init_signal("sdmmc1_dat7",
	252	OMAP_PIN_INPUT_PULLUP);
	253	}
	254	}
	255	if (controller_nr == 1) {
	256	/* MMC2 */
	257	omap_mux_init_signal("sdmmc2_clk",
	258	OMAP_PIN_INPUT_PULLUP);
	259	omap_mux_init_signal("sdmmc2_cmd",
	260	OMAP_PIN_INPUT_PULLUP);
	261	omap_mux_init_signal("sdmmc2_dat0",
	262	OMAP_PIN_INPUT_PULLUP);
	263
	264	/*
	265	* For 8 wire configurations, Lines DAT4, 5, 6 and 7
	266	* need to be muxed in the board-*.c files
	267	*/
	268	if (mmc_controller->slots[0].caps &
	269	(MMC_CAP_4_BIT_DATA \| MMC_CAP_8_BIT_DATA)) {
	270	omap_mux_init_signal("sdmmc2_dat1",
	271	OMAP_PIN_INPUT_PULLUP);
	272	omap_mux_init_signal("sdmmc2_dat2",
	273	OMAP_PIN_INPUT_PULLUP);
	274	omap_mux_init_signal("sdmmc2_dat3",
	275	OMAP_PIN_INPUT_PULLUP);
	276	}
	277	if (mmc_controller->slots[0].caps &
	278	MMC_CAP_8_BIT_DATA) {
	279	omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
	280	OMAP_PIN_INPUT_PULLUP);
	281	omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
	282	OMAP_PIN_INPUT_PULLUP);
	283	omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
	284	OMAP_PIN_INPUT_PULLUP);
	285	omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
	286	OMAP_PIN_INPUT_PULLUP);
	287	}
288	}
289
290	/*
291	* For MMC3 the pins need to be muxed in the board-*.c files
292	*/
293	}
294	}
295
d1589f09 TL	296	static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
d1589f09 TL	297	struct omap_mmc_platform_data *mmc)
4621d5f8 KK	298	{
	299	char *hc_name;
	300
	301	hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
	302	if (!hc_name) {
	303	pr_err("Cannot allocate memory for controller slot name\n");
	304	kfree(hc_name);
	305	return -ENOMEM;
	306	}
	307
	308	if (c->name)
	309	strncpy(hc_name, c->name, HSMMC_NAME_LEN);
	310	else
	311	snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
	312	c->mmc, 1);
	313	mmc->slots[0].name = hc_name;
	314	mmc->nr_slots = 1;
	315	mmc->slots[0].caps = c->caps;
6fdc75de	316	mmc->slots[0].pm_caps = c->pm_caps;
4621d5f8 KK	317	mmc->slots[0].internal_clock = !c->ext_clock;
4621d5f8 KK	318	mmc->dma_mask = 0xffffffff;
d418ed87	319	mmc->max_freq = c->max_freq;
4621d5f8 KK	320	if (cpu_is_omap44xx())
	321	mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
	322	else
	323	mmc->reg_offset = 0;
	324
	325	mmc->get_context_loss_count = hsmmc_get_context_loss;
	326
	327	mmc->slots[0].switch_pin = c->gpio_cd;
	328	mmc->slots[0].gpio_wp = c->gpio_wp;
	329
	330	mmc->slots[0].remux = c->remux;
	331	mmc->slots[0].init_card = c->init_card;
	332
	333	if (c->cover_only)
	334	mmc->slots[0].cover = 1;
	335
	336	if (c->nonremovable)
	337	mmc->slots[0].nonremovable = 1;
	338
	339	if (c->power_saving)
	340	mmc->slots[0].power_saving = 1;
	341
	342	if (c->no_off)
	343	mmc->slots[0].no_off = 1;
	344
b1c1df7a B	345	if (c->no_off_init)
	346	mmc->slots[0].no_regulator_off_init = c->no_off_init;
	347
4621d5f8 KK	348	if (c->vcc_aux_disable_is_sleep)
	349	mmc->slots[0].vcc_aux_disable_is_sleep = 1;
	350
	351	/*
	352	* NOTE: MMC slots should have a Vcc regulator set up.
	353	* This may be from a TWL4030-family chip, another
	354	* controllable regulator, or a fixed supply.
	355	*
	356	* temporary HACK: ocr_mask instead of fixed supply
	357	*/
e89715a7 A	358	if (cpu_is_omap3505() \|\| cpu_is_omap3517())
	359	mmc->slots[0].ocr_mask = MMC_VDD_165_195 \|
	360	MMC_VDD_26_27 \|
	361	MMC_VDD_27_28 \|
	362	MMC_VDD_29_30 \|
	363	MMC_VDD_30_31 \|
	364	MMC_VDD_31_32;
	365	else
	366	mmc->slots[0].ocr_mask = c->ocr_mask;
4621d5f8	367
e62245ba	368	if (!cpu_is_omap3517() && !cpu_is_omap3505())
4621d5f8 KK	369	mmc->slots[0].features \|= HSMMC_HAS_PBIAS;
	370
	371	if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
	372	mmc->slots[0].features \|= HSMMC_HAS_UPDATED_RESET;
	373
	374	switch (c->mmc) {
	375	case 1:
	376	if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
	377	/* on-chip level shifting via PBIAS0/PBIAS1 */
	378	if (cpu_is_omap44xx()) {
	379	mmc->slots[0].before_set_reg =
	380	omap4_hsmmc1_before_set_reg;
	381	mmc->slots[0].after_set_reg =
	382	omap4_hsmmc1_after_set_reg;
	383	} else {
	384	mmc->slots[0].before_set_reg =
	385	omap_hsmmc1_before_set_reg;
	386	mmc->slots[0].after_set_reg =
	387	omap_hsmmc1_after_set_reg;
	388	}
	389	}
	390
e62245ba IG	391	if (cpu_is_omap3517() \|\| cpu_is_omap3505())
	392	mmc->slots[0].set_power = nop_mmc_set_power;
	393
4621d5f8 KK	394	/* OMAP3630 HSMMC1 supports only 4-bit */
	395	if (cpu_is_omap3630() &&
	396	(c->caps & MMC_CAP_8_BIT_DATA)) {
	397	c->caps &= ~MMC_CAP_8_BIT_DATA;
	398	c->caps \|= MMC_CAP_4_BIT_DATA;
	399	mmc->slots[0].caps = c->caps;
	400	}
	401	break;
	402	case 2:
e62245ba IG	403	if (cpu_is_omap3517() \|\| cpu_is_omap3505())
	404	mmc->slots[0].set_power = am35x_hsmmc2_set_power;
	405
4621d5f8 KK	406	if (c->ext_clock)
	407	c->transceiver = 1;
	408	if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
	409	c->caps &= ~MMC_CAP_8_BIT_DATA;
	410	c->caps \|= MMC_CAP_4_BIT_DATA;
	411	}
4621d5f8 KK	412	if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
4621d5f8 KK	413	/* off-chip level shifting, or none */
ffa1e4ed	414	mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
4621d5f8 KK	415	mmc->slots[0].after_set_reg = NULL;
	416	}
	417	break;
ffa1e4ed	418	case 3:
4621d5f8 KK	419	case 4:
	420	case 5:
	421	mmc->slots[0].before_set_reg = NULL;
	422	mmc->slots[0].after_set_reg = NULL;
	423	break;
	424	default:
	425	pr_err("MMC%d configuration not supported!\n", c->mmc);
	426	kfree(hc_name);
	427	return -ENODEV;
	428	}
	429	return 0;
	430	}
	431
97899e55	432	static int omap_hsmmc_done;
3b972bf0 TL	433
	434	void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
	435	{
	436	struct platform_device *pdev;
	437	struct omap_mmc_platform_data *mmc_pdata;
	438	int res;
	439
	440	if (omap_hsmmc_done != 1)
	441	return;
	442
	443	omap_hsmmc_done++;
	444
	445	for (; c->mmc; c++) {
	446	if (!c->deferred)
	447	continue;
	448
	449	pdev = c->pdev;
	450	if (!pdev)
	451	continue;
	452
	453	mmc_pdata = pdev->dev.platform_data;
	454	if (!mmc_pdata)
	455	continue;
	456
	457	mmc_pdata->slots[0].switch_pin = c->gpio_cd;
	458	mmc_pdata->slots[0].gpio_wp = c->gpio_wp;
	459
	460	res = omap_device_register(pdev);
	461	if (res)
	462	pr_err("Could not late init MMC %s\n",
	463	c->name);
	464	}
	465	}
	466
4621d5f8 KK	467	#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
4621d5f8 KK	468
6028505c	469	static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
3b972bf0	470	int ctrl_nr)
4621d5f8 KK	471	{
4621d5f8 KK	472	struct omap_hwmod *oh;
3b972bf0 TL	473	struct omap_hwmod *ohs[1];
3b972bf0 TL	474	struct omap_device *od;
3528c58e	475	struct platform_device *pdev;
4621d5f8 KK	476	char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
	477	struct omap_mmc_platform_data *mmc_data;
	478	struct omap_mmc_dev_attr *mmc_dev_attr;
	479	char *name;
3b972bf0	480	int res;
4621d5f8 KK	481
	482	mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
	483	if (!mmc_data) {
	484	pr_err("Cannot allocate memory for mmc device!\n");
3b972bf0	485	return;
4621d5f8 KK	486	}
4621d5f8 KK	487
3b972bf0 TL	488	res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
	489	if (res < 0)
	490	goto free_mmc;
	491
4621d5f8 KK	492	omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
4621d5f8 KK	493
0005ae73	494	name = "omap_hsmmc";
3b972bf0	495	res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
4621d5f8	496	"mmc%d", ctrl_nr);
3b972bf0	497	WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
4621d5f8	498	"String buffer overflow in MMC%d device setup\n", ctrl_nr);
3b972bf0	499
4621d5f8 KK	500	oh = omap_hwmod_lookup(oh_name);
	501	if (!oh) {
	502	pr_err("Could not look up %s\n", oh_name);
3b972bf0	503	goto free_name;
4621d5f8	504	}
3b972bf0	505	ohs[0] = oh;
4621d5f8 KK	506	if (oh->dev_attr != NULL) {
	507	mmc_dev_attr = oh->dev_attr;
	508	mmc_data->controller_flags = mmc_dev_attr->flags;
26c547fd GI	509	/*
	510	* erratum 2.1.1.128 doesn't apply if board has
	511	* a transceiver is attached
	512	*/
	513	if (hsmmcinfo->transceiver)
	514	mmc_data->controller_flags &=
	515	~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
4621d5f8 KK	516	}
4621d5f8 KK	517
3b972bf0 TL	518	pdev = platform_device_alloc(name, ctrl_nr - 1);
	519	if (!pdev) {
	520	pr_err("Could not allocate pdev for %s\n", name);
	521	goto free_name;
4621d5f8	522	}
3b972bf0 TL	523	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	524
	525	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
	526	if (!od) {
	527	pr_err("Could not allocate od for %s\n", name);
	528	goto put_pdev;
	529	}
	530
	531	res = platform_device_add_data(pdev, mmc_data,
	532	sizeof(struct omap_mmc_platform_data));
	533	if (res) {
	534	pr_err("Could not add pdata for %s\n", name);
	535	goto put_pdev;
	536	}
	537
	538	hsmmcinfo->pdev = pdev;
	539
	540	if (hsmmcinfo->deferred)
	541	goto free_mmc;
	542
	543	res = omap_device_register(pdev);
	544	if (res) {
	545	pr_err("Could not register od for %s\n", name);
	546	goto free_od;
	547	}
	548
	549	goto free_mmc;
	550
	551	free_od:
	552	omap_device_delete(od);
	553
	554	put_pdev:
	555	platform_device_put(pdev);
	556
	557	free_name:
	558	kfree(mmc_data->slots[0].name);
4621d5f8	559
3b972bf0	560	free_mmc:
4621d5f8 KK	561	kfree(mmc_data);
4621d5f8 KK	562	}
90c62bf0	563
d1589f09	564	void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
90c62bf0	565	{
c83c8e6c	566	u32 reg;
90c62bf0	567
97899e55 TL	568	if (omap_hsmmc_done)
	569	return;
	570
	571	omap_hsmmc_done = 1;
	572
c83c8e6c	573	if (!cpu_is_omap44xx()) {
	574	if (cpu_is_omap2430()) {
	575	control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
	576	control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
	577	} else {
	578	control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
	579	control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
	580	}
90c62bf0	581	} else {
dcf5ef3f SS	582	control_pbias_offset =
	583	OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
	584	control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
	585	reg = omap4_ctrl_pad_readl(control_mmc1);
	586	reg \|= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK \|
	587	OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
	588	reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK \|
	589	OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
c862dd70	590	reg \|= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK \|
dcf5ef3f SS	591	OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK \|
	592	OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
	593	omap4_ctrl_pad_writel(reg, control_mmc1);
90c62bf0 TL	594	}
90c62bf0 TL	595
4621d5f8	596	for (; controllers->mmc; controllers++)
3b972bf0	597	omap_hsmmc_init_one(controllers, controllers->mmc);
01971f65	598
90c62bf0 TL	599	}
	600
	601	#endif