Commit | Line | Data |
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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/devices.c | |
3 | * | |
4 | * OMAP2 platform device setup/initialization | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
1dbae815 TL |
12 | #include <linux/module.h> |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/platform_device.h> | |
fced80c7 | 16 | #include <linux/io.h> |
1dbae815 | 17 | |
a09e64fb | 18 | #include <mach/hardware.h> |
1dbae815 TL |
19 | #include <asm/mach-types.h> |
20 | #include <asm/mach/map.h> | |
21 | ||
90c62bf0 | 22 | #include <mach/control.h> |
a09e64fb RK |
23 | #include <mach/tc.h> |
24 | #include <mach/board.h> | |
25 | #include <mach/mux.h> | |
26 | #include <mach/gpio.h> | |
646e3ed1 | 27 | #include <mach/eac.h> |
d8874665 | 28 | #include <mach/mmc.h> |
1dbae815 | 29 | |
c40fae95 TL |
30 | #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) |
31 | #define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE) | |
32 | ||
33 | static struct resource mbox_resources[] = { | |
34 | { | |
35 | .start = OMAP2_MBOX_BASE, | |
36 | .end = OMAP2_MBOX_BASE + 0x11f, | |
37 | .flags = IORESOURCE_MEM, | |
38 | }, | |
39 | { | |
40 | .start = INT_24XX_MAIL_U0_MPU, | |
41 | .flags = IORESOURCE_IRQ, | |
42 | }, | |
43 | { | |
44 | .start = INT_24XX_MAIL_U3_MPU, | |
45 | .flags = IORESOURCE_IRQ, | |
46 | }, | |
47 | }; | |
48 | ||
49 | static struct platform_device mbox_device = { | |
50 | .name = "mailbox", | |
51 | .id = -1, | |
52 | .num_resources = ARRAY_SIZE(mbox_resources), | |
53 | .resource = mbox_resources, | |
54 | }; | |
55 | ||
56 | static inline void omap_init_mbox(void) | |
57 | { | |
58 | platform_device_register(&mbox_device); | |
59 | } | |
60 | #else | |
61 | static inline void omap_init_mbox(void) { } | |
62 | #endif | |
63 | ||
9b6553cd TL |
64 | #if defined(CONFIG_OMAP_STI) |
65 | ||
646e3ed1 TL |
66 | #if defined(CONFIG_ARCH_OMAP2) |
67 | ||
68 | #define OMAP2_STI_BASE 0x48068000 | |
9b6553cd TL |
69 | #define OMAP2_STI_CHANNEL_BASE 0x54000000 |
70 | #define OMAP2_STI_IRQ 4 | |
71 | ||
72 | static struct resource sti_resources[] = { | |
73 | { | |
74 | .start = OMAP2_STI_BASE, | |
75 | .end = OMAP2_STI_BASE + 0x7ff, | |
76 | .flags = IORESOURCE_MEM, | |
77 | }, | |
78 | { | |
79 | .start = OMAP2_STI_CHANNEL_BASE, | |
80 | .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1, | |
81 | .flags = IORESOURCE_MEM, | |
82 | }, | |
83 | { | |
84 | .start = OMAP2_STI_IRQ, | |
85 | .flags = IORESOURCE_IRQ, | |
86 | } | |
87 | }; | |
646e3ed1 TL |
88 | #elif defined(CONFIG_ARCH_OMAP3) |
89 | ||
90 | #define OMAP3_SDTI_BASE 0x54500000 | |
91 | #define OMAP3_SDTI_CHANNEL_BASE 0x54600000 | |
92 | ||
93 | static struct resource sti_resources[] = { | |
94 | { | |
95 | .start = OMAP3_SDTI_BASE, | |
96 | .end = OMAP3_SDTI_BASE + 0xFFF, | |
97 | .flags = IORESOURCE_MEM, | |
98 | }, | |
99 | { | |
100 | .start = OMAP3_SDTI_CHANNEL_BASE, | |
101 | .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1, | |
102 | .flags = IORESOURCE_MEM, | |
103 | } | |
104 | }; | |
105 | ||
106 | #endif | |
9b6553cd TL |
107 | |
108 | static struct platform_device sti_device = { | |
109 | .name = "sti", | |
110 | .id = -1, | |
9b6553cd TL |
111 | .num_resources = ARRAY_SIZE(sti_resources), |
112 | .resource = sti_resources, | |
113 | }; | |
114 | ||
115 | static inline void omap_init_sti(void) | |
116 | { | |
117 | platform_device_register(&sti_device); | |
118 | } | |
119 | #else | |
120 | static inline void omap_init_sti(void) {} | |
121 | #endif | |
122 | ||
646e3ed1 | 123 | #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) |
ed7eb9d9 | 124 | |
a09e64fb | 125 | #include <mach/mcspi.h> |
ed7eb9d9 JY |
126 | |
127 | #define OMAP2_MCSPI1_BASE 0x48098000 | |
128 | #define OMAP2_MCSPI2_BASE 0x4809a000 | |
646e3ed1 TL |
129 | #define OMAP2_MCSPI3_BASE 0x480b8000 |
130 | #define OMAP2_MCSPI4_BASE 0x480ba000 | |
ed7eb9d9 | 131 | |
ed7eb9d9 | 132 | static struct omap2_mcspi_platform_config omap2_mcspi1_config = { |
ed7eb9d9 JY |
133 | .num_cs = 4, |
134 | }; | |
135 | ||
c40fae95 TL |
136 | static struct resource omap2_mcspi1_resources[] = { |
137 | { | |
138 | .start = OMAP2_MCSPI1_BASE, | |
139 | .end = OMAP2_MCSPI1_BASE + 0xff, | |
140 | .flags = IORESOURCE_MEM, | |
141 | }, | |
142 | }; | |
143 | ||
646e3ed1 | 144 | static struct platform_device omap2_mcspi1 = { |
ed7eb9d9 JY |
145 | .name = "omap2_mcspi", |
146 | .id = 1, | |
c40fae95 TL |
147 | .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), |
148 | .resource = omap2_mcspi1_resources, | |
ed7eb9d9 JY |
149 | .dev = { |
150 | .platform_data = &omap2_mcspi1_config, | |
151 | }, | |
152 | }; | |
153 | ||
154 | static struct omap2_mcspi_platform_config omap2_mcspi2_config = { | |
ed7eb9d9 JY |
155 | .num_cs = 2, |
156 | }; | |
157 | ||
c40fae95 TL |
158 | static struct resource omap2_mcspi2_resources[] = { |
159 | { | |
160 | .start = OMAP2_MCSPI2_BASE, | |
161 | .end = OMAP2_MCSPI2_BASE + 0xff, | |
162 | .flags = IORESOURCE_MEM, | |
163 | }, | |
164 | }; | |
165 | ||
646e3ed1 | 166 | static struct platform_device omap2_mcspi2 = { |
ed7eb9d9 JY |
167 | .name = "omap2_mcspi", |
168 | .id = 2, | |
c40fae95 TL |
169 | .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), |
170 | .resource = omap2_mcspi2_resources, | |
ed7eb9d9 JY |
171 | .dev = { |
172 | .platform_data = &omap2_mcspi2_config, | |
173 | }, | |
174 | }; | |
175 | ||
646e3ed1 TL |
176 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) |
177 | static struct omap2_mcspi_platform_config omap2_mcspi3_config = { | |
178 | .num_cs = 2, | |
179 | }; | |
180 | ||
181 | static struct resource omap2_mcspi3_resources[] = { | |
182 | { | |
183 | .start = OMAP2_MCSPI3_BASE, | |
184 | .end = OMAP2_MCSPI3_BASE + 0xff, | |
185 | .flags = IORESOURCE_MEM, | |
186 | }, | |
187 | }; | |
188 | ||
189 | static struct platform_device omap2_mcspi3 = { | |
190 | .name = "omap2_mcspi", | |
191 | .id = 3, | |
192 | .num_resources = ARRAY_SIZE(omap2_mcspi3_resources), | |
193 | .resource = omap2_mcspi3_resources, | |
194 | .dev = { | |
195 | .platform_data = &omap2_mcspi3_config, | |
196 | }, | |
197 | }; | |
198 | #endif | |
199 | ||
200 | #ifdef CONFIG_ARCH_OMAP3 | |
201 | static struct omap2_mcspi_platform_config omap2_mcspi4_config = { | |
202 | .num_cs = 1, | |
203 | }; | |
204 | ||
205 | static struct resource omap2_mcspi4_resources[] = { | |
206 | { | |
207 | .start = OMAP2_MCSPI4_BASE, | |
208 | .end = OMAP2_MCSPI4_BASE + 0xff, | |
209 | .flags = IORESOURCE_MEM, | |
210 | }, | |
211 | }; | |
212 | ||
213 | static struct platform_device omap2_mcspi4 = { | |
214 | .name = "omap2_mcspi", | |
215 | .id = 4, | |
216 | .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), | |
217 | .resource = omap2_mcspi4_resources, | |
218 | .dev = { | |
219 | .platform_data = &omap2_mcspi4_config, | |
220 | }, | |
221 | }; | |
222 | #endif | |
223 | ||
ed7eb9d9 JY |
224 | static void omap_init_mcspi(void) |
225 | { | |
226 | platform_device_register(&omap2_mcspi1); | |
227 | platform_device_register(&omap2_mcspi2); | |
646e3ed1 TL |
228 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) |
229 | platform_device_register(&omap2_mcspi3); | |
230 | #endif | |
231 | #ifdef CONFIG_ARCH_OMAP3 | |
232 | platform_device_register(&omap2_mcspi4); | |
233 | #endif | |
ed7eb9d9 JY |
234 | } |
235 | ||
236 | #else | |
237 | static inline void omap_init_mcspi(void) {} | |
238 | #endif | |
239 | ||
646e3ed1 TL |
240 | #ifdef CONFIG_SND_OMAP24XX_EAC |
241 | ||
242 | #define OMAP2_EAC_BASE 0x48090000 | |
243 | ||
244 | static struct resource omap2_eac_resources[] = { | |
245 | { | |
246 | .start = OMAP2_EAC_BASE, | |
247 | .end = OMAP2_EAC_BASE + 0x109, | |
248 | .flags = IORESOURCE_MEM, | |
249 | }, | |
250 | }; | |
251 | ||
252 | static struct platform_device omap2_eac_device = { | |
253 | .name = "omap24xx-eac", | |
254 | .id = -1, | |
255 | .num_resources = ARRAY_SIZE(omap2_eac_resources), | |
256 | .resource = omap2_eac_resources, | |
257 | .dev = { | |
258 | .platform_data = NULL, | |
259 | }, | |
260 | }; | |
261 | ||
262 | void omap_init_eac(struct eac_platform_data *pdata) | |
263 | { | |
264 | omap2_eac_device.dev.platform_data = pdata; | |
265 | platform_device_register(&omap2_eac_device); | |
266 | } | |
267 | ||
268 | #else | |
269 | void omap_init_eac(struct eac_platform_data *pdata) {} | |
270 | #endif | |
271 | ||
272 | #ifdef CONFIG_OMAP_SHA1_MD5 | |
273 | static struct resource sha1_md5_resources[] = { | |
274 | { | |
275 | .start = OMAP24XX_SEC_SHA1MD5_BASE, | |
276 | .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, | |
277 | .flags = IORESOURCE_MEM, | |
278 | }, | |
279 | { | |
280 | .start = INT_24XX_SHA1MD5, | |
281 | .flags = IORESOURCE_IRQ, | |
282 | } | |
283 | }; | |
284 | ||
285 | static struct platform_device sha1_md5_device = { | |
286 | .name = "OMAP SHA1/MD5", | |
287 | .id = -1, | |
288 | .num_resources = ARRAY_SIZE(sha1_md5_resources), | |
289 | .resource = sha1_md5_resources, | |
290 | }; | |
291 | ||
292 | static void omap_init_sha1_md5(void) | |
293 | { | |
294 | platform_device_register(&sha1_md5_device); | |
295 | } | |
296 | #else | |
297 | static inline void omap_init_sha1_md5(void) { } | |
298 | #endif | |
299 | ||
d8874665 TL |
300 | /*-------------------------------------------------------------------------*/ |
301 | ||
302 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ | |
303 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) | |
304 | ||
305 | static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, | |
306 | int controller_nr) | |
307 | { | |
308 | if (cpu_is_omap2420() && controller_nr == 0) { | |
309 | omap_cfg_reg(H18_24XX_MMC_CMD); | |
310 | omap_cfg_reg(H15_24XX_MMC_CLKI); | |
311 | omap_cfg_reg(G19_24XX_MMC_CLKO); | |
312 | omap_cfg_reg(F20_24XX_MMC_DAT0); | |
313 | omap_cfg_reg(F19_24XX_MMC_DAT_DIR0); | |
314 | omap_cfg_reg(G18_24XX_MMC_CMD_DIR); | |
90c62bf0 | 315 | if (mmc_controller->slots[0].wires == 4) { |
d8874665 TL |
316 | omap_cfg_reg(H14_24XX_MMC_DAT1); |
317 | omap_cfg_reg(E19_24XX_MMC_DAT2); | |
318 | omap_cfg_reg(D19_24XX_MMC_DAT3); | |
319 | omap_cfg_reg(E20_24XX_MMC_DAT_DIR1); | |
320 | omap_cfg_reg(F18_24XX_MMC_DAT_DIR2); | |
321 | omap_cfg_reg(E18_24XX_MMC_DAT_DIR3); | |
322 | } | |
323 | ||
324 | /* | |
325 | * Use internal loop-back in MMC/SDIO Module Input Clock | |
326 | * selection | |
327 | */ | |
328 | if (mmc_controller->slots[0].internal_clock) { | |
329 | u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
330 | v |= (1 << 24); | |
331 | omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); | |
332 | } | |
333 | } | |
334 | } | |
335 | ||
336 | void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, | |
337 | int nr_controllers) | |
338 | { | |
339 | int i; | |
340 | ||
341 | for (i = 0; i < nr_controllers; i++) { | |
342 | unsigned long base, size; | |
343 | unsigned int irq = 0; | |
344 | ||
345 | if (!mmc_data[i]) | |
346 | continue; | |
347 | ||
348 | omap2_mmc_mux(mmc_data[i], i); | |
349 | ||
350 | switch (i) { | |
351 | case 0: | |
352 | base = OMAP2_MMC1_BASE; | |
353 | irq = INT_24XX_MMC_IRQ; | |
354 | break; | |
355 | case 1: | |
356 | base = OMAP2_MMC2_BASE; | |
357 | irq = INT_24XX_MMC2_IRQ; | |
358 | break; | |
359 | case 2: | |
360 | if (!cpu_is_omap34xx()) | |
361 | return; | |
362 | base = OMAP3_MMC3_BASE; | |
363 | irq = INT_34XX_MMC3_IRQ; | |
364 | break; | |
365 | default: | |
366 | continue; | |
367 | } | |
368 | ||
369 | if (cpu_is_omap2420()) | |
370 | size = OMAP2420_MMC_SIZE; | |
371 | else | |
372 | size = HSMMC_SIZE; | |
373 | ||
374 | omap_mmc_add(i, base, size, irq, mmc_data[i]); | |
375 | }; | |
376 | } | |
377 | ||
378 | #endif | |
379 | ||
380 | /*-------------------------------------------------------------------------*/ | |
381 | ||
646e3ed1 TL |
382 | #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) |
383 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) | |
384 | #define OMAP_HDQ_BASE 0x480B2000 | |
385 | #endif | |
386 | static struct resource omap_hdq_resources[] = { | |
387 | { | |
388 | .start = OMAP_HDQ_BASE, | |
389 | .end = OMAP_HDQ_BASE + 0x1C, | |
390 | .flags = IORESOURCE_MEM, | |
391 | }, | |
392 | { | |
393 | .start = INT_24XX_HDQ_IRQ, | |
394 | .flags = IORESOURCE_IRQ, | |
395 | }, | |
396 | }; | |
397 | static struct platform_device omap_hdq_dev = { | |
398 | .name = "omap_hdq", | |
399 | .id = 0, | |
400 | .dev = { | |
401 | .platform_data = NULL, | |
402 | }, | |
403 | .num_resources = ARRAY_SIZE(omap_hdq_resources), | |
404 | .resource = omap_hdq_resources, | |
405 | }; | |
406 | static inline void omap_hdq_init(void) | |
407 | { | |
408 | (void) platform_device_register(&omap_hdq_dev); | |
409 | } | |
410 | #else | |
411 | static inline void omap_hdq_init(void) {} | |
412 | #endif | |
413 | ||
1dbae815 TL |
414 | /*-------------------------------------------------------------------------*/ |
415 | ||
416 | static int __init omap2_init_devices(void) | |
417 | { | |
418 | /* please keep these calls, and their implementations above, | |
419 | * in alphabetical order so they're easier to sort through. | |
420 | */ | |
c40fae95 | 421 | omap_init_mbox(); |
ed7eb9d9 | 422 | omap_init_mcspi(); |
646e3ed1 | 423 | omap_hdq_init(); |
9b6553cd | 424 | omap_init_sti(); |
646e3ed1 | 425 | omap_init_sha1_md5(); |
1dbae815 TL |
426 | |
427 | return 0; | |
428 | } | |
429 | arch_initcall(omap2_init_devices); |