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OMAP clock: drop .id field; ensure each clock has a unique name
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / clock44xx_data.c
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972c5427
RN		 1/*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#include <linux/kernel.h>
93340a22 23#include <linux/list.h>
972c5427
RN		 24#include <linux/clk.h>
25
26#include <plat/control.h>
27#include <plat/clkdev_omap.h>
28
29#include "clock.h"
30#include "clock44xx.h"
31#include "cm.h"
32#include "cm-regbits-44xx.h"
33#include "prm.h"
34#include "prm-regbits-44xx.h"
35
36/* Root clocks */
37
38static struct clk extalt_clkin_ck = {
39 .name = "extalt_clkin_ck",
40 .rate = 59000000,
41 .ops = &clkops_null,
c78a05e8 42 .flags = ALWAYS_ENABLED,
972c5427
RN		 43};
44
45static struct clk pad_clks_ck = {
46 .name = "pad_clks_ck",
47 .rate = 12000000,
48 .ops = &clkops_null,
c78a05e8 49 .flags = ALWAYS_ENABLED,
972c5427
RN		 50};
51
52static struct clk pad_slimbus_core_clks_ck = {
53 .name = "pad_slimbus_core_clks_ck",
54 .rate = 12000000,
55 .ops = &clkops_null,
c78a05e8 56 .flags = ALWAYS_ENABLED,
972c5427
RN		 57};
58
59static struct clk secure_32k_clk_src_ck = {
60 .name = "secure_32k_clk_src_ck",
61 .rate = 32768,
62 .ops = &clkops_null,
c78a05e8 63 .flags = ALWAYS_ENABLED,
972c5427
RN		 64};
65
66static struct clk slimbus_clk = {
67 .name = "slimbus_clk",
68 .rate = 12000000,
69 .ops = &clkops_null,
c78a05e8 70 .flags = ALWAYS_ENABLED,
972c5427
RN		 71};
72
73static struct clk sys_32k_ck = {
74 .name = "sys_32k_ck",
75 .rate = 32768,
76 .ops = &clkops_null,
c78a05e8 77 .flags = ALWAYS_ENABLED,
972c5427
RN		 78};
79
80static struct clk virt_12000000_ck = {
81 .name = "virt_12000000_ck",
82 .ops = &clkops_null,
83 .rate = 12000000,
84};
85
86static struct clk virt_13000000_ck = {
87 .name = "virt_13000000_ck",
88 .ops = &clkops_null,
89 .rate = 13000000,
90};
91
92static struct clk virt_16800000_ck = {
93 .name = "virt_16800000_ck",
94 .ops = &clkops_null,
95 .rate = 16800000,
96};
97
98static struct clk virt_19200000_ck = {
99 .name = "virt_19200000_ck",
100 .ops = &clkops_null,
101 .rate = 19200000,
102};
103
104static struct clk virt_26000000_ck = {
105 .name = "virt_26000000_ck",
106 .ops = &clkops_null,
107 .rate = 26000000,
108};
109
110static struct clk virt_27000000_ck = {
111 .name = "virt_27000000_ck",
112 .ops = &clkops_null,
113 .rate = 27000000,
114};
115
116static struct clk virt_38400000_ck = {
117 .name = "virt_38400000_ck",
118 .ops = &clkops_null,
119 .rate = 38400000,
120};
121
122static const struct clksel_rate div_1_0_rates[] = {
123 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
124 { .div = 0 },
125};
126
127static const struct clksel_rate div_1_1_rates[] = {
128 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
129 { .div = 0 },
130};
131
132static const struct clksel_rate div_1_2_rates[] = {
133 { .div = 1, .val = 2, .flags = RATE_IN_4430 },
134 { .div = 0 },
135};
136
137static const struct clksel_rate div_1_3_rates[] = {
138 { .div = 1, .val = 3, .flags = RATE_IN_4430 },
139 { .div = 0 },
140};
141
142static const struct clksel_rate div_1_4_rates[] = {
143 { .div = 1, .val = 4, .flags = RATE_IN_4430 },
144 { .div = 0 },
145};
146
147static const struct clksel_rate div_1_5_rates[] = {
148 { .div = 1, .val = 5, .flags = RATE_IN_4430 },
149 { .div = 0 },
150};
151
152static const struct clksel_rate div_1_6_rates[] = {
153 { .div = 1, .val = 6, .flags = RATE_IN_4430 },
154 { .div = 0 },
155};
156
157static const struct clksel_rate div_1_7_rates[] = {
158 { .div = 1, .val = 7, .flags = RATE_IN_4430 },
159 { .div = 0 },
160};
161
162static const struct clksel sys_clkin_sel[] = {
163 { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
164 { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
165 { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
166 { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
167 { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
168 { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
169 { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
170 { .parent = NULL },
171};
172
173static struct clk sys_clkin_ck = {
174 .name = "sys_clkin_ck",
175 .rate = 38400000,
176 .clksel = sys_clkin_sel,
177 .init = &omap2_init_clksel_parent,
178 .clksel_reg = OMAP4430_CM_SYS_CLKSEL,
179 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
180 .ops = &clkops_null,
181 .recalc = &omap2_clksel_recalc,
c78a05e8 182 .flags = ALWAYS_ENABLED,
972c5427
RN		 183};
184
185static struct clk utmi_phy_clkout_ck = {
186 .name = "utmi_phy_clkout_ck",
187 .rate = 12000000,
188 .ops = &clkops_null,
c78a05e8 189 .flags = ALWAYS_ENABLED,
972c5427
RN		 190};
191
192static struct clk xclk60mhsp1_ck = {
193 .name = "xclk60mhsp1_ck",
194 .rate = 12000000,
195 .ops = &clkops_null,
c78a05e8 196 .flags = ALWAYS_ENABLED,
972c5427
RN		 197};
198
199static struct clk xclk60mhsp2_ck = {
200 .name = "xclk60mhsp2_ck",
201 .rate = 12000000,
202 .ops = &clkops_null,
c78a05e8 203 .flags = ALWAYS_ENABLED,
972c5427
RN		 204};
205
206static struct clk xclk60motg_ck = {
207 .name = "xclk60motg_ck",
208 .rate = 60000000,
209 .ops = &clkops_null,
c78a05e8 210 .flags = ALWAYS_ENABLED,
972c5427
RN		 211};
212
213/* Module clocks and DPLL outputs */
214
215static const struct clksel_rate div2_1to2_rates[] = {
216 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
217 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
218 { .div = 0 },
219};
220
221static const struct clksel dpll_sys_ref_clk_div[] = {
222 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
223 { .parent = NULL },
224};
225
226static struct clk dpll_sys_ref_clk = {
227 .name = "dpll_sys_ref_clk",
228 .parent = &sys_clkin_ck,
229 .clksel = dpll_sys_ref_clk_div,
230 .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
231 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
232 .ops = &clkops_null,
233 .recalc = &omap2_clksel_recalc,
234 .round_rate = &omap2_clksel_round_rate,
235 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 236};
237
238static const struct clksel abe_dpll_refclk_mux_sel[] = {
239 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
240 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
241 { .parent = NULL },
242};
243
244static struct clk abe_dpll_refclk_mux_ck = {
245 .name = "abe_dpll_refclk_mux_ck",
246 .parent = &dpll_sys_ref_clk,
247 .clksel = abe_dpll_refclk_mux_sel,
248 .init = &omap2_init_clksel_parent,
249 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
250 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
251 .ops = &clkops_null,
252 .recalc = &omap2_clksel_recalc,
972c5427
RN		 253};
254
255/* DPLL_ABE */
256static struct dpll_data dpll_abe_dd = {
257 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
258 .clk_bypass = &sys_clkin_ck,
259 .clk_ref = &abe_dpll_refclk_mux_ck,
260 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
261 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
262 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
263 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
264 .mult_mask = OMAP4430_DPLL_MULT_MASK,
265 .div1_mask = OMAP4430_DPLL_DIV_MASK,
266 .enable_mask = OMAP4430_DPLL_EN_MASK,
267 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
268 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
269 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
270 .max_divider = OMAP4430_MAX_DPLL_DIV,
271 .min_divider = 1,
272};
273
274
275static struct clk dpll_abe_ck = {
276 .name = "dpll_abe_ck",
277 .parent = &abe_dpll_refclk_mux_ck,
278 .dpll_data = &dpll_abe_dd,
911bd739 279 .init = &omap2_init_dpll_parent,
4751227d 280 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 281 .recalc = &omap3_dpll_recalc,
282 .round_rate = &omap2_dpll_round_rate,
283 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 284};
285
286static struct clk dpll_abe_m2x2_ck = {
287 .name = "dpll_abe_m2x2_ck",
288 .parent = &dpll_abe_ck,
289 .ops = &clkops_null,
290 .recalc = &followparent_recalc,
972c5427
RN		 291};
292
293static struct clk abe_24m_fclk = {
294 .name = "abe_24m_fclk",
295 .parent = &dpll_abe_m2x2_ck,
296 .ops = &clkops_null,
297 .recalc = &followparent_recalc,
972c5427
RN		 298};
299
300static const struct clksel_rate div3_1to4_rates[] = {
301 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
302 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
303 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
304 { .div = 0 },
305};
306
307static const struct clksel abe_clk_div[] = {
308 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
309 { .parent = NULL },
310};
311
312static struct clk abe_clk = {
313 .name = "abe_clk",
314 .parent = &dpll_abe_m2x2_ck,
315 .clksel = abe_clk_div,
316 .clksel_reg = OMAP4430_CM_CLKSEL_ABE,
317 .clksel_mask = OMAP4430_CLKSEL_OPP_MASK,
318 .ops = &clkops_null,
319 .recalc = &omap2_clksel_recalc,
320 .round_rate = &omap2_clksel_round_rate,
321 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 322};
323
324static const struct clksel aess_fclk_div[] = {
325 { .parent = &abe_clk, .rates = div2_1to2_rates },
326 { .parent = NULL },
327};
328
329static struct clk aess_fclk = {
330 .name = "aess_fclk",
331 .parent = &abe_clk,
332 .clksel = aess_fclk_div,
333 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
334 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
335 .ops = &clkops_null,
336 .recalc = &omap2_clksel_recalc,
337 .round_rate = &omap2_clksel_round_rate,
338 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 339};
340
341static const struct clksel_rate div31_1to31_rates[] = {
ecbb0659
RN		 342 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
343 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
344 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
345 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
346 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
347 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
348 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
349 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
350 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
351 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
352 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
353 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
354 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
355 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
356 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
357 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
358 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
359 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
360 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
361 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
362 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
363 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
364 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
365 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
366 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
367 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
368 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
369 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
370 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
371 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
372 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
972c5427
RN		 373 { .div = 0 },
374};
375
376static const struct clksel dpll_abe_m3_div[] = {
377 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
378 { .parent = NULL },
379};
380
381static struct clk dpll_abe_m3_ck = {
382 .name = "dpll_abe_m3_ck",
383 .parent = &dpll_abe_ck,
384 .clksel = dpll_abe_m3_div,
385 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
386 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
387 .ops = &clkops_null,
388 .recalc = &omap2_clksel_recalc,
389 .round_rate = &omap2_clksel_round_rate,
390 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 391};
392
393static const struct clksel core_hsd_byp_clk_mux_sel[] = {
394 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
395 { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
396 { .parent = NULL },
397};
398
399static struct clk core_hsd_byp_clk_mux_ck = {
400 .name = "core_hsd_byp_clk_mux_ck",
401 .parent = &dpll_sys_ref_clk,
402 .clksel = core_hsd_byp_clk_mux_sel,
403 .init = &omap2_init_clksel_parent,
404 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
405 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
406 .ops = &clkops_null,
407 .recalc = &omap2_clksel_recalc,
972c5427
RN		 408};
409
410/* DPLL_CORE */
411static struct dpll_data dpll_core_dd = {
412 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
413 .clk_bypass = &core_hsd_byp_clk_mux_ck,
414 .clk_ref = &dpll_sys_ref_clk,
415 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
416 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
417 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
418 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
419 .mult_mask = OMAP4430_DPLL_MULT_MASK,
420 .div1_mask = OMAP4430_DPLL_DIV_MASK,
421 .enable_mask = OMAP4430_DPLL_EN_MASK,
422 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
423 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
424 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
425 .max_divider = OMAP4430_MAX_DPLL_DIV,
426 .min_divider = 1,
427};
428
429
430static struct clk dpll_core_ck = {
431 .name = "dpll_core_ck",
432 .parent = &dpll_sys_ref_clk,
433 .dpll_data = &dpll_core_dd,
911bd739 434 .init = &omap2_init_dpll_parent,
972c5427
RN		 435 .ops = &clkops_null,
436 .recalc = &omap3_dpll_recalc,
972c5427
RN		 437};
438
439static const struct clksel dpll_core_m6_div[] = {
440 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
441 { .parent = NULL },
442};
443
444static struct clk dpll_core_m6_ck = {
445 .name = "dpll_core_m6_ck",
446 .parent = &dpll_core_ck,
447 .clksel = dpll_core_m6_div,
448 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
449 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
450 .ops = &clkops_null,
451 .recalc = &omap2_clksel_recalc,
452 .round_rate = &omap2_clksel_round_rate,
453 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 454};
455
456static const struct clksel dbgclk_mux_sel[] = {
457 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
458 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
459 { .parent = NULL },
460};
461
462static struct clk dbgclk_mux_ck = {
463 .name = "dbgclk_mux_ck",
464 .parent = &sys_clkin_ck,
465 .ops = &clkops_null,
466 .recalc = &followparent_recalc,
972c5427
RN		 467};
468
469static struct clk dpll_core_m2_ck = {
470 .name = "dpll_core_m2_ck",
471 .parent = &dpll_core_ck,
472 .clksel = dpll_core_m6_div,
473 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
474 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
475 .ops = &clkops_null,
476 .recalc = &omap2_clksel_recalc,
477 .round_rate = &omap2_clksel_round_rate,
478 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 479};
480
481static struct clk ddrphy_ck = {
482 .name = "ddrphy_ck",
483 .parent = &dpll_core_m2_ck,
484 .ops = &clkops_null,
485 .recalc = &followparent_recalc,
972c5427
RN		 486};
487
488static struct clk dpll_core_m5_ck = {
489 .name = "dpll_core_m5_ck",
490 .parent = &dpll_core_ck,
491 .clksel = dpll_core_m6_div,
492 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
493 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
494 .ops = &clkops_null,
495 .recalc = &omap2_clksel_recalc,
496 .round_rate = &omap2_clksel_round_rate,
497 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 498};
499
500static const struct clksel div_core_div[] = {
501 { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
502 { .parent = NULL },
503};
504
505static struct clk div_core_ck = {
506 .name = "div_core_ck",
507 .parent = &dpll_core_m5_ck,
508 .clksel = div_core_div,
509 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
510 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
511 .ops = &clkops_null,
512 .recalc = &omap2_clksel_recalc,
513 .round_rate = &omap2_clksel_round_rate,
514 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 515};
516
517static const struct clksel_rate div4_1to8_rates[] = {
518 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
519 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
520 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
521 { .div = 8, .val = 3, .flags = RATE_IN_4430 },
522 { .div = 0 },
523};
524
525static const struct clksel div_iva_hs_clk_div[] = {
526 { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
527 { .parent = NULL },
528};
529
530static struct clk div_iva_hs_clk = {
531 .name = "div_iva_hs_clk",
532 .parent = &dpll_core_m5_ck,
533 .clksel = div_iva_hs_clk_div,
534 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
535 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
536 .ops = &clkops_null,
537 .recalc = &omap2_clksel_recalc,
538 .round_rate = &omap2_clksel_round_rate,
539 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 540};
541
542static struct clk div_mpu_hs_clk = {
543 .name = "div_mpu_hs_clk",
544 .parent = &dpll_core_m5_ck,
545 .clksel = div_iva_hs_clk_div,
546 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
547 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
548 .ops = &clkops_null,
549 .recalc = &omap2_clksel_recalc,
550 .round_rate = &omap2_clksel_round_rate,
551 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 552};
553
554static struct clk dpll_core_m4_ck = {
555 .name = "dpll_core_m4_ck",
556 .parent = &dpll_core_ck,
557 .clksel = dpll_core_m6_div,
558 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
559 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
560 .ops = &clkops_null,
561 .recalc = &omap2_clksel_recalc,
562 .round_rate = &omap2_clksel_round_rate,
563 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 564};
565
566static struct clk dll_clk_div_ck = {
567 .name = "dll_clk_div_ck",
568 .parent = &dpll_core_m4_ck,
569 .ops = &clkops_null,
570 .recalc = &followparent_recalc,
972c5427
RN		 571};
572
573static struct clk dpll_abe_m2_ck = {
574 .name = "dpll_abe_m2_ck",
575 .parent = &dpll_abe_ck,
576 .clksel = dpll_abe_m3_div,
577 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
578 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
579 .ops = &clkops_null,
580 .recalc = &omap2_clksel_recalc,
581 .round_rate = &omap2_clksel_round_rate,
582 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 583};
584
585static struct clk dpll_core_m3_ck = {
586 .name = "dpll_core_m3_ck",
587 .parent = &dpll_core_ck,
588 .clksel = dpll_core_m6_div,
589 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
590 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
591 .ops = &clkops_null,
592 .recalc = &omap2_clksel_recalc,
593 .round_rate = &omap2_clksel_round_rate,
594 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 595};
596
597static struct clk dpll_core_m7_ck = {
598 .name = "dpll_core_m7_ck",
599 .parent = &dpll_core_ck,
600 .clksel = dpll_core_m6_div,
601 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
602 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
603 .ops = &clkops_null,
604 .recalc = &omap2_clksel_recalc,
605 .round_rate = &omap2_clksel_round_rate,
606 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 607};
608
609static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
610 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
611 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
612 { .parent = NULL },
613};
614
615static struct clk iva_hsd_byp_clk_mux_ck = {
616 .name = "iva_hsd_byp_clk_mux_ck",
617 .parent = &dpll_sys_ref_clk,
618 .ops = &clkops_null,
619 .recalc = &followparent_recalc,
972c5427
RN		 620};
621
622/* DPLL_IVA */
623static struct dpll_data dpll_iva_dd = {
624 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
625 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
626 .clk_ref = &dpll_sys_ref_clk,
627 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
628 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
629 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
630 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
631 .mult_mask = OMAP4430_DPLL_MULT_MASK,
632 .div1_mask = OMAP4430_DPLL_DIV_MASK,
633 .enable_mask = OMAP4430_DPLL_EN_MASK,
634 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
635 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
636 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
637 .max_divider = OMAP4430_MAX_DPLL_DIV,
638 .min_divider = 1,
639};
640
641
642static struct clk dpll_iva_ck = {
643 .name = "dpll_iva_ck",
644 .parent = &dpll_sys_ref_clk,
645 .dpll_data = &dpll_iva_dd,
911bd739 646 .init = &omap2_init_dpll_parent,
4751227d 647 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 648 .recalc = &omap3_dpll_recalc,
649 .round_rate = &omap2_dpll_round_rate,
650 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 651};
652
653static const struct clksel dpll_iva_m4_div[] = {
654 { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
655 { .parent = NULL },
656};
657
658static struct clk dpll_iva_m4_ck = {
659 .name = "dpll_iva_m4_ck",
660 .parent = &dpll_iva_ck,
661 .clksel = dpll_iva_m4_div,
662 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
663 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
664 .ops = &clkops_null,
665 .recalc = &omap2_clksel_recalc,
666 .round_rate = &omap2_clksel_round_rate,
667 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 668};
669
670static struct clk dpll_iva_m5_ck = {
671 .name = "dpll_iva_m5_ck",
672 .parent = &dpll_iva_ck,
673 .clksel = dpll_iva_m4_div,
674 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
675 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
676 .ops = &clkops_null,
677 .recalc = &omap2_clksel_recalc,
678 .round_rate = &omap2_clksel_round_rate,
679 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 680};
681
682/* DPLL_MPU */
683static struct dpll_data dpll_mpu_dd = {
684 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
685 .clk_bypass = &div_mpu_hs_clk,
686 .clk_ref = &dpll_sys_ref_clk,
687 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
688 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
689 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
690 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
691 .mult_mask = OMAP4430_DPLL_MULT_MASK,
692 .div1_mask = OMAP4430_DPLL_DIV_MASK,
693 .enable_mask = OMAP4430_DPLL_EN_MASK,
694 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
695 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
696 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
697 .max_divider = OMAP4430_MAX_DPLL_DIV,
698 .min_divider = 1,
699};
700
701
702static struct clk dpll_mpu_ck = {
703 .name = "dpll_mpu_ck",
704 .parent = &dpll_sys_ref_clk,
705 .dpll_data = &dpll_mpu_dd,
911bd739 706 .init = &omap2_init_dpll_parent,
4751227d 707 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 708 .recalc = &omap3_dpll_recalc,
709 .round_rate = &omap2_dpll_round_rate,
710 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 711};
712
713static const struct clksel dpll_mpu_m2_div[] = {
714 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
715 { .parent = NULL },
716};
717
718static struct clk dpll_mpu_m2_ck = {
719 .name = "dpll_mpu_m2_ck",
720 .parent = &dpll_mpu_ck,
721 .clksel = dpll_mpu_m2_div,
722 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
723 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
724 .ops = &clkops_null,
725 .recalc = &omap2_clksel_recalc,
726 .round_rate = &omap2_clksel_round_rate,
727 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 728};
729
730static struct clk per_hs_clk_div_ck = {
731 .name = "per_hs_clk_div_ck",
732 .parent = &dpll_abe_m3_ck,
733 .ops = &clkops_null,
734 .recalc = &followparent_recalc,
972c5427
RN		 735};
736
737static const struct clksel per_hsd_byp_clk_mux_sel[] = {
738 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
739 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
740 { .parent = NULL },
741};
742
743static struct clk per_hsd_byp_clk_mux_ck = {
744 .name = "per_hsd_byp_clk_mux_ck",
745 .parent = &dpll_sys_ref_clk,
746 .clksel = per_hsd_byp_clk_mux_sel,
747 .init = &omap2_init_clksel_parent,
748 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
749 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
750 .ops = &clkops_null,
751 .recalc = &omap2_clksel_recalc,
972c5427
RN		 752};
753
754/* DPLL_PER */
755static struct dpll_data dpll_per_dd = {
756 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
757 .clk_bypass = &per_hsd_byp_clk_mux_ck,
758 .clk_ref = &dpll_sys_ref_clk,
759 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
760 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
761 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
762 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
763 .mult_mask = OMAP4430_DPLL_MULT_MASK,
764 .div1_mask = OMAP4430_DPLL_DIV_MASK,
765 .enable_mask = OMAP4430_DPLL_EN_MASK,
766 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
767 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
768 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
769 .max_divider = OMAP4430_MAX_DPLL_DIV,
770 .min_divider = 1,
771};
772
773
774static struct clk dpll_per_ck = {
775 .name = "dpll_per_ck",
776 .parent = &dpll_sys_ref_clk,
777 .dpll_data = &dpll_per_dd,
911bd739 778 .init = &omap2_init_dpll_parent,
4751227d 779 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 780 .recalc = &omap3_dpll_recalc,
781 .round_rate = &omap2_dpll_round_rate,
782 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 783};
784
785static const struct clksel dpll_per_m2_div[] = {
786 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
787 { .parent = NULL },
788};
789
790static struct clk dpll_per_m2_ck = {
791 .name = "dpll_per_m2_ck",
792 .parent = &dpll_per_ck,
793 .clksel = dpll_per_m2_div,
794 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
795 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
796 .ops = &clkops_null,
797 .recalc = &omap2_clksel_recalc,
798 .round_rate = &omap2_clksel_round_rate,
799 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 800};
801
802static struct clk dpll_per_m2x2_ck = {
803 .name = "dpll_per_m2x2_ck",
804 .parent = &dpll_per_ck,
805 .ops = &clkops_null,
806 .recalc = &followparent_recalc,
972c5427
RN		 807};
808
809static struct clk dpll_per_m3_ck = {
810 .name = "dpll_per_m3_ck",
811 .parent = &dpll_per_ck,
812 .clksel = dpll_per_m2_div,
813 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
814 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
815 .ops = &clkops_null,
816 .recalc = &omap2_clksel_recalc,
817 .round_rate = &omap2_clksel_round_rate,
818 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 819};
820
821static struct clk dpll_per_m4_ck = {
822 .name = "dpll_per_m4_ck",
823 .parent = &dpll_per_ck,
824 .clksel = dpll_per_m2_div,
825 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
826 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
827 .ops = &clkops_null,
828 .recalc = &omap2_clksel_recalc,
829 .round_rate = &omap2_clksel_round_rate,
830 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 831};
832
833static struct clk dpll_per_m5_ck = {
834 .name = "dpll_per_m5_ck",
835 .parent = &dpll_per_ck,
836 .clksel = dpll_per_m2_div,
837 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
838 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
839 .ops = &clkops_null,
840 .recalc = &omap2_clksel_recalc,
841 .round_rate = &omap2_clksel_round_rate,
842 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 843};
844
845static struct clk dpll_per_m6_ck = {
846 .name = "dpll_per_m6_ck",
847 .parent = &dpll_per_ck,
848 .clksel = dpll_per_m2_div,
849 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
850 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
851 .ops = &clkops_null,
852 .recalc = &omap2_clksel_recalc,
853 .round_rate = &omap2_clksel_round_rate,
854 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 855};
856
857static struct clk dpll_per_m7_ck = {
858 .name = "dpll_per_m7_ck",
859 .parent = &dpll_per_ck,
860 .clksel = dpll_per_m2_div,
861 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
862 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
863 .ops = &clkops_null,
864 .recalc = &omap2_clksel_recalc,
865 .round_rate = &omap2_clksel_round_rate,
866 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 867};
868
869/* DPLL_UNIPRO */
870static struct dpll_data dpll_unipro_dd = {
871 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
872 .clk_bypass = &dpll_sys_ref_clk,
873 .clk_ref = &dpll_sys_ref_clk,
874 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
875 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
876 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
877 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
878 .mult_mask = OMAP4430_DPLL_MULT_MASK,
879 .div1_mask = OMAP4430_DPLL_DIV_MASK,
880 .enable_mask = OMAP4430_DPLL_EN_MASK,
881 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
882 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
883 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
884 .max_divider = OMAP4430_MAX_DPLL_DIV,
885 .min_divider = 1,
886};
887
888
889static struct clk dpll_unipro_ck = {
890 .name = "dpll_unipro_ck",
891 .parent = &dpll_sys_ref_clk,
892 .dpll_data = &dpll_unipro_dd,
911bd739 893 .init = &omap2_init_dpll_parent,
4751227d 894 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 895 .recalc = &omap3_dpll_recalc,
896 .round_rate = &omap2_dpll_round_rate,
897 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 898};
899
900static const struct clksel dpll_unipro_m2x2_div[] = {
901 { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
902 { .parent = NULL },
903};
904
905static struct clk dpll_unipro_m2x2_ck = {
906 .name = "dpll_unipro_m2x2_ck",
907 .parent = &dpll_unipro_ck,
908 .clksel = dpll_unipro_m2x2_div,
909 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
910 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
911 .ops = &clkops_null,
912 .recalc = &omap2_clksel_recalc,
913 .round_rate = &omap2_clksel_round_rate,
914 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 915};
916
917static struct clk usb_hs_clk_div_ck = {
918 .name = "usb_hs_clk_div_ck",
919 .parent = &dpll_abe_m3_ck,
920 .ops = &clkops_null,
921 .recalc = &followparent_recalc,
972c5427
RN		 922};
923
924/* DPLL_USB */
925static struct dpll_data dpll_usb_dd = {
926 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
927 .clk_bypass = &usb_hs_clk_div_ck,
928 .clk_ref = &dpll_sys_ref_clk,
929 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
930 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
931 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
932 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
933 .mult_mask = OMAP4430_DPLL_MULT_MASK,
934 .div1_mask = OMAP4430_DPLL_DIV_MASK,
935 .enable_mask = OMAP4430_DPLL_EN_MASK,
936 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
937 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
938 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
939 .max_divider = OMAP4430_MAX_DPLL_DIV,
940 .min_divider = 1,
358965d7 941 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL
972c5427
RN		 942};
943
944
945static struct clk dpll_usb_ck = {
946 .name = "dpll_usb_ck",
947 .parent = &dpll_sys_ref_clk,
948 .dpll_data = &dpll_usb_dd,
911bd739 949 .init = &omap2_init_dpll_parent,
4751227d 950 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 951 .recalc = &omap3_dpll_recalc,
952 .round_rate = &omap2_dpll_round_rate,
953 .set_rate = &omap3_noncore_dpll_set_rate,
972c5427
RN		 954};
955
956static struct clk dpll_usb_clkdcoldo_ck = {
957 .name = "dpll_usb_clkdcoldo_ck",
958 .parent = &dpll_usb_ck,
959 .ops = &clkops_null,
960 .recalc = &followparent_recalc,
972c5427
RN		 961};
962
963static const struct clksel dpll_usb_m2_div[] = {
964 { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
965 { .parent = NULL },
966};
967
968static struct clk dpll_usb_m2_ck = {
969 .name = "dpll_usb_m2_ck",
970 .parent = &dpll_usb_ck,
971 .clksel = dpll_usb_m2_div,
972 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
973 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
974 .ops = &clkops_null,
975 .recalc = &omap2_clksel_recalc,
976 .round_rate = &omap2_clksel_round_rate,
977 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 978};
979
980static const struct clksel ducati_clk_mux_sel[] = {
981 { .parent = &div_core_ck, .rates = div_1_0_rates },
982 { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
983 { .parent = NULL },
984};
985
986static struct clk ducati_clk_mux_ck = {
987 .name = "ducati_clk_mux_ck",
988 .parent = &div_core_ck,
989 .clksel = ducati_clk_mux_sel,
990 .init = &omap2_init_clksel_parent,
991 .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
992 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
993 .ops = &clkops_null,
994 .recalc = &omap2_clksel_recalc,
972c5427
RN		 995};
996
997static struct clk func_12m_fclk = {
998 .name = "func_12m_fclk",
999 .parent = &dpll_per_m2x2_ck,
1000 .ops = &clkops_null,
1001 .recalc = &followparent_recalc,
972c5427
RN		 1002};
1003
1004static struct clk func_24m_clk = {
1005 .name = "func_24m_clk",
1006 .parent = &dpll_per_m2_ck,
1007 .ops = &clkops_null,
1008 .recalc = &followparent_recalc,
972c5427
RN		 1009};
1010
1011static struct clk func_24mc_fclk = {
1012 .name = "func_24mc_fclk",
1013 .parent = &dpll_per_m2x2_ck,
1014 .ops = &clkops_null,
1015 .recalc = &followparent_recalc,
972c5427
RN		 1016};
1017
1018static const struct clksel_rate div2_4to8_rates[] = {
1019 { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1020 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1021 { .div = 0 },
1022};
1023
1024static const struct clksel func_48m_fclk_div[] = {
1025 { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1026 { .parent = NULL },
1027};
1028
1029static struct clk func_48m_fclk = {
1030 .name = "func_48m_fclk",
1031 .parent = &dpll_per_m2x2_ck,
1032 .clksel = func_48m_fclk_div,
1033 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1034 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1035 .ops = &clkops_null,
1036 .recalc = &omap2_clksel_recalc,
1037 .round_rate = &omap2_clksel_round_rate,
1038 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1039};
1040
1041static struct clk func_48mc_fclk = {
1042 .name = "func_48mc_fclk",
1043 .parent = &dpll_per_m2x2_ck,
1044 .ops = &clkops_null,
1045 .recalc = &followparent_recalc,
972c5427
RN		 1046};
1047
1048static const struct clksel_rate div2_2to4_rates[] = {
1049 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1050 { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1051 { .div = 0 },
1052};
1053
1054static const struct clksel func_64m_fclk_div[] = {
1055 { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
1056 { .parent = NULL },
1057};
1058
1059static struct clk func_64m_fclk = {
1060 .name = "func_64m_fclk",
1061 .parent = &dpll_per_m4_ck,
1062 .clksel = func_64m_fclk_div,
1063 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1064 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1065 .ops = &clkops_null,
1066 .recalc = &omap2_clksel_recalc,
1067 .round_rate = &omap2_clksel_round_rate,
1068 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1069};
1070
1071static const struct clksel func_96m_fclk_div[] = {
1072 { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1073 { .parent = NULL },
1074};
1075
1076static struct clk func_96m_fclk = {
1077 .name = "func_96m_fclk",
1078 .parent = &dpll_per_m2x2_ck,
1079 .clksel = func_96m_fclk_div,
1080 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1081 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1082 .ops = &clkops_null,
1083 .recalc = &omap2_clksel_recalc,
1084 .round_rate = &omap2_clksel_round_rate,
1085 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1086};
1087
1088static const struct clksel hsmmc6_fclk_sel[] = {
1089 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1090 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1091 { .parent = NULL },
1092};
1093
1094static struct clk hsmmc6_fclk = {
1095 .name = "hsmmc6_fclk",
1096 .parent = &func_64m_fclk,
1097 .ops = &clkops_null,
1098 .recalc = &followparent_recalc,
972c5427
RN		 1099};
1100
1101static const struct clksel_rate div2_1to8_rates[] = {
1102 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1103 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1104 { .div = 0 },
1105};
1106
1107static const struct clksel init_60m_fclk_div[] = {
1108 { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1109 { .parent = NULL },
1110};
1111
1112static struct clk init_60m_fclk = {
1113 .name = "init_60m_fclk",
1114 .parent = &dpll_usb_m2_ck,
1115 .clksel = init_60m_fclk_div,
1116 .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ,
1117 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1118 .ops = &clkops_null,
1119 .recalc = &omap2_clksel_recalc,
1120 .round_rate = &omap2_clksel_round_rate,
1121 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1122};
1123
1124static const struct clksel l3_div_div[] = {
1125 { .parent = &div_core_ck, .rates = div2_1to2_rates },
1126 { .parent = NULL },
1127};
1128
1129static struct clk l3_div_ck = {
1130 .name = "l3_div_ck",
1131 .parent = &div_core_ck,
1132 .clksel = l3_div_div,
1133 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1134 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
1135 .ops = &clkops_null,
1136 .recalc = &omap2_clksel_recalc,
1137 .round_rate = &omap2_clksel_round_rate,
1138 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1139};
1140
1141static const struct clksel l4_div_div[] = {
1142 { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1143 { .parent = NULL },
1144};
1145
1146static struct clk l4_div_ck = {
1147 .name = "l4_div_ck",
1148 .parent = &l3_div_ck,
1149 .clksel = l4_div_div,
1150 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1151 .clksel_mask = OMAP4430_CLKSEL_L4_MASK,
1152 .ops = &clkops_null,
1153 .recalc = &omap2_clksel_recalc,
1154 .round_rate = &omap2_clksel_round_rate,
1155 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1156};
1157
1158static struct clk lp_clk_div_ck = {
1159 .name = "lp_clk_div_ck",
1160 .parent = &dpll_abe_m2x2_ck,
1161 .ops = &clkops_null,
1162 .recalc = &followparent_recalc,
972c5427
RN		 1163};
1164
1165static const struct clksel l4_wkup_clk_mux_sel[] = {
1166 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1167 { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1168 { .parent = NULL },
1169};
1170
1171static struct clk l4_wkup_clk_mux_ck = {
1172 .name = "l4_wkup_clk_mux_ck",
1173 .parent = &sys_clkin_ck,
1174 .clksel = l4_wkup_clk_mux_sel,
1175 .init = &omap2_init_clksel_parent,
1176 .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL,
1177 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1178 .ops = &clkops_null,
1179 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1180};
1181
1182static const struct clksel per_abe_nc_fclk_div[] = {
1183 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1184 { .parent = NULL },
1185};
1186
1187static struct clk per_abe_nc_fclk = {
1188 .name = "per_abe_nc_fclk",
1189 .parent = &dpll_abe_m2_ck,
1190 .clksel = per_abe_nc_fclk_div,
1191 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1192 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1193 .ops = &clkops_null,
1194 .recalc = &omap2_clksel_recalc,
1195 .round_rate = &omap2_clksel_round_rate,
1196 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1197};
1198
1199static const struct clksel mcasp2_fclk_sel[] = {
1200 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1201 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1202 { .parent = NULL },
1203};
1204
1205static struct clk mcasp2_fclk = {
1206 .name = "mcasp2_fclk",
1207 .parent = &func_96m_fclk,
1208 .ops = &clkops_null,
1209 .recalc = &followparent_recalc,
972c5427
RN		 1210};
1211
1212static struct clk mcasp3_fclk = {
1213 .name = "mcasp3_fclk",
1214 .parent = &func_96m_fclk,
1215 .ops = &clkops_null,
1216 .recalc = &followparent_recalc,
972c5427
RN		 1217};
1218
1219static struct clk ocp_abe_iclk = {
1220 .name = "ocp_abe_iclk",
1221 .parent = &aess_fclk,
1222 .ops = &clkops_null,
1223 .recalc = &followparent_recalc,
972c5427
RN		 1224};
1225
1226static struct clk per_abe_24m_fclk = {
1227 .name = "per_abe_24m_fclk",
1228 .parent = &dpll_abe_m2_ck,
1229 .ops = &clkops_null,
1230 .recalc = &followparent_recalc,
972c5427
RN		 1231};
1232
1233static const struct clksel pmd_stm_clock_mux_sel[] = {
1234 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1235 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
1236 { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates },
1237 { .parent = NULL },
1238};
1239
1240static struct clk pmd_stm_clock_mux_ck = {
1241 .name = "pmd_stm_clock_mux_ck",
1242 .parent = &sys_clkin_ck,
1243 .ops = &clkops_null,
1244 .recalc = &followparent_recalc,
972c5427
RN		 1245};
1246
1247static struct clk pmd_trace_clk_mux_ck = {
1248 .name = "pmd_trace_clk_mux_ck",
1249 .parent = &sys_clkin_ck,
1250 .ops = &clkops_null,
1251 .recalc = &followparent_recalc,
972c5427
RN		 1252};
1253
1254static struct clk syc_clk_div_ck = {
1255 .name = "syc_clk_div_ck",
1256 .parent = &sys_clkin_ck,
1257 .clksel = dpll_sys_ref_clk_div,
1258 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1259 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1260 .ops = &clkops_null,
1261 .recalc = &omap2_clksel_recalc,
1262 .round_rate = &omap2_clksel_round_rate,
1263 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1264};
1265
1266/* Leaf clocks controlled by modules */
1267
1268static struct clk aes1_ck = {
1269 .name = "aes1_ck",
1270 .ops = &clkops_omap2_dflt,
1271 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1272 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1273 .clkdm_name = "l4_secure_clkdm",
1274 .parent = &l3_div_ck,
1275 .recalc = &followparent_recalc,
1276};
1277
1278static struct clk aes2_ck = {
1279 .name = "aes2_ck",
1280 .ops = &clkops_omap2_dflt,
1281 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1282 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1283 .clkdm_name = "l4_secure_clkdm",
1284 .parent = &l3_div_ck,
1285 .recalc = &followparent_recalc,
1286};
1287
1288static struct clk aess_ck = {
1289 .name = "aess_ck",
1290 .ops = &clkops_omap2_dflt,
1291 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1292 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1293 .clkdm_name = "abe_clkdm",
1294 .parent = &aess_fclk,
1295 .recalc = &followparent_recalc,
1296};
1297
1298static struct clk cust_efuse_ck = {
1299 .name = "cust_efuse_ck",
1300 .ops = &clkops_omap2_dflt,
1301 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1302 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1303 .clkdm_name = "l4_cefuse_clkdm",
1304 .parent = &sys_clkin_ck,
1305 .recalc = &followparent_recalc,
1306};
1307
1308static struct clk des3des_ck = {
1309 .name = "des3des_ck",
1310 .ops = &clkops_omap2_dflt,
1311 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1312 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1313 .clkdm_name = "l4_secure_clkdm",
1314 .parent = &l4_div_ck,
1315 .recalc = &followparent_recalc,
1316};
1317
1318static const struct clksel dmic_sync_mux_sel[] = {
1319 { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1320 { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1321 { .parent = &func_24m_clk, .rates = div_1_2_rates },
1322 { .parent = NULL },
1323};
1324
1325static struct clk dmic_sync_mux_ck = {
1326 .name = "dmic_sync_mux_ck",
1327 .parent = &abe_24m_fclk,
1328 .clksel = dmic_sync_mux_sel,
1329 .init = &omap2_init_clksel_parent,
1330 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1331 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1332 .ops = &clkops_null,
1333 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1334};
1335
1336static const struct clksel func_dmic_abe_gfclk_sel[] = {
1337 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1338 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1339 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1340 { .parent = NULL },
1341};
1342
1343/* Merged func_dmic_abe_gfclk into dmic_ck */
1344static struct clk dmic_ck = {
1345 .name = "dmic_ck",
1346 .parent = &dmic_sync_mux_ck,
1347 .clksel = func_dmic_abe_gfclk_sel,
1348 .init = &omap2_init_clksel_parent,
1349 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1350 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1351 .ops = &clkops_omap2_dflt,
1352 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1353 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1354 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1355 .clkdm_name = "abe_clkdm",
1356};
1357
1358static struct clk dss_ck = {
1359 .name = "dss_ck",
1360 .ops = &clkops_omap2_dflt,
1361 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1362 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1363 .clkdm_name = "l3_dss_clkdm",
1364 .parent = &l3_div_ck,
1365 .recalc = &followparent_recalc,
1366};
1367
1368static struct clk ducati_ck = {
1369 .name = "ducati_ck",
1370 .ops = &clkops_omap2_dflt,
1371 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1372 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1373 .clkdm_name = "ducati_clkdm",
1374 .parent = &ducati_clk_mux_ck,
1375 .recalc = &followparent_recalc,
1376};
1377
1378static struct clk emif1_ck = {
1379 .name = "emif1_ck",
1380 .ops = &clkops_omap2_dflt,
1381 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1382 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1383 .clkdm_name = "l3_emif_clkdm",
1384 .parent = &ddrphy_ck,
1385 .recalc = &followparent_recalc,
1386};
1387
1388static struct clk emif2_ck = {
1389 .name = "emif2_ck",
1390 .ops = &clkops_omap2_dflt,
1391 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1392 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1393 .clkdm_name = "l3_emif_clkdm",
1394 .parent = &ddrphy_ck,
1395 .recalc = &followparent_recalc,
1396};
1397
1398static const struct clksel fdif_fclk_div[] = {
1399 { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
1400 { .parent = NULL },
1401};
1402
1403/* Merged fdif_fclk into fdif_ck */
1404static struct clk fdif_ck = {
1405 .name = "fdif_ck",
1406 .parent = &dpll_per_m4_ck,
1407 .clksel = fdif_fclk_div,
1408 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1409 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
1410 .ops = &clkops_omap2_dflt,
1411 .recalc = &omap2_clksel_recalc,
1412 .round_rate = &omap2_clksel_round_rate,
1413 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1414 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1415 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1416 .clkdm_name = "iss_clkdm",
1417};
1418
1419static const struct clksel per_sgx_fclk_div[] = {
1420 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1421 { .parent = NULL },
1422};
1423
1424static struct clk per_sgx_fclk = {
1425 .name = "per_sgx_fclk",
1426 .parent = &dpll_per_m2x2_ck,
1427 .clksel = per_sgx_fclk_div,
1428 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1429 .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK,
1430 .ops = &clkops_null,
1431 .recalc = &omap2_clksel_recalc,
1432 .round_rate = &omap2_clksel_round_rate,
1433 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1434};
1435
1436static const struct clksel sgx_clk_mux_sel[] = {
1437 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1438 { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
1439 { .parent = NULL },
1440};
1441
1442/* Merged sgx_clk_mux into gfx_ck */
1443static struct clk gfx_ck = {
1444 .name = "gfx_ck",
1445 .parent = &dpll_core_m7_ck,
1446 .clksel = sgx_clk_mux_sel,
1447 .init = &omap2_init_clksel_parent,
1448 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1449 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1450 .ops = &clkops_omap2_dflt,
1451 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1452 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1453 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1454 .clkdm_name = "l3_gfx_clkdm",
1455};
1456
1457static struct clk gpio1_ck = {
1458 .name = "gpio1_ck",
1459 .ops = &clkops_omap2_dflt,
1460 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1461 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1462 .clkdm_name = "l4_wkup_clkdm",
1463 .parent = &l4_wkup_clk_mux_ck,
1464 .recalc = &followparent_recalc,
1465};
1466
1467static struct clk gpio2_ck = {
1468 .name = "gpio2_ck",
1469 .ops = &clkops_omap2_dflt,
1470 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1471 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1472 .clkdm_name = "l4_per_clkdm",
1473 .parent = &l4_div_ck,
1474 .recalc = &followparent_recalc,
1475};
1476
1477static struct clk gpio3_ck = {
1478 .name = "gpio3_ck",
1479 .ops = &clkops_omap2_dflt,
1480 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1481 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1482 .clkdm_name = "l4_per_clkdm",
1483 .parent = &l4_div_ck,
1484 .recalc = &followparent_recalc,
1485};
1486
1487static struct clk gpio4_ck = {
1488 .name = "gpio4_ck",
1489 .ops = &clkops_omap2_dflt,
1490 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1491 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1492 .clkdm_name = "l4_per_clkdm",
1493 .parent = &l4_div_ck,
1494 .recalc = &followparent_recalc,
1495};
1496
1497static struct clk gpio5_ck = {
1498 .name = "gpio5_ck",
1499 .ops = &clkops_omap2_dflt,
1500 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1501 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1502 .clkdm_name = "l4_per_clkdm",
1503 .parent = &l4_div_ck,
1504 .recalc = &followparent_recalc,
1505};
1506
1507static struct clk gpio6_ck = {
1508 .name = "gpio6_ck",
1509 .ops = &clkops_omap2_dflt,
1510 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1511 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1512 .clkdm_name = "l4_per_clkdm",
1513 .parent = &l4_div_ck,
1514 .recalc = &followparent_recalc,
1515};
1516
1517static struct clk gpmc_ck = {
1518 .name = "gpmc_ck",
1519 .ops = &clkops_omap2_dflt,
1520 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1521 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1522 .clkdm_name = "l3_2_clkdm",
1523 .parent = &l3_div_ck,
1524 .recalc = &followparent_recalc,
1525};
1526
1527static const struct clksel dmt1_clk_mux_sel[] = {
1528 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1529 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1530 { .parent = NULL },
1531};
1532
1533/* Merged dmt1_clk_mux into gptimer1_ck */
1534static struct clk gptimer1_ck = {
1535 .name = "gptimer1_ck",
1536 .parent = &sys_clkin_ck,
1537 .clksel = dmt1_clk_mux_sel,
1538 .init = &omap2_init_clksel_parent,
1539 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1540 .clksel_mask = OMAP4430_CLKSEL_MASK,
1541 .ops = &clkops_omap2_dflt,
1542 .recalc = &omap2_clksel_recalc,
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RN		 1543 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1544 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1545 .clkdm_name = "l4_wkup_clkdm",
1546};
1547
1548/* Merged cm2_dm10_mux into gptimer10_ck */
1549static struct clk gptimer10_ck = {
1550 .name = "gptimer10_ck",
1551 .parent = &sys_clkin_ck,
1552 .clksel = dmt1_clk_mux_sel,
1553 .init = &omap2_init_clksel_parent,
1554 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1555 .clksel_mask = OMAP4430_CLKSEL_MASK,
1556 .ops = &clkops_omap2_dflt,
1557 .recalc = &omap2_clksel_recalc,
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RN		 1558 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1559 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1560 .clkdm_name = "l4_per_clkdm",
1561};
1562
1563/* Merged cm2_dm11_mux into gptimer11_ck */
1564static struct clk gptimer11_ck = {
1565 .name = "gptimer11_ck",
1566 .parent = &sys_clkin_ck,
1567 .clksel = dmt1_clk_mux_sel,
1568 .init = &omap2_init_clksel_parent,
1569 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1570 .clksel_mask = OMAP4430_CLKSEL_MASK,
1571 .ops = &clkops_omap2_dflt,
1572 .recalc = &omap2_clksel_recalc,
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RN		 1573 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1574 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1575 .clkdm_name = "l4_per_clkdm",
1576};
1577
1578/* Merged cm2_dm2_mux into gptimer2_ck */
1579static struct clk gptimer2_ck = {
1580 .name = "gptimer2_ck",
1581 .parent = &sys_clkin_ck,
1582 .clksel = dmt1_clk_mux_sel,
1583 .init = &omap2_init_clksel_parent,
1584 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1585 .clksel_mask = OMAP4430_CLKSEL_MASK,
1586 .ops = &clkops_omap2_dflt,
1587 .recalc = &omap2_clksel_recalc,
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RN		 1588 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1589 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1590 .clkdm_name = "l4_per_clkdm",
1591};
1592
1593/* Merged cm2_dm3_mux into gptimer3_ck */
1594static struct clk gptimer3_ck = {
1595 .name = "gptimer3_ck",
1596 .parent = &sys_clkin_ck,
1597 .clksel = dmt1_clk_mux_sel,
1598 .init = &omap2_init_clksel_parent,
1599 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1600 .clksel_mask = OMAP4430_CLKSEL_MASK,
1601 .ops = &clkops_omap2_dflt,
1602 .recalc = &omap2_clksel_recalc,
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RN		 1603 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1604 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1605 .clkdm_name = "l4_per_clkdm",
1606};
1607
1608/* Merged cm2_dm4_mux into gptimer4_ck */
1609static struct clk gptimer4_ck = {
1610 .name = "gptimer4_ck",
1611 .parent = &sys_clkin_ck,
1612 .clksel = dmt1_clk_mux_sel,
1613 .init = &omap2_init_clksel_parent,
1614 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1615 .clksel_mask = OMAP4430_CLKSEL_MASK,
1616 .ops = &clkops_omap2_dflt,
1617 .recalc = &omap2_clksel_recalc,
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RN		 1618 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1619 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1620 .clkdm_name = "l4_per_clkdm",
1621};
1622
1623static const struct clksel timer5_sync_mux_sel[] = {
1624 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1625 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1626 { .parent = NULL },
1627};
1628
1629/* Merged timer5_sync_mux into gptimer5_ck */
1630static struct clk gptimer5_ck = {
1631 .name = "gptimer5_ck",
1632 .parent = &syc_clk_div_ck,
1633 .clksel = timer5_sync_mux_sel,
1634 .init = &omap2_init_clksel_parent,
1635 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1636 .clksel_mask = OMAP4430_CLKSEL_MASK,
1637 .ops = &clkops_omap2_dflt,
1638 .recalc = &omap2_clksel_recalc,
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RN		 1639 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1640 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1641 .clkdm_name = "abe_clkdm",
1642};
1643
1644/* Merged timer6_sync_mux into gptimer6_ck */
1645static struct clk gptimer6_ck = {
1646 .name = "gptimer6_ck",
1647 .parent = &syc_clk_div_ck,
1648 .clksel = timer5_sync_mux_sel,
1649 .init = &omap2_init_clksel_parent,
1650 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1651 .clksel_mask = OMAP4430_CLKSEL_MASK,
1652 .ops = &clkops_omap2_dflt,
1653 .recalc = &omap2_clksel_recalc,
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RN		 1654 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1655 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1656 .clkdm_name = "abe_clkdm",
1657};
1658
1659/* Merged timer7_sync_mux into gptimer7_ck */
1660static struct clk gptimer7_ck = {
1661 .name = "gptimer7_ck",
1662 .parent = &syc_clk_div_ck,
1663 .clksel = timer5_sync_mux_sel,
1664 .init = &omap2_init_clksel_parent,
1665 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1666 .clksel_mask = OMAP4430_CLKSEL_MASK,
1667 .ops = &clkops_omap2_dflt,
1668 .recalc = &omap2_clksel_recalc,
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RN		 1669 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1670 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1671 .clkdm_name = "abe_clkdm",
1672};
1673
1674/* Merged timer8_sync_mux into gptimer8_ck */
1675static struct clk gptimer8_ck = {
1676 .name = "gptimer8_ck",
1677 .parent = &syc_clk_div_ck,
1678 .clksel = timer5_sync_mux_sel,
1679 .init = &omap2_init_clksel_parent,
1680 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1681 .clksel_mask = OMAP4430_CLKSEL_MASK,
1682 .ops = &clkops_omap2_dflt,
1683 .recalc = &omap2_clksel_recalc,
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RN		 1684 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1685 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1686 .clkdm_name = "abe_clkdm",
1687};
1688
1689/* Merged cm2_dm9_mux into gptimer9_ck */
1690static struct clk gptimer9_ck = {
1691 .name = "gptimer9_ck",
1692 .parent = &sys_clkin_ck,
1693 .clksel = dmt1_clk_mux_sel,
1694 .init = &omap2_init_clksel_parent,
1695 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1696 .clksel_mask = OMAP4430_CLKSEL_MASK,
1697 .ops = &clkops_omap2_dflt,
1698 .recalc = &omap2_clksel_recalc,
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RN		 1699 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1700 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1701 .clkdm_name = "l4_per_clkdm",
1702};
1703
1704static struct clk hdq1w_ck = {
1705 .name = "hdq1w_ck",
1706 .ops = &clkops_omap2_dflt,
1707 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1708 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1709 .clkdm_name = "l4_per_clkdm",
1710 .parent = &func_12m_fclk,
1711 .recalc = &followparent_recalc,
1712};
1713
1714/* Merged hsi_fclk into hsi_ck */
1715static struct clk hsi_ck = {
1716 .name = "hsi_ck",
1717 .parent = &dpll_per_m2x2_ck,
1718 .clksel = per_sgx_fclk_div,
1719 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1720 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1721 .ops = &clkops_omap2_dflt,
1722 .recalc = &omap2_clksel_recalc,
1723 .round_rate = &omap2_clksel_round_rate,
1724 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 1725 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1726 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1727 .clkdm_name = "l3_init_clkdm",
1728};
1729
1730static struct clk i2c1_ck = {
1731 .name = "i2c1_ck",
1732 .ops = &clkops_omap2_dflt,
1733 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1734 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1735 .clkdm_name = "l4_per_clkdm",
1736 .parent = &func_96m_fclk,
1737 .recalc = &followparent_recalc,
1738};
1739
1740static struct clk i2c2_ck = {
1741 .name = "i2c2_ck",
1742 .ops = &clkops_omap2_dflt,
1743 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1744 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1745 .clkdm_name = "l4_per_clkdm",
1746 .parent = &func_96m_fclk,
1747 .recalc = &followparent_recalc,
1748};
1749
1750static struct clk i2c3_ck = {
1751 .name = "i2c3_ck",
1752 .ops = &clkops_omap2_dflt,
1753 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1754 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1755 .clkdm_name = "l4_per_clkdm",
1756 .parent = &func_96m_fclk,
1757 .recalc = &followparent_recalc,
1758};
1759
1760static struct clk i2c4_ck = {
1761 .name = "i2c4_ck",
1762 .ops = &clkops_omap2_dflt,
1763 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1764 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1765 .clkdm_name = "l4_per_clkdm",
1766 .parent = &func_96m_fclk,
1767 .recalc = &followparent_recalc,
1768};
1769
1770static struct clk iss_ck = {
1771 .name = "iss_ck",
1772 .ops = &clkops_omap2_dflt,
1773 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1774 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1775 .clkdm_name = "iss_clkdm",
1776 .parent = &ducati_clk_mux_ck,
1777 .recalc = &followparent_recalc,
1778};
1779
1780static struct clk ivahd_ck = {
1781 .name = "ivahd_ck",
1782 .ops = &clkops_omap2_dflt,
1783 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1784 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1785 .clkdm_name = "ivahd_clkdm",
1786 .parent = &dpll_iva_m5_ck,
1787 .recalc = &followparent_recalc,
1788};
1789
1790static struct clk keyboard_ck = {
1791 .name = "keyboard_ck",
1792 .ops = &clkops_omap2_dflt,
1793 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1794 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1795 .clkdm_name = "l4_wkup_clkdm",
1796 .parent = &sys_32k_ck,
1797 .recalc = &followparent_recalc,
1798};
1799
1800static struct clk l3_instr_interconnect_ck = {
1801 .name = "l3_instr_interconnect_ck",
1802 .ops = &clkops_omap2_dflt,
1803 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1804 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1805 .clkdm_name = "l3_instr_clkdm",
1806 .parent = &l3_div_ck,
1807 .recalc = &followparent_recalc,
1808};
1809
1810static struct clk l3_interconnect_3_ck = {
1811 .name = "l3_interconnect_3_ck",
1812 .ops = &clkops_omap2_dflt,
1813 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1814 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1815 .clkdm_name = "l3_instr_clkdm",
1816 .parent = &l3_div_ck,
1817 .recalc = &followparent_recalc,
1818};
1819
1820static struct clk mcasp_sync_mux_ck = {
1821 .name = "mcasp_sync_mux_ck",
1822 .parent = &abe_24m_fclk,
1823 .clksel = dmic_sync_mux_sel,
1824 .init = &omap2_init_clksel_parent,
1825 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1826 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1827 .ops = &clkops_null,
1828 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1829};
1830
1831static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1832 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1833 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1834 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1835 { .parent = NULL },
1836};
1837
1838/* Merged func_mcasp_abe_gfclk into mcasp_ck */
1839static struct clk mcasp_ck = {
1840 .name = "mcasp_ck",
1841 .parent = &mcasp_sync_mux_ck,
1842 .clksel = func_mcasp_abe_gfclk_sel,
1843 .init = &omap2_init_clksel_parent,
1844 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1845 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1846 .ops = &clkops_omap2_dflt,
1847 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1848 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1849 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1850 .clkdm_name = "abe_clkdm",
1851};
1852
1853static struct clk mcbsp1_sync_mux_ck = {
1854 .name = "mcbsp1_sync_mux_ck",
1855 .parent = &abe_24m_fclk,
1856 .clksel = dmic_sync_mux_sel,
1857 .init = &omap2_init_clksel_parent,
1858 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1859 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1860 .ops = &clkops_null,
1861 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1862};
1863
1864static const struct clksel func_mcbsp1_gfclk_sel[] = {
1865 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1866 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1867 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1868 { .parent = NULL },
1869};
1870
1871/* Merged func_mcbsp1_gfclk into mcbsp1_ck */
1872static struct clk mcbsp1_ck = {
1873 .name = "mcbsp1_ck",
1874 .parent = &mcbsp1_sync_mux_ck,
1875 .clksel = func_mcbsp1_gfclk_sel,
1876 .init = &omap2_init_clksel_parent,
1877 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1878 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1879 .ops = &clkops_omap2_dflt,
1880 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1881 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1882 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1883 .clkdm_name = "abe_clkdm",
1884};
1885
1886static struct clk mcbsp2_sync_mux_ck = {
1887 .name = "mcbsp2_sync_mux_ck",
1888 .parent = &abe_24m_fclk,
1889 .clksel = dmic_sync_mux_sel,
1890 .init = &omap2_init_clksel_parent,
1891 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1892 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1893 .ops = &clkops_null,
1894 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1895};
1896
1897static const struct clksel func_mcbsp2_gfclk_sel[] = {
1898 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1899 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1900 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1901 { .parent = NULL },
1902};
1903
1904/* Merged func_mcbsp2_gfclk into mcbsp2_ck */
1905static struct clk mcbsp2_ck = {
1906 .name = "mcbsp2_ck",
1907 .parent = &mcbsp2_sync_mux_ck,
1908 .clksel = func_mcbsp2_gfclk_sel,
1909 .init = &omap2_init_clksel_parent,
1910 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1911 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1912 .ops = &clkops_omap2_dflt,
1913 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1914 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1915 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1916 .clkdm_name = "abe_clkdm",
1917};
1918
1919static struct clk mcbsp3_sync_mux_ck = {
1920 .name = "mcbsp3_sync_mux_ck",
1921 .parent = &abe_24m_fclk,
1922 .clksel = dmic_sync_mux_sel,
1923 .init = &omap2_init_clksel_parent,
1924 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1925 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1926 .ops = &clkops_null,
1927 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1928};
1929
1930static const struct clksel func_mcbsp3_gfclk_sel[] = {
1931 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1932 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1933 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1934 { .parent = NULL },
1935};
1936
1937/* Merged func_mcbsp3_gfclk into mcbsp3_ck */
1938static struct clk mcbsp3_ck = {
1939 .name = "mcbsp3_ck",
1940 .parent = &mcbsp3_sync_mux_ck,
1941 .clksel = func_mcbsp3_gfclk_sel,
1942 .init = &omap2_init_clksel_parent,
1943 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1944 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1945 .ops = &clkops_omap2_dflt,
1946 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1947 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1948 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1949 .clkdm_name = "abe_clkdm",
1950};
1951
1952static struct clk mcbsp4_sync_mux_ck = {
1953 .name = "mcbsp4_sync_mux_ck",
1954 .parent = &func_96m_fclk,
1955 .clksel = mcasp2_fclk_sel,
1956 .init = &omap2_init_clksel_parent,
1957 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1958 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1959 .ops = &clkops_null,
1960 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1961};
1962
1963static const struct clksel per_mcbsp4_gfclk_sel[] = {
1964 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1965 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1966 { .parent = NULL },
1967};
1968
1969/* Merged per_mcbsp4_gfclk into mcbsp4_ck */
1970static struct clk mcbsp4_ck = {
1971 .name = "mcbsp4_ck",
1972 .parent = &mcbsp4_sync_mux_ck,
1973 .clksel = per_mcbsp4_gfclk_sel,
1974 .init = &omap2_init_clksel_parent,
1975 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1976 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1977 .ops = &clkops_omap2_dflt,
1978 .recalc = &omap2_clksel_recalc,
972c5427
RN		 1979 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1980 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1981 .clkdm_name = "l4_per_clkdm",
1982};
1983
1984static struct clk mcspi1_ck = {
1985 .name = "mcspi1_ck",
1986 .ops = &clkops_omap2_dflt,
1987 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1988 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1989 .clkdm_name = "l4_per_clkdm",
1990 .parent = &func_48m_fclk,
1991 .recalc = &followparent_recalc,
1992};
1993
1994static struct clk mcspi2_ck = {
1995 .name = "mcspi2_ck",
1996 .ops = &clkops_omap2_dflt,
1997 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1998 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1999 .clkdm_name = "l4_per_clkdm",
2000 .parent = &func_48m_fclk,
2001 .recalc = &followparent_recalc,
2002};
2003
2004static struct clk mcspi3_ck = {
2005 .name = "mcspi3_ck",
2006 .ops = &clkops_omap2_dflt,
2007 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2008 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2009 .clkdm_name = "l4_per_clkdm",
2010 .parent = &func_48m_fclk,
2011 .recalc = &followparent_recalc,
2012};
2013
2014static struct clk mcspi4_ck = {
2015 .name = "mcspi4_ck",
2016 .ops = &clkops_omap2_dflt,
2017 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2018 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2019 .clkdm_name = "l4_per_clkdm",
2020 .parent = &func_48m_fclk,
2021 .recalc = &followparent_recalc,
2022};
2023
2024/* Merged hsmmc1_fclk into mmc1_ck */
2025static struct clk mmc1_ck = {
2026 .name = "mmc1_ck",
2027 .parent = &func_64m_fclk,
2028 .clksel = hsmmc6_fclk_sel,
2029 .init = &omap2_init_clksel_parent,
2030 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2031 .clksel_mask = OMAP4430_CLKSEL_MASK,
2032 .ops = &clkops_omap2_dflt,
2033 .recalc = &omap2_clksel_recalc,
972c5427
RN		 2034 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2035 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2036 .clkdm_name = "l3_init_clkdm",
2037};
2038
2039/* Merged hsmmc2_fclk into mmc2_ck */
2040static struct clk mmc2_ck = {
2041 .name = "mmc2_ck",
2042 .parent = &func_64m_fclk,
2043 .clksel = hsmmc6_fclk_sel,
2044 .init = &omap2_init_clksel_parent,
2045 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2046 .clksel_mask = OMAP4430_CLKSEL_MASK,
2047 .ops = &clkops_omap2_dflt,
2048 .recalc = &omap2_clksel_recalc,
972c5427
RN		 2049 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2050 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2051 .clkdm_name = "l3_init_clkdm",
2052};
2053
2054static struct clk mmc3_ck = {
2055 .name = "mmc3_ck",
2056 .ops = &clkops_omap2_dflt,
2057 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2058 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2059 .clkdm_name = "l4_per_clkdm",
2060 .parent = &func_48m_fclk,
2061 .recalc = &followparent_recalc,
2062};
2063
2064static struct clk mmc4_ck = {
2065 .name = "mmc4_ck",
2066 .ops = &clkops_omap2_dflt,
2067 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2068 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2069 .clkdm_name = "l4_per_clkdm",
2070 .parent = &func_48m_fclk,
2071 .recalc = &followparent_recalc,
2072};
2073
2074static struct clk mmc5_ck = {
2075 .name = "mmc5_ck",
2076 .ops = &clkops_omap2_dflt,
2077 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2078 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2079 .clkdm_name = "l4_per_clkdm",
2080 .parent = &func_48m_fclk,
2081 .recalc = &followparent_recalc,
2082};
2083
2084static struct clk ocp_wp1_ck = {
2085 .name = "ocp_wp1_ck",
2086 .ops = &clkops_omap2_dflt,
2087 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2088 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2089 .clkdm_name = "l3_instr_clkdm",
2090 .parent = &l3_div_ck,
2091 .recalc = &followparent_recalc,
2092};
2093
2094static struct clk pdm_ck = {
2095 .name = "pdm_ck",
2096 .ops = &clkops_omap2_dflt,
2097 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2098 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2099 .clkdm_name = "abe_clkdm",
2100 .parent = &pad_clks_ck,
2101 .recalc = &followparent_recalc,
2102};
2103
2104static struct clk pkaeip29_ck = {
2105 .name = "pkaeip29_ck",
2106 .ops = &clkops_omap2_dflt,
2107 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
2108 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2109 .clkdm_name = "l4_secure_clkdm",
2110 .parent = &l4_div_ck,
2111 .recalc = &followparent_recalc,
2112};
2113
2114static struct clk rng_ck = {
2115 .name = "rng_ck",
2116 .ops = &clkops_omap2_dflt,
2117 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2118 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2119 .clkdm_name = "l4_secure_clkdm",
2120 .parent = &l4_div_ck,
2121 .recalc = &followparent_recalc,
2122};
2123
2124static struct clk sha2md51_ck = {
2125 .name = "sha2md51_ck",
2126 .ops = &clkops_omap2_dflt,
2127 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2128 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2129 .clkdm_name = "l4_secure_clkdm",
2130 .parent = &l3_div_ck,
2131 .recalc = &followparent_recalc,
2132};
2133
2134static struct clk sl2_ck = {
2135 .name = "sl2_ck",
2136 .ops = &clkops_omap2_dflt,
2137 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2138 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2139 .clkdm_name = "ivahd_clkdm",
2140 .parent = &dpll_iva_m5_ck,
2141 .recalc = &followparent_recalc,
2142};
2143
2144static struct clk slimbus1_ck = {
2145 .name = "slimbus1_ck",
2146 .ops = &clkops_omap2_dflt,
2147 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2148 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2149 .clkdm_name = "abe_clkdm",
2150 .parent = &ocp_abe_iclk,
2151 .recalc = &followparent_recalc,
2152};
2153
2154static struct clk slimbus2_ck = {
2155 .name = "slimbus2_ck",
2156 .ops = &clkops_omap2_dflt,
2157 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2158 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2159 .clkdm_name = "l4_per_clkdm",
2160 .parent = &l4_div_ck,
2161 .recalc = &followparent_recalc,
2162};
2163
2164static struct clk sr_core_ck = {
2165 .name = "sr_core_ck",
2166 .ops = &clkops_omap2_dflt,
2167 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2168 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2169 .clkdm_name = "l4_ao_clkdm",
2170 .parent = &l4_wkup_clk_mux_ck,
2171 .recalc = &followparent_recalc,
2172};
2173
2174static struct clk sr_iva_ck = {
2175 .name = "sr_iva_ck",
2176 .ops = &clkops_omap2_dflt,
2177 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2178 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2179 .clkdm_name = "l4_ao_clkdm",
2180 .parent = &l4_wkup_clk_mux_ck,
2181 .recalc = &followparent_recalc,
2182};
2183
2184static struct clk sr_mpu_ck = {
2185 .name = "sr_mpu_ck",
2186 .ops = &clkops_omap2_dflt,
2187 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2188 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2189 .clkdm_name = "l4_ao_clkdm",
2190 .parent = &l4_wkup_clk_mux_ck,
2191 .recalc = &followparent_recalc,
2192};
2193
2194static struct clk tesla_ck = {
2195 .name = "tesla_ck",
2196 .ops = &clkops_omap2_dflt,
2197 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
2198 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2199 .clkdm_name = "tesla_clkdm",
2200 .parent = &dpll_iva_m4_ck,
2201 .recalc = &followparent_recalc,
2202};
2203
2204static struct clk uart1_ck = {
2205 .name = "uart1_ck",
2206 .ops = &clkops_omap2_dflt,
2207 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2208 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2209 .clkdm_name = "l4_per_clkdm",
2210 .parent = &func_48m_fclk,
2211 .recalc = &followparent_recalc,
2212};
2213
2214static struct clk uart2_ck = {
2215 .name = "uart2_ck",
2216 .ops = &clkops_omap2_dflt,
2217 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2218 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2219 .clkdm_name = "l4_per_clkdm",
2220 .parent = &func_48m_fclk,
2221 .recalc = &followparent_recalc,
2222};
2223
2224static struct clk uart3_ck = {
2225 .name = "uart3_ck",
2226 .ops = &clkops_omap2_dflt,
2227 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2228 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2229 .clkdm_name = "l4_per_clkdm",
2230 .parent = &func_48m_fclk,
2231 .recalc = &followparent_recalc,
2232};
2233
2234static struct clk uart4_ck = {
2235 .name = "uart4_ck",
2236 .ops = &clkops_omap2_dflt,
2237 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2238 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2239 .clkdm_name = "l4_per_clkdm",
2240 .parent = &func_48m_fclk,
2241 .recalc = &followparent_recalc,
2242};
2243
2244static struct clk unipro1_ck = {
2245 .name = "unipro1_ck",
2246 .ops = &clkops_omap2_dflt,
2247 .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
2248 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2249 .clkdm_name = "l3_init_clkdm",
2250 .parent = &func_96m_fclk,
2251 .recalc = &followparent_recalc,
2252};
2253
2254static struct clk usb_host_ck = {
2255 .name = "usb_host_ck",
2256 .ops = &clkops_omap2_dflt,
2257 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2258 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2259 .clkdm_name = "l3_init_clkdm",
2260 .parent = &init_60m_fclk,
2261 .recalc = &followparent_recalc,
2262};
2263
2264static struct clk usb_host_fs_ck = {
2265 .name = "usb_host_fs_ck",
2266 .ops = &clkops_omap2_dflt,
2267 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2268 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2269 .clkdm_name = "l3_init_clkdm",
2270 .parent = &func_48mc_fclk,
2271 .recalc = &followparent_recalc,
2272};
2273
2274static struct clk usb_otg_ck = {
2275 .name = "usb_otg_ck",
2276 .ops = &clkops_omap2_dflt,
2277 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2278 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2279 .clkdm_name = "l3_init_clkdm",
2280 .parent = &l3_div_ck,
2281 .recalc = &followparent_recalc,
2282};
2283
2284static struct clk usb_tll_ck = {
2285 .name = "usb_tll_ck",
2286 .ops = &clkops_omap2_dflt,
2287 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2288 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2289 .clkdm_name = "l3_init_clkdm",
2290 .parent = &l4_div_ck,
2291 .recalc = &followparent_recalc,
2292};
2293
2294static struct clk usbphyocp2scp_ck = {
2295 .name = "usbphyocp2scp_ck",
2296 .ops = &clkops_omap2_dflt,
2297 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2298 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2299 .clkdm_name = "l3_init_clkdm",
2300 .parent = &l4_div_ck,
2301 .recalc = &followparent_recalc,
2302};
2303
2304static struct clk usim_ck = {
2305 .name = "usim_ck",
2306 .ops = &clkops_omap2_dflt,
2307 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2308 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2309 .clkdm_name = "l4_wkup_clkdm",
2310 .parent = &sys_32k_ck,
2311 .recalc = &followparent_recalc,
2312};
2313
2314static struct clk wdt2_ck = {
2315 .name = "wdt2_ck",
2316 .ops = &clkops_omap2_dflt,
2317 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2318 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2319 .clkdm_name = "l4_wkup_clkdm",
2320 .parent = &sys_32k_ck,
2321 .recalc = &followparent_recalc,
2322};
2323
2324static struct clk wdt3_ck = {
2325 .name = "wdt3_ck",
2326 .ops = &clkops_omap2_dflt,
2327 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2328 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2329 .clkdm_name = "abe_clkdm",
2330 .parent = &sys_32k_ck,
2331 .recalc = &followparent_recalc,
2332};
2333
2334/* Remaining optional clocks */
2335static const struct clksel otg_60m_gfclk_sel[] = {
2336 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2337 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2338 { .parent = NULL },
2339};
2340
2341static struct clk otg_60m_gfclk_ck = {
2342 .name = "otg_60m_gfclk_ck",
2343 .parent = &utmi_phy_clkout_ck,
2344 .clksel = otg_60m_gfclk_sel,
2345 .init = &omap2_init_clksel_parent,
2346 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2347 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2348 .ops = &clkops_null,
2349 .recalc = &omap2_clksel_recalc,
972c5427
RN		 2350};
2351
2352static const struct clksel stm_clk_div_div[] = {
2353 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2354 { .parent = NULL },
2355};
2356
2357static struct clk stm_clk_div_ck = {
2358 .name = "stm_clk_div_ck",
2359 .parent = &pmd_stm_clock_mux_ck,
2360 .clksel = stm_clk_div_div,
2361 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2362 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2363 .ops = &clkops_null,
2364 .recalc = &omap2_clksel_recalc,
2365 .round_rate = &omap2_clksel_round_rate,
2366 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 2367};
2368
2369static const struct clksel trace_clk_div_div[] = {
2370 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2371 { .parent = NULL },
2372};
2373
2374static struct clk trace_clk_div_ck = {
2375 .name = "trace_clk_div_ck",
2376 .parent = &pmd_trace_clk_mux_ck,
2377 .clksel = trace_clk_div_div,
2378 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2379 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2380 .ops = &clkops_null,
2381 .recalc = &omap2_clksel_recalc,
2382 .round_rate = &omap2_clksel_round_rate,
2383 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 2384};
2385
2386static const struct clksel_rate div2_14to18_rates[] = {
2387 { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2388 { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2389 { .div = 0 },
2390};
2391
2392static const struct clksel usim_fclk_div[] = {
2393 { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
2394 { .parent = NULL },
2395};
2396
2397static struct clk usim_fclk = {
2398 .name = "usim_fclk",
2399 .parent = &dpll_per_m4_ck,
2400 .clksel = usim_fclk_div,
2401 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2402 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2403 .ops = &clkops_null,
2404 .recalc = &omap2_clksel_recalc,
2405 .round_rate = &omap2_clksel_round_rate,
2406 .set_rate = &omap2_clksel_set_rate,
972c5427
RN		 2407};
2408
2409static const struct clksel utmi_p1_gfclk_sel[] = {
2410 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2411 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2412 { .parent = NULL },
2413};
2414
2415static struct clk utmi_p1_gfclk_ck = {
2416 .name = "utmi_p1_gfclk_ck",
2417 .parent = &init_60m_fclk,
2418 .clksel = utmi_p1_gfclk_sel,
2419 .init = &omap2_init_clksel_parent,
2420 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2421 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2422 .ops = &clkops_null,
2423 .recalc = &omap2_clksel_recalc,
972c5427
RN		 2424};
2425
2426static const struct clksel utmi_p2_gfclk_sel[] = {
2427 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2428 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2429 { .parent = NULL },
2430};
2431
2432static struct clk utmi_p2_gfclk_ck = {
2433 .name = "utmi_p2_gfclk_ck",
2434 .parent = &init_60m_fclk,
2435 .clksel = utmi_p2_gfclk_sel,
2436 .init = &omap2_init_clksel_parent,
2437 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2438 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2439 .ops = &clkops_null,
2440 .recalc = &omap2_clksel_recalc,
972c5427
RN		 2441};
2442
2443/*
2444 * clkdev
2445 */
2446
2447static struct omap_clk omap44xx_clks[] = {
2448 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
2449 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
2450 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
2451 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
2452 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
2453 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
2454 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
2455 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
2456 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
2457 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
2458 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
2459 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
2460 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
2461 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
2462 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
2463 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
2464 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
2465 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
2466 CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X),
2467 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
2468 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
2469 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
2470 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
2471 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
2472 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
2473 CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X),
2474 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
2475 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
2476 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X),
2477 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
2478 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
2479 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
2480 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X),
2481 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
2482 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
2483 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
2484 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X),
2485 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
2486 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
2487 CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X),
2488 CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X),
2489 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
2490 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
2491 CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X),
2492 CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X),
2493 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
2494 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
2495 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
2496 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
2497 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
2498 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
2499 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
2500 CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X),
2501 CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X),
2502 CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X),
2503 CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X),
2504 CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X),
2505 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
2506 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
2507 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
2508 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
2509 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
2510 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
2511 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
2512 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
2513 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
2514 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
2515 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
2516 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
2517 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
2518 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
2519 CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
2520 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
2521 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
2522 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
2523 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
2524 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
2525 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
2526 CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
2527 CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
2528 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
2529 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
2530 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
2531 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
2532 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
2533 CLK(NULL, "aes1_ck", &aes1_ck, CK_443X),
2534 CLK(NULL, "aes2_ck", &aes2_ck, CK_443X),
2535 CLK(NULL, "aess_ck", &aess_ck, CK_443X),
2536 CLK(NULL, "cust_efuse_ck", &cust_efuse_ck, CK_443X),
2537 CLK(NULL, "des3des_ck", &des3des_ck, CK_443X),
2538 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
2539 CLK(NULL, "dmic_ck", &dmic_ck, CK_443X),
2540 CLK(NULL, "dss_ck", &dss_ck, CK_443X),
2541 CLK(NULL, "ducati_ck", &ducati_ck, CK_443X),
2542 CLK(NULL, "emif1_ck", &emif1_ck, CK_443X),
2543 CLK(NULL, "emif2_ck", &emif2_ck, CK_443X),
2544 CLK(NULL, "fdif_ck", &fdif_ck, CK_443X),
2545 CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X),
2546 CLK(NULL, "gfx_ck", &gfx_ck, CK_443X),
2547 CLK(NULL, "gpio1_ck", &gpio1_ck, CK_443X),
2548 CLK(NULL, "gpio2_ck", &gpio2_ck, CK_443X),
2549 CLK(NULL, "gpio3_ck", &gpio3_ck, CK_443X),
2550 CLK(NULL, "gpio4_ck", &gpio4_ck, CK_443X),
2551 CLK(NULL, "gpio5_ck", &gpio5_ck, CK_443X),
2552 CLK(NULL, "gpio6_ck", &gpio6_ck, CK_443X),
2553 CLK(NULL, "gpmc_ck", &gpmc_ck, CK_443X),
2554 CLK(NULL, "gptimer1_ck", &gptimer1_ck, CK_443X),
2555 CLK(NULL, "gptimer10_ck", &gptimer10_ck, CK_443X),
2556 CLK(NULL, "gptimer11_ck", &gptimer11_ck, CK_443X),
2557 CLK(NULL, "gptimer2_ck", &gptimer2_ck, CK_443X),
2558 CLK(NULL, "gptimer3_ck", &gptimer3_ck, CK_443X),
2559 CLK(NULL, "gptimer4_ck", &gptimer4_ck, CK_443X),
2560 CLK(NULL, "gptimer5_ck", &gptimer5_ck, CK_443X),
2561 CLK(NULL, "gptimer6_ck", &gptimer6_ck, CK_443X),
2562 CLK(NULL, "gptimer7_ck", &gptimer7_ck, CK_443X),
2563 CLK(NULL, "gptimer8_ck", &gptimer8_ck, CK_443X),
2564 CLK(NULL, "gptimer9_ck", &gptimer9_ck, CK_443X),
2565 CLK("omap2_hdq.0", "ick", &hdq1w_ck, CK_443X),
2566 CLK(NULL, "hsi_ck", &hsi_ck, CK_443X),
2567 CLK("i2c_omap.1", "ick", &i2c1_ck, CK_443X),
2568 CLK("i2c_omap.2", "ick", &i2c2_ck, CK_443X),
2569 CLK("i2c_omap.3", "ick", &i2c3_ck, CK_443X),
2570 CLK("i2c_omap.4", "ick", &i2c4_ck, CK_443X),
2571 CLK(NULL, "iss_ck", &iss_ck, CK_443X),
2572 CLK(NULL, "ivahd_ck", &ivahd_ck, CK_443X),
2573 CLK(NULL, "keyboard_ck", &keyboard_ck, CK_443X),
2574 CLK(NULL, "l3_instr_interconnect_ck", &l3_instr_interconnect_ck, CK_443X),
2575 CLK(NULL, "l3_interconnect_3_ck", &l3_interconnect_3_ck, CK_443X),
2576 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
2577 CLK(NULL, "mcasp_ck", &mcasp_ck, CK_443X),
2578 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
2579 CLK("omap-mcbsp.1", "fck", &mcbsp1_ck, CK_443X),
2580 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
2581 CLK("omap-mcbsp.2", "fck", &mcbsp2_ck, CK_443X),
2582 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
2583 CLK("omap-mcbsp.3", "fck", &mcbsp3_ck, CK_443X),
2584 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
2585 CLK("omap-mcbsp.4", "fck", &mcbsp4_ck, CK_443X),
2586 CLK("omap2_mcspi.1", "fck", &mcspi1_ck, CK_443X),
2587 CLK("omap2_mcspi.2", "fck", &mcspi2_ck, CK_443X),
2588 CLK("omap2_mcspi.3", "fck", &mcspi3_ck, CK_443X),
2589 CLK("omap2_mcspi.4", "fck", &mcspi4_ck, CK_443X),
2590 CLK("mmci-omap-hs.0", "fck", &mmc1_ck, CK_443X),
2591 CLK("mmci-omap-hs.1", "fck", &mmc2_ck, CK_443X),
2592 CLK("mmci-omap-hs.2", "fck", &mmc3_ck, CK_443X),
2593 CLK("mmci-omap-hs.3", "fck", &mmc4_ck, CK_443X),
2594 CLK("mmci-omap-hs.4", "fck", &mmc5_ck, CK_443X),
2595 CLK(NULL, "ocp_wp1_ck", &ocp_wp1_ck, CK_443X),
2596 CLK(NULL, "pdm_ck", &pdm_ck, CK_443X),
2597 CLK(NULL, "pkaeip29_ck", &pkaeip29_ck, CK_443X),
2598 CLK("omap_rng", "ick", &rng_ck, CK_443X),
2599 CLK(NULL, "sha2md51_ck", &sha2md51_ck, CK_443X),
2600 CLK(NULL, "sl2_ck", &sl2_ck, CK_443X),
2601 CLK(NULL, "slimbus1_ck", &slimbus1_ck, CK_443X),
2602 CLK(NULL, "slimbus2_ck", &slimbus2_ck, CK_443X),
2603 CLK(NULL, "sr_core_ck", &sr_core_ck, CK_443X),
2604 CLK(NULL, "sr_iva_ck", &sr_iva_ck, CK_443X),
2605 CLK(NULL, "sr_mpu_ck", &sr_mpu_ck, CK_443X),
2606 CLK(NULL, "tesla_ck", &tesla_ck, CK_443X),
2607 CLK(NULL, "uart1_ck", &uart1_ck, CK_443X),
2608 CLK(NULL, "uart2_ck", &uart2_ck, CK_443X),
2609 CLK(NULL, "uart3_ck", &uart3_ck, CK_443X),
2610 CLK(NULL, "uart4_ck", &uart4_ck, CK_443X),
2611 CLK(NULL, "unipro1_ck", &unipro1_ck, CK_443X),
2612 CLK(NULL, "usb_host_ck", &usb_host_ck, CK_443X),
2613 CLK(NULL, "usb_host_fs_ck", &usb_host_fs_ck, CK_443X),
2614 CLK("musb_hdrc", "ick", &usb_otg_ck, CK_443X),
2615 CLK(NULL, "usb_tll_ck", &usb_tll_ck, CK_443X),
2616 CLK(NULL, "usbphyocp2scp_ck", &usbphyocp2scp_ck, CK_443X),
2617 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
2618 CLK("omap_wdt", "fck", &wdt2_ck, CK_443X),
2619 CLK(NULL, "wdt3_ck", &wdt3_ck, CK_443X),
2620 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X),
2621 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2622 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
2623 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2624 CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X),
2625 CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X),
2626};
2627
e80a9729 2628int __init omap4xxx_clk_init(void)
972c5427 2629{
972c5427 2630 struct omap_clk *c;
972c5427
RN		 2631 u32 cpu_clkflg;
2632
2633 if (cpu_is_omap44xx()) {
2634 cpu_mask = RATE_IN_4430;
2635 cpu_clkflg = CK_443X;
2636 }
2637
2638 clk_init(&omap2_clk_functions);
2639
2640 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2641 c++)
2642 clk_preinit(c->lk.clk);
2643
2644 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2645 c++)
2646 if (c->cpu & cpu_clkflg) {
2647 clkdev_add(&c->lk);
2648 clk_register(c->lk.clk);
972c5427 2649 omap2_init_clk_clkdm(c->lk.clk);
972c5427
RN		 2650 }
2651
2652 recalculate_root_clocks();
2653
2654 /*
2655 * Only enable those clocks we will need, let the drivers
2656 * enable other clocks as necessary
2657 */
2658 clk_enable_init_clocks();
2659
2660 return 0;
2661}
kernel source for telekom puls (alcatel/mediatek)