Commit | Line | Data |
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972c5427 RN |
1 | /* |
2 | * OMAP4 Clock data | |
3 | * | |
54776050 RN |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
972c5427 RN |
6 | * |
7 | * Paul Walmsley (paul@pwsan.com) | |
8 | * Rajendra Nayak (rnayak@ti.com) | |
9 | * Benoit Cousson (b-cousson@ti.com) | |
10 | * | |
11 | * This file is automatically generated from the OMAP hardware databases. | |
12 | * We respectfully ask that any modifications to this file be coordinated | |
13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
14 | * authors above to ensure that the autogeneration scripts are kept | |
15 | * up-to-date with the file contents. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
76cf5295 RN |
20 | * |
21 | * XXX Some of the ES1 clocks have been removed/changed; once support | |
22 | * is added for discriminating clocks by ES level, these should be added back | |
23 | * in. | |
972c5427 RN |
24 | */ |
25 | ||
26 | #include <linux/kernel.h> | |
93340a22 | 27 | #include <linux/list.h> |
972c5427 | 28 | #include <linux/clk.h> |
972c5427 RN |
29 | #include <plat/clkdev_omap.h> |
30 | ||
31 | #include "clock.h" | |
32 | #include "clock44xx.h" | |
d198b514 PW |
33 | #include "cm1_44xx.h" |
34 | #include "cm2_44xx.h" | |
972c5427 | 35 | #include "cm-regbits-44xx.h" |
59fb659b | 36 | #include "prm44xx.h" |
d198b514 | 37 | #include "prm44xx.h" |
972c5427 | 38 | #include "prm-regbits-44xx.h" |
4814ced5 | 39 | #include "control.h" |
e0cb70c5 | 40 | #include "scrm44xx.h" |
972c5427 | 41 | |
59fb659b PW |
42 | /* OMAP4 modulemode control */ |
43 | #define OMAP4430_MODULEMODE_HWCTRL 0 | |
44 | #define OMAP4430_MODULEMODE_SWCTRL 1 | |
45 | ||
972c5427 RN |
46 | /* Root clocks */ |
47 | ||
48 | static struct clk extalt_clkin_ck = { | |
49 | .name = "extalt_clkin_ck", | |
50 | .rate = 59000000, | |
51 | .ops = &clkops_null, | |
972c5427 RN |
52 | }; |
53 | ||
54 | static struct clk pad_clks_ck = { | |
55 | .name = "pad_clks_ck", | |
56 | .rate = 12000000, | |
d9b98f5f BC |
57 | .ops = &clkops_omap2_dflt, |
58 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, | |
59 | .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, | |
972c5427 RN |
60 | }; |
61 | ||
62 | static struct clk pad_slimbus_core_clks_ck = { | |
63 | .name = "pad_slimbus_core_clks_ck", | |
64 | .rate = 12000000, | |
65 | .ops = &clkops_null, | |
972c5427 RN |
66 | }; |
67 | ||
68 | static struct clk secure_32k_clk_src_ck = { | |
69 | .name = "secure_32k_clk_src_ck", | |
70 | .rate = 32768, | |
71 | .ops = &clkops_null, | |
972c5427 RN |
72 | }; |
73 | ||
74 | static struct clk slimbus_clk = { | |
75 | .name = "slimbus_clk", | |
76 | .rate = 12000000, | |
d9b98f5f BC |
77 | .ops = &clkops_omap2_dflt, |
78 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, | |
79 | .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, | |
972c5427 RN |
80 | }; |
81 | ||
82 | static struct clk sys_32k_ck = { | |
83 | .name = "sys_32k_ck", | |
84 | .rate = 32768, | |
85 | .ops = &clkops_null, | |
972c5427 RN |
86 | }; |
87 | ||
88 | static struct clk virt_12000000_ck = { | |
89 | .name = "virt_12000000_ck", | |
90 | .ops = &clkops_null, | |
91 | .rate = 12000000, | |
92 | }; | |
93 | ||
94 | static struct clk virt_13000000_ck = { | |
95 | .name = "virt_13000000_ck", | |
96 | .ops = &clkops_null, | |
97 | .rate = 13000000, | |
98 | }; | |
99 | ||
100 | static struct clk virt_16800000_ck = { | |
101 | .name = "virt_16800000_ck", | |
102 | .ops = &clkops_null, | |
103 | .rate = 16800000, | |
104 | }; | |
105 | ||
106 | static struct clk virt_19200000_ck = { | |
107 | .name = "virt_19200000_ck", | |
108 | .ops = &clkops_null, | |
109 | .rate = 19200000, | |
110 | }; | |
111 | ||
112 | static struct clk virt_26000000_ck = { | |
113 | .name = "virt_26000000_ck", | |
114 | .ops = &clkops_null, | |
115 | .rate = 26000000, | |
116 | }; | |
117 | ||
118 | static struct clk virt_27000000_ck = { | |
119 | .name = "virt_27000000_ck", | |
120 | .ops = &clkops_null, | |
121 | .rate = 27000000, | |
122 | }; | |
123 | ||
124 | static struct clk virt_38400000_ck = { | |
125 | .name = "virt_38400000_ck", | |
126 | .ops = &clkops_null, | |
127 | .rate = 38400000, | |
128 | }; | |
129 | ||
130 | static const struct clksel_rate div_1_0_rates[] = { | |
131 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
132 | { .div = 0 }, | |
133 | }; | |
134 | ||
135 | static const struct clksel_rate div_1_1_rates[] = { | |
136 | { .div = 1, .val = 1, .flags = RATE_IN_4430 }, | |
137 | { .div = 0 }, | |
138 | }; | |
139 | ||
140 | static const struct clksel_rate div_1_2_rates[] = { | |
141 | { .div = 1, .val = 2, .flags = RATE_IN_4430 }, | |
142 | { .div = 0 }, | |
143 | }; | |
144 | ||
145 | static const struct clksel_rate div_1_3_rates[] = { | |
146 | { .div = 1, .val = 3, .flags = RATE_IN_4430 }, | |
147 | { .div = 0 }, | |
148 | }; | |
149 | ||
150 | static const struct clksel_rate div_1_4_rates[] = { | |
151 | { .div = 1, .val = 4, .flags = RATE_IN_4430 }, | |
152 | { .div = 0 }, | |
153 | }; | |
154 | ||
155 | static const struct clksel_rate div_1_5_rates[] = { | |
156 | { .div = 1, .val = 5, .flags = RATE_IN_4430 }, | |
157 | { .div = 0 }, | |
158 | }; | |
159 | ||
160 | static const struct clksel_rate div_1_6_rates[] = { | |
161 | { .div = 1, .val = 6, .flags = RATE_IN_4430 }, | |
162 | { .div = 0 }, | |
163 | }; | |
164 | ||
165 | static const struct clksel_rate div_1_7_rates[] = { | |
166 | { .div = 1, .val = 7, .flags = RATE_IN_4430 }, | |
167 | { .div = 0 }, | |
168 | }; | |
169 | ||
170 | static const struct clksel sys_clkin_sel[] = { | |
171 | { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, | |
172 | { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, | |
173 | { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, | |
174 | { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, | |
175 | { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, | |
176 | { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, | |
177 | { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, | |
178 | { .parent = NULL }, | |
179 | }; | |
180 | ||
181 | static struct clk sys_clkin_ck = { | |
182 | .name = "sys_clkin_ck", | |
183 | .rate = 38400000, | |
184 | .clksel = sys_clkin_sel, | |
185 | .init = &omap2_init_clksel_parent, | |
186 | .clksel_reg = OMAP4430_CM_SYS_CLKSEL, | |
187 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, | |
188 | .ops = &clkops_null, | |
189 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
190 | }; |
191 | ||
76cf5295 RN |
192 | static struct clk tie_low_clock_ck = { |
193 | .name = "tie_low_clock_ck", | |
194 | .rate = 0, | |
195 | .ops = &clkops_null, | |
196 | }; | |
197 | ||
972c5427 RN |
198 | static struct clk utmi_phy_clkout_ck = { |
199 | .name = "utmi_phy_clkout_ck", | |
76cf5295 | 200 | .rate = 60000000, |
972c5427 | 201 | .ops = &clkops_null, |
972c5427 RN |
202 | }; |
203 | ||
204 | static struct clk xclk60mhsp1_ck = { | |
205 | .name = "xclk60mhsp1_ck", | |
76cf5295 | 206 | .rate = 60000000, |
972c5427 | 207 | .ops = &clkops_null, |
972c5427 RN |
208 | }; |
209 | ||
210 | static struct clk xclk60mhsp2_ck = { | |
211 | .name = "xclk60mhsp2_ck", | |
76cf5295 | 212 | .rate = 60000000, |
972c5427 | 213 | .ops = &clkops_null, |
972c5427 RN |
214 | }; |
215 | ||
216 | static struct clk xclk60motg_ck = { | |
217 | .name = "xclk60motg_ck", | |
218 | .rate = 60000000, | |
219 | .ops = &clkops_null, | |
972c5427 RN |
220 | }; |
221 | ||
222 | /* Module clocks and DPLL outputs */ | |
223 | ||
76cf5295 RN |
224 | static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { |
225 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
226 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | |
972c5427 RN |
227 | { .parent = NULL }, |
228 | }; | |
229 | ||
76cf5295 RN |
230 | static struct clk abe_dpll_bypass_clk_mux_ck = { |
231 | .name = "abe_dpll_bypass_clk_mux_ck", | |
972c5427 | 232 | .parent = &sys_clkin_ck, |
972c5427 | 233 | .ops = &clkops_null, |
76cf5295 | 234 | .recalc = &followparent_recalc, |
972c5427 RN |
235 | }; |
236 | ||
237 | static struct clk abe_dpll_refclk_mux_ck = { | |
238 | .name = "abe_dpll_refclk_mux_ck", | |
76cf5295 RN |
239 | .parent = &sys_clkin_ck, |
240 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
972c5427 RN |
241 | .init = &omap2_init_clksel_parent, |
242 | .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, | |
243 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
244 | .ops = &clkops_null, | |
245 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
246 | }; |
247 | ||
248 | /* DPLL_ABE */ | |
249 | static struct dpll_data dpll_abe_dd = { | |
250 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, | |
76cf5295 | 251 | .clk_bypass = &abe_dpll_bypass_clk_mux_ck, |
972c5427 RN |
252 | .clk_ref = &abe_dpll_refclk_mux_ck, |
253 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, | |
254 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
255 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, | |
256 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, | |
257 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
258 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
259 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
260 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
261 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
262 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
263 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
264 | .min_divider = 1, | |
265 | }; | |
266 | ||
267 | ||
268 | static struct clk dpll_abe_ck = { | |
269 | .name = "dpll_abe_ck", | |
270 | .parent = &abe_dpll_refclk_mux_ck, | |
271 | .dpll_data = &dpll_abe_dd, | |
911bd739 | 272 | .init = &omap2_init_dpll_parent, |
657ebfad | 273 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
274 | .recalc = &omap3_dpll_recalc, |
275 | .round_rate = &omap2_dpll_round_rate, | |
276 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
277 | }; |
278 | ||
032b5a7e TG |
279 | static struct clk dpll_abe_x2_ck = { |
280 | .name = "dpll_abe_x2_ck", | |
281 | .parent = &dpll_abe_ck, | |
282 | .ops = &clkops_null, | |
283 | .recalc = &omap3_clkoutx2_recalc, | |
284 | }; | |
285 | ||
286 | static const struct clksel_rate div31_1to31_rates[] = { | |
287 | { .div = 1, .val = 1, .flags = RATE_IN_4430 }, | |
288 | { .div = 2, .val = 2, .flags = RATE_IN_4430 }, | |
289 | { .div = 3, .val = 3, .flags = RATE_IN_4430 }, | |
290 | { .div = 4, .val = 4, .flags = RATE_IN_4430 }, | |
291 | { .div = 5, .val = 5, .flags = RATE_IN_4430 }, | |
292 | { .div = 6, .val = 6, .flags = RATE_IN_4430 }, | |
293 | { .div = 7, .val = 7, .flags = RATE_IN_4430 }, | |
294 | { .div = 8, .val = 8, .flags = RATE_IN_4430 }, | |
295 | { .div = 9, .val = 9, .flags = RATE_IN_4430 }, | |
296 | { .div = 10, .val = 10, .flags = RATE_IN_4430 }, | |
297 | { .div = 11, .val = 11, .flags = RATE_IN_4430 }, | |
298 | { .div = 12, .val = 12, .flags = RATE_IN_4430 }, | |
299 | { .div = 13, .val = 13, .flags = RATE_IN_4430 }, | |
300 | { .div = 14, .val = 14, .flags = RATE_IN_4430 }, | |
301 | { .div = 15, .val = 15, .flags = RATE_IN_4430 }, | |
302 | { .div = 16, .val = 16, .flags = RATE_IN_4430 }, | |
303 | { .div = 17, .val = 17, .flags = RATE_IN_4430 }, | |
304 | { .div = 18, .val = 18, .flags = RATE_IN_4430 }, | |
305 | { .div = 19, .val = 19, .flags = RATE_IN_4430 }, | |
306 | { .div = 20, .val = 20, .flags = RATE_IN_4430 }, | |
307 | { .div = 21, .val = 21, .flags = RATE_IN_4430 }, | |
308 | { .div = 22, .val = 22, .flags = RATE_IN_4430 }, | |
309 | { .div = 23, .val = 23, .flags = RATE_IN_4430 }, | |
310 | { .div = 24, .val = 24, .flags = RATE_IN_4430 }, | |
311 | { .div = 25, .val = 25, .flags = RATE_IN_4430 }, | |
312 | { .div = 26, .val = 26, .flags = RATE_IN_4430 }, | |
313 | { .div = 27, .val = 27, .flags = RATE_IN_4430 }, | |
314 | { .div = 28, .val = 28, .flags = RATE_IN_4430 }, | |
315 | { .div = 29, .val = 29, .flags = RATE_IN_4430 }, | |
316 | { .div = 30, .val = 30, .flags = RATE_IN_4430 }, | |
317 | { .div = 31, .val = 31, .flags = RATE_IN_4430 }, | |
318 | { .div = 0 }, | |
319 | }; | |
320 | ||
321 | static const struct clksel dpll_abe_m2x2_div[] = { | |
322 | { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, | |
323 | { .parent = NULL }, | |
324 | }; | |
325 | ||
972c5427 RN |
326 | static struct clk dpll_abe_m2x2_ck = { |
327 | .name = "dpll_abe_m2x2_ck", | |
032b5a7e TG |
328 | .parent = &dpll_abe_x2_ck, |
329 | .clksel = dpll_abe_m2x2_div, | |
330 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, | |
331 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
972c5427 | 332 | .ops = &clkops_null, |
032b5a7e TG |
333 | .recalc = &omap2_clksel_recalc, |
334 | .round_rate = &omap2_clksel_round_rate, | |
335 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
336 | }; |
337 | ||
338 | static struct clk abe_24m_fclk = { | |
339 | .name = "abe_24m_fclk", | |
340 | .parent = &dpll_abe_m2x2_ck, | |
341 | .ops = &clkops_null, | |
342 | .recalc = &followparent_recalc, | |
972c5427 RN |
343 | }; |
344 | ||
345 | static const struct clksel_rate div3_1to4_rates[] = { | |
346 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
347 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | |
348 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, | |
349 | { .div = 0 }, | |
350 | }; | |
351 | ||
352 | static const struct clksel abe_clk_div[] = { | |
353 | { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, | |
354 | { .parent = NULL }, | |
355 | }; | |
356 | ||
357 | static struct clk abe_clk = { | |
358 | .name = "abe_clk", | |
359 | .parent = &dpll_abe_m2x2_ck, | |
360 | .clksel = abe_clk_div, | |
361 | .clksel_reg = OMAP4430_CM_CLKSEL_ABE, | |
362 | .clksel_mask = OMAP4430_CLKSEL_OPP_MASK, | |
363 | .ops = &clkops_null, | |
364 | .recalc = &omap2_clksel_recalc, | |
365 | .round_rate = &omap2_clksel_round_rate, | |
366 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
367 | }; |
368 | ||
76cf5295 RN |
369 | static const struct clksel_rate div2_1to2_rates[] = { |
370 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
371 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | |
372 | { .div = 0 }, | |
373 | }; | |
374 | ||
972c5427 RN |
375 | static const struct clksel aess_fclk_div[] = { |
376 | { .parent = &abe_clk, .rates = div2_1to2_rates }, | |
377 | { .parent = NULL }, | |
378 | }; | |
379 | ||
380 | static struct clk aess_fclk = { | |
381 | .name = "aess_fclk", | |
382 | .parent = &abe_clk, | |
383 | .clksel = aess_fclk_div, | |
384 | .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | |
385 | .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, | |
386 | .ops = &clkops_null, | |
387 | .recalc = &omap2_clksel_recalc, | |
388 | .round_rate = &omap2_clksel_round_rate, | |
389 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
390 | }; |
391 | ||
032b5a7e TG |
392 | static struct clk dpll_abe_m3x2_ck = { |
393 | .name = "dpll_abe_m3x2_ck", | |
394 | .parent = &dpll_abe_x2_ck, | |
395 | .clksel = dpll_abe_m2x2_div, | |
972c5427 RN |
396 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, |
397 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
398 | .ops = &clkops_null, | |
399 | .recalc = &omap2_clksel_recalc, | |
400 | .round_rate = &omap2_clksel_round_rate, | |
401 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
402 | }; |
403 | ||
404 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { | |
76cf5295 | 405 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
032b5a7e | 406 | { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates }, |
972c5427 RN |
407 | { .parent = NULL }, |
408 | }; | |
409 | ||
410 | static struct clk core_hsd_byp_clk_mux_ck = { | |
411 | .name = "core_hsd_byp_clk_mux_ck", | |
76cf5295 | 412 | .parent = &sys_clkin_ck, |
972c5427 RN |
413 | .clksel = core_hsd_byp_clk_mux_sel, |
414 | .init = &omap2_init_clksel_parent, | |
415 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, | |
416 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | |
417 | .ops = &clkops_null, | |
418 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
419 | }; |
420 | ||
421 | /* DPLL_CORE */ | |
422 | static struct dpll_data dpll_core_dd = { | |
423 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, | |
424 | .clk_bypass = &core_hsd_byp_clk_mux_ck, | |
76cf5295 | 425 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
426 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, |
427 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
428 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, | |
429 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, | |
430 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
431 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
432 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
433 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
434 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
435 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
436 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
437 | .min_divider = 1, | |
438 | }; | |
439 | ||
440 | ||
441 | static struct clk dpll_core_ck = { | |
442 | .name = "dpll_core_ck", | |
76cf5295 | 443 | .parent = &sys_clkin_ck, |
972c5427 | 444 | .dpll_data = &dpll_core_dd, |
911bd739 | 445 | .init = &omap2_init_dpll_parent, |
972c5427 RN |
446 | .ops = &clkops_null, |
447 | .recalc = &omap3_dpll_recalc, | |
972c5427 RN |
448 | }; |
449 | ||
032b5a7e TG |
450 | static struct clk dpll_core_x2_ck = { |
451 | .name = "dpll_core_x2_ck", | |
452 | .parent = &dpll_core_ck, | |
453 | .ops = &clkops_null, | |
454 | .recalc = &omap3_clkoutx2_recalc, | |
455 | }; | |
456 | ||
457 | static const struct clksel dpll_core_m6x2_div[] = { | |
458 | { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, | |
972c5427 RN |
459 | { .parent = NULL }, |
460 | }; | |
461 | ||
032b5a7e TG |
462 | static struct clk dpll_core_m6x2_ck = { |
463 | .name = "dpll_core_m6x2_ck", | |
464 | .parent = &dpll_core_x2_ck, | |
465 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
466 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, |
467 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, | |
468 | .ops = &clkops_null, | |
469 | .recalc = &omap2_clksel_recalc, | |
470 | .round_rate = &omap2_clksel_round_rate, | |
471 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
472 | }; |
473 | ||
474 | static const struct clksel dbgclk_mux_sel[] = { | |
475 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
032b5a7e | 476 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
972c5427 RN |
477 | { .parent = NULL }, |
478 | }; | |
479 | ||
480 | static struct clk dbgclk_mux_ck = { | |
481 | .name = "dbgclk_mux_ck", | |
482 | .parent = &sys_clkin_ck, | |
483 | .ops = &clkops_null, | |
484 | .recalc = &followparent_recalc, | |
972c5427 RN |
485 | }; |
486 | ||
032b5a7e TG |
487 | static const struct clksel dpll_core_m2_div[] = { |
488 | { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, | |
489 | { .parent = NULL }, | |
490 | }; | |
491 | ||
972c5427 RN |
492 | static struct clk dpll_core_m2_ck = { |
493 | .name = "dpll_core_m2_ck", | |
494 | .parent = &dpll_core_ck, | |
032b5a7e | 495 | .clksel = dpll_core_m2_div, |
972c5427 RN |
496 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, |
497 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
498 | .ops = &clkops_null, | |
499 | .recalc = &omap2_clksel_recalc, | |
500 | .round_rate = &omap2_clksel_round_rate, | |
501 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
502 | }; |
503 | ||
504 | static struct clk ddrphy_ck = { | |
505 | .name = "ddrphy_ck", | |
506 | .parent = &dpll_core_m2_ck, | |
507 | .ops = &clkops_null, | |
508 | .recalc = &followparent_recalc, | |
972c5427 RN |
509 | }; |
510 | ||
032b5a7e TG |
511 | static struct clk dpll_core_m5x2_ck = { |
512 | .name = "dpll_core_m5x2_ck", | |
513 | .parent = &dpll_core_x2_ck, | |
514 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
515 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, |
516 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | |
517 | .ops = &clkops_null, | |
518 | .recalc = &omap2_clksel_recalc, | |
519 | .round_rate = &omap2_clksel_round_rate, | |
520 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
521 | }; |
522 | ||
523 | static const struct clksel div_core_div[] = { | |
032b5a7e | 524 | { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates }, |
972c5427 RN |
525 | { .parent = NULL }, |
526 | }; | |
527 | ||
528 | static struct clk div_core_ck = { | |
529 | .name = "div_core_ck", | |
032b5a7e | 530 | .parent = &dpll_core_m5x2_ck, |
972c5427 RN |
531 | .clksel = div_core_div, |
532 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | |
533 | .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, | |
534 | .ops = &clkops_null, | |
535 | .recalc = &omap2_clksel_recalc, | |
536 | .round_rate = &omap2_clksel_round_rate, | |
537 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
538 | }; |
539 | ||
540 | static const struct clksel_rate div4_1to8_rates[] = { | |
541 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
542 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | |
543 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, | |
544 | { .div = 8, .val = 3, .flags = RATE_IN_4430 }, | |
545 | { .div = 0 }, | |
546 | }; | |
547 | ||
548 | static const struct clksel div_iva_hs_clk_div[] = { | |
032b5a7e | 549 | { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates }, |
972c5427 RN |
550 | { .parent = NULL }, |
551 | }; | |
552 | ||
553 | static struct clk div_iva_hs_clk = { | |
554 | .name = "div_iva_hs_clk", | |
032b5a7e | 555 | .parent = &dpll_core_m5x2_ck, |
972c5427 RN |
556 | .clksel = div_iva_hs_clk_div, |
557 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, | |
558 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, | |
559 | .ops = &clkops_null, | |
560 | .recalc = &omap2_clksel_recalc, | |
561 | .round_rate = &omap2_clksel_round_rate, | |
562 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
563 | }; |
564 | ||
565 | static struct clk div_mpu_hs_clk = { | |
566 | .name = "div_mpu_hs_clk", | |
032b5a7e | 567 | .parent = &dpll_core_m5x2_ck, |
972c5427 RN |
568 | .clksel = div_iva_hs_clk_div, |
569 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, | |
570 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, | |
571 | .ops = &clkops_null, | |
572 | .recalc = &omap2_clksel_recalc, | |
573 | .round_rate = &omap2_clksel_round_rate, | |
574 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
575 | }; |
576 | ||
032b5a7e TG |
577 | static struct clk dpll_core_m4x2_ck = { |
578 | .name = "dpll_core_m4x2_ck", | |
579 | .parent = &dpll_core_x2_ck, | |
580 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
581 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, |
582 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | |
583 | .ops = &clkops_null, | |
584 | .recalc = &omap2_clksel_recalc, | |
585 | .round_rate = &omap2_clksel_round_rate, | |
586 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
587 | }; |
588 | ||
589 | static struct clk dll_clk_div_ck = { | |
590 | .name = "dll_clk_div_ck", | |
032b5a7e | 591 | .parent = &dpll_core_m4x2_ck, |
972c5427 RN |
592 | .ops = &clkops_null, |
593 | .recalc = &followparent_recalc, | |
972c5427 RN |
594 | }; |
595 | ||
032b5a7e TG |
596 | static const struct clksel dpll_abe_m2_div[] = { |
597 | { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, | |
598 | { .parent = NULL }, | |
599 | }; | |
600 | ||
972c5427 RN |
601 | static struct clk dpll_abe_m2_ck = { |
602 | .name = "dpll_abe_m2_ck", | |
603 | .parent = &dpll_abe_ck, | |
032b5a7e | 604 | .clksel = dpll_abe_m2_div, |
972c5427 RN |
605 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, |
606 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
607 | .ops = &clkops_null, | |
608 | .recalc = &omap2_clksel_recalc, | |
609 | .round_rate = &omap2_clksel_round_rate, | |
610 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
611 | }; |
612 | ||
032b5a7e TG |
613 | static struct clk dpll_core_m3x2_ck = { |
614 | .name = "dpll_core_m3x2_ck", | |
615 | .parent = &dpll_core_x2_ck, | |
616 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
617 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, |
618 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
cb13459b RN |
619 | .ops = &clkops_omap2_dflt, |
620 | .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, | |
621 | .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, | |
972c5427 RN |
622 | .recalc = &omap2_clksel_recalc, |
623 | .round_rate = &omap2_clksel_round_rate, | |
624 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
625 | }; |
626 | ||
032b5a7e TG |
627 | static struct clk dpll_core_m7x2_ck = { |
628 | .name = "dpll_core_m7x2_ck", | |
629 | .parent = &dpll_core_x2_ck, | |
630 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
631 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, |
632 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, | |
633 | .ops = &clkops_null, | |
634 | .recalc = &omap2_clksel_recalc, | |
635 | .round_rate = &omap2_clksel_round_rate, | |
636 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
637 | }; |
638 | ||
639 | static const struct clksel iva_hsd_byp_clk_mux_sel[] = { | |
76cf5295 | 640 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
972c5427 RN |
641 | { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, |
642 | { .parent = NULL }, | |
643 | }; | |
644 | ||
645 | static struct clk iva_hsd_byp_clk_mux_ck = { | |
646 | .name = "iva_hsd_byp_clk_mux_ck", | |
76cf5295 | 647 | .parent = &sys_clkin_ck, |
768ab94f JB |
648 | .clksel = iva_hsd_byp_clk_mux_sel, |
649 | .init = &omap2_init_clksel_parent, | |
650 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, | |
651 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | |
972c5427 | 652 | .ops = &clkops_null, |
768ab94f | 653 | .recalc = &omap2_clksel_recalc, |
972c5427 RN |
654 | }; |
655 | ||
656 | /* DPLL_IVA */ | |
657 | static struct dpll_data dpll_iva_dd = { | |
658 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, | |
659 | .clk_bypass = &iva_hsd_byp_clk_mux_ck, | |
76cf5295 | 660 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
661 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, |
662 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
663 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, | |
664 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, | |
665 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
666 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
667 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
668 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
669 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
670 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
671 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
672 | .min_divider = 1, | |
673 | }; | |
674 | ||
675 | ||
676 | static struct clk dpll_iva_ck = { | |
677 | .name = "dpll_iva_ck", | |
76cf5295 | 678 | .parent = &sys_clkin_ck, |
972c5427 | 679 | .dpll_data = &dpll_iva_dd, |
911bd739 | 680 | .init = &omap2_init_dpll_parent, |
657ebfad | 681 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
682 | .recalc = &omap3_dpll_recalc, |
683 | .round_rate = &omap2_dpll_round_rate, | |
684 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
685 | }; |
686 | ||
032b5a7e TG |
687 | static struct clk dpll_iva_x2_ck = { |
688 | .name = "dpll_iva_x2_ck", | |
689 | .parent = &dpll_iva_ck, | |
690 | .ops = &clkops_null, | |
691 | .recalc = &omap3_clkoutx2_recalc, | |
692 | }; | |
693 | ||
694 | static const struct clksel dpll_iva_m4x2_div[] = { | |
695 | { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates }, | |
972c5427 RN |
696 | { .parent = NULL }, |
697 | }; | |
698 | ||
032b5a7e TG |
699 | static struct clk dpll_iva_m4x2_ck = { |
700 | .name = "dpll_iva_m4x2_ck", | |
701 | .parent = &dpll_iva_x2_ck, | |
702 | .clksel = dpll_iva_m4x2_div, | |
972c5427 RN |
703 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, |
704 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | |
705 | .ops = &clkops_null, | |
706 | .recalc = &omap2_clksel_recalc, | |
707 | .round_rate = &omap2_clksel_round_rate, | |
708 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
709 | }; |
710 | ||
032b5a7e TG |
711 | static struct clk dpll_iva_m5x2_ck = { |
712 | .name = "dpll_iva_m5x2_ck", | |
713 | .parent = &dpll_iva_x2_ck, | |
714 | .clksel = dpll_iva_m4x2_div, | |
972c5427 RN |
715 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, |
716 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | |
717 | .ops = &clkops_null, | |
718 | .recalc = &omap2_clksel_recalc, | |
719 | .round_rate = &omap2_clksel_round_rate, | |
720 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
721 | }; |
722 | ||
723 | /* DPLL_MPU */ | |
724 | static struct dpll_data dpll_mpu_dd = { | |
725 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, | |
726 | .clk_bypass = &div_mpu_hs_clk, | |
76cf5295 | 727 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
728 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, |
729 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
730 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, | |
731 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, | |
732 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
733 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
734 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
735 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
736 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
737 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
738 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
739 | .min_divider = 1, | |
740 | }; | |
741 | ||
742 | ||
743 | static struct clk dpll_mpu_ck = { | |
744 | .name = "dpll_mpu_ck", | |
76cf5295 | 745 | .parent = &sys_clkin_ck, |
972c5427 | 746 | .dpll_data = &dpll_mpu_dd, |
911bd739 | 747 | .init = &omap2_init_dpll_parent, |
657ebfad | 748 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
749 | .recalc = &omap3_dpll_recalc, |
750 | .round_rate = &omap2_dpll_round_rate, | |
751 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
752 | }; |
753 | ||
754 | static const struct clksel dpll_mpu_m2_div[] = { | |
755 | { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, | |
756 | { .parent = NULL }, | |
757 | }; | |
758 | ||
759 | static struct clk dpll_mpu_m2_ck = { | |
760 | .name = "dpll_mpu_m2_ck", | |
761 | .parent = &dpll_mpu_ck, | |
762 | .clksel = dpll_mpu_m2_div, | |
763 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, | |
764 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
765 | .ops = &clkops_null, | |
766 | .recalc = &omap2_clksel_recalc, | |
767 | .round_rate = &omap2_clksel_round_rate, | |
768 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
769 | }; |
770 | ||
771 | static struct clk per_hs_clk_div_ck = { | |
772 | .name = "per_hs_clk_div_ck", | |
032b5a7e | 773 | .parent = &dpll_abe_m3x2_ck, |
972c5427 RN |
774 | .ops = &clkops_null, |
775 | .recalc = &followparent_recalc, | |
972c5427 RN |
776 | }; |
777 | ||
778 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { | |
76cf5295 | 779 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
972c5427 RN |
780 | { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, |
781 | { .parent = NULL }, | |
782 | }; | |
783 | ||
784 | static struct clk per_hsd_byp_clk_mux_ck = { | |
785 | .name = "per_hsd_byp_clk_mux_ck", | |
76cf5295 | 786 | .parent = &sys_clkin_ck, |
972c5427 RN |
787 | .clksel = per_hsd_byp_clk_mux_sel, |
788 | .init = &omap2_init_clksel_parent, | |
789 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, | |
790 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | |
791 | .ops = &clkops_null, | |
792 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
793 | }; |
794 | ||
795 | /* DPLL_PER */ | |
796 | static struct dpll_data dpll_per_dd = { | |
797 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, | |
798 | .clk_bypass = &per_hsd_byp_clk_mux_ck, | |
76cf5295 | 799 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
800 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, |
801 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
802 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, | |
803 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, | |
804 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
805 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
806 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
807 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
808 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
809 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
810 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
811 | .min_divider = 1, | |
812 | }; | |
813 | ||
814 | ||
815 | static struct clk dpll_per_ck = { | |
816 | .name = "dpll_per_ck", | |
76cf5295 | 817 | .parent = &sys_clkin_ck, |
972c5427 | 818 | .dpll_data = &dpll_per_dd, |
911bd739 | 819 | .init = &omap2_init_dpll_parent, |
657ebfad | 820 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
821 | .recalc = &omap3_dpll_recalc, |
822 | .round_rate = &omap2_dpll_round_rate, | |
823 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
824 | }; |
825 | ||
826 | static const struct clksel dpll_per_m2_div[] = { | |
827 | { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, | |
828 | { .parent = NULL }, | |
829 | }; | |
830 | ||
831 | static struct clk dpll_per_m2_ck = { | |
832 | .name = "dpll_per_m2_ck", | |
833 | .parent = &dpll_per_ck, | |
834 | .clksel = dpll_per_m2_div, | |
835 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, | |
836 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
837 | .ops = &clkops_null, | |
838 | .recalc = &omap2_clksel_recalc, | |
839 | .round_rate = &omap2_clksel_round_rate, | |
840 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
841 | }; |
842 | ||
032b5a7e TG |
843 | static struct clk dpll_per_x2_ck = { |
844 | .name = "dpll_per_x2_ck", | |
845 | .parent = &dpll_per_ck, | |
846 | .ops = &clkops_null, | |
847 | .recalc = &omap3_clkoutx2_recalc, | |
848 | }; | |
849 | ||
850 | static const struct clksel dpll_per_m2x2_div[] = { | |
851 | { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, | |
852 | { .parent = NULL }, | |
853 | }; | |
854 | ||
972c5427 RN |
855 | static struct clk dpll_per_m2x2_ck = { |
856 | .name = "dpll_per_m2x2_ck", | |
032b5a7e TG |
857 | .parent = &dpll_per_x2_ck, |
858 | .clksel = dpll_per_m2x2_div, | |
859 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, | |
860 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
972c5427 | 861 | .ops = &clkops_null, |
032b5a7e TG |
862 | .recalc = &omap2_clksel_recalc, |
863 | .round_rate = &omap2_clksel_round_rate, | |
864 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
865 | }; |
866 | ||
032b5a7e TG |
867 | static struct clk dpll_per_m3x2_ck = { |
868 | .name = "dpll_per_m3x2_ck", | |
869 | .parent = &dpll_per_x2_ck, | |
870 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
871 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, |
872 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
cb13459b RN |
873 | .ops = &clkops_omap2_dflt, |
874 | .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, | |
875 | .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, | |
972c5427 RN |
876 | .recalc = &omap2_clksel_recalc, |
877 | .round_rate = &omap2_clksel_round_rate, | |
878 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
879 | }; |
880 | ||
032b5a7e TG |
881 | static struct clk dpll_per_m4x2_ck = { |
882 | .name = "dpll_per_m4x2_ck", | |
883 | .parent = &dpll_per_x2_ck, | |
884 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
885 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, |
886 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | |
887 | .ops = &clkops_null, | |
888 | .recalc = &omap2_clksel_recalc, | |
889 | .round_rate = &omap2_clksel_round_rate, | |
890 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
891 | }; |
892 | ||
032b5a7e TG |
893 | static struct clk dpll_per_m5x2_ck = { |
894 | .name = "dpll_per_m5x2_ck", | |
895 | .parent = &dpll_per_x2_ck, | |
896 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
897 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, |
898 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | |
899 | .ops = &clkops_null, | |
900 | .recalc = &omap2_clksel_recalc, | |
901 | .round_rate = &omap2_clksel_round_rate, | |
902 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
903 | }; |
904 | ||
032b5a7e TG |
905 | static struct clk dpll_per_m6x2_ck = { |
906 | .name = "dpll_per_m6x2_ck", | |
907 | .parent = &dpll_per_x2_ck, | |
908 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
909 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, |
910 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, | |
911 | .ops = &clkops_null, | |
912 | .recalc = &omap2_clksel_recalc, | |
913 | .round_rate = &omap2_clksel_round_rate, | |
914 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
915 | }; |
916 | ||
032b5a7e TG |
917 | static struct clk dpll_per_m7x2_ck = { |
918 | .name = "dpll_per_m7x2_ck", | |
919 | .parent = &dpll_per_x2_ck, | |
920 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
921 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, |
922 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, | |
923 | .ops = &clkops_null, | |
924 | .recalc = &omap2_clksel_recalc, | |
925 | .round_rate = &omap2_clksel_round_rate, | |
926 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
927 | }; |
928 | ||
929 | /* DPLL_UNIPRO */ | |
930 | static struct dpll_data dpll_unipro_dd = { | |
931 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, | |
76cf5295 RN |
932 | .clk_bypass = &sys_clkin_ck, |
933 | .clk_ref = &sys_clkin_ck, | |
972c5427 RN |
934 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, |
935 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
936 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, | |
937 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO, | |
938 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
939 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
940 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
941 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
942 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
943 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
944 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
945 | .min_divider = 1, | |
946 | }; | |
947 | ||
948 | ||
949 | static struct clk dpll_unipro_ck = { | |
950 | .name = "dpll_unipro_ck", | |
76cf5295 | 951 | .parent = &sys_clkin_ck, |
972c5427 | 952 | .dpll_data = &dpll_unipro_dd, |
911bd739 | 953 | .init = &omap2_init_dpll_parent, |
657ebfad | 954 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
955 | .recalc = &omap3_dpll_recalc, |
956 | .round_rate = &omap2_dpll_round_rate, | |
957 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
958 | }; |
959 | ||
032b5a7e TG |
960 | static struct clk dpll_unipro_x2_ck = { |
961 | .name = "dpll_unipro_x2_ck", | |
962 | .parent = &dpll_unipro_ck, | |
963 | .ops = &clkops_null, | |
964 | .recalc = &omap3_clkoutx2_recalc, | |
965 | }; | |
966 | ||
972c5427 | 967 | static const struct clksel dpll_unipro_m2x2_div[] = { |
032b5a7e | 968 | { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates }, |
972c5427 RN |
969 | { .parent = NULL }, |
970 | }; | |
971 | ||
972 | static struct clk dpll_unipro_m2x2_ck = { | |
973 | .name = "dpll_unipro_m2x2_ck", | |
032b5a7e | 974 | .parent = &dpll_unipro_x2_ck, |
972c5427 RN |
975 | .clksel = dpll_unipro_m2x2_div, |
976 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, | |
977 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
978 | .ops = &clkops_null, | |
979 | .recalc = &omap2_clksel_recalc, | |
980 | .round_rate = &omap2_clksel_round_rate, | |
981 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
982 | }; |
983 | ||
984 | static struct clk usb_hs_clk_div_ck = { | |
985 | .name = "usb_hs_clk_div_ck", | |
032b5a7e | 986 | .parent = &dpll_abe_m3x2_ck, |
972c5427 RN |
987 | .ops = &clkops_null, |
988 | .recalc = &followparent_recalc, | |
972c5427 RN |
989 | }; |
990 | ||
991 | /* DPLL_USB */ | |
992 | static struct dpll_data dpll_usb_dd = { | |
993 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, | |
994 | .clk_bypass = &usb_hs_clk_div_ck, | |
0e433271 | 995 | .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL, |
76cf5295 | 996 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
997 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, |
998 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
999 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, | |
1000 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, | |
1001 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
1002 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
1003 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
1004 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
1005 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
1006 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | |
1007 | .max_divider = OMAP4430_MAX_DPLL_DIV, | |
1008 | .min_divider = 1, | |
1009 | }; | |
1010 | ||
1011 | ||
1012 | static struct clk dpll_usb_ck = { | |
1013 | .name = "dpll_usb_ck", | |
76cf5295 | 1014 | .parent = &sys_clkin_ck, |
972c5427 | 1015 | .dpll_data = &dpll_usb_dd, |
911bd739 | 1016 | .init = &omap2_init_dpll_parent, |
657ebfad | 1017 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
1018 | .recalc = &omap3_dpll_recalc, |
1019 | .round_rate = &omap2_dpll_round_rate, | |
1020 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
1021 | }; |
1022 | ||
1023 | static struct clk dpll_usb_clkdcoldo_ck = { | |
1024 | .name = "dpll_usb_clkdcoldo_ck", | |
1025 | .parent = &dpll_usb_ck, | |
1026 | .ops = &clkops_null, | |
1027 | .recalc = &followparent_recalc, | |
972c5427 RN |
1028 | }; |
1029 | ||
1030 | static const struct clksel dpll_usb_m2_div[] = { | |
1031 | { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, | |
1032 | { .parent = NULL }, | |
1033 | }; | |
1034 | ||
1035 | static struct clk dpll_usb_m2_ck = { | |
1036 | .name = "dpll_usb_m2_ck", | |
1037 | .parent = &dpll_usb_ck, | |
1038 | .clksel = dpll_usb_m2_div, | |
1039 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, | |
1040 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, | |
1041 | .ops = &clkops_null, | |
1042 | .recalc = &omap2_clksel_recalc, | |
1043 | .round_rate = &omap2_clksel_round_rate, | |
1044 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1045 | }; |
1046 | ||
1047 | static const struct clksel ducati_clk_mux_sel[] = { | |
1048 | { .parent = &div_core_ck, .rates = div_1_0_rates }, | |
032b5a7e | 1049 | { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates }, |
972c5427 RN |
1050 | { .parent = NULL }, |
1051 | }; | |
1052 | ||
1053 | static struct clk ducati_clk_mux_ck = { | |
1054 | .name = "ducati_clk_mux_ck", | |
1055 | .parent = &div_core_ck, | |
1056 | .clksel = ducati_clk_mux_sel, | |
1057 | .init = &omap2_init_clksel_parent, | |
1058 | .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, | |
1059 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
1060 | .ops = &clkops_null, | |
1061 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1062 | }; |
1063 | ||
1064 | static struct clk func_12m_fclk = { | |
1065 | .name = "func_12m_fclk", | |
1066 | .parent = &dpll_per_m2x2_ck, | |
1067 | .ops = &clkops_null, | |
1068 | .recalc = &followparent_recalc, | |
972c5427 RN |
1069 | }; |
1070 | ||
1071 | static struct clk func_24m_clk = { | |
1072 | .name = "func_24m_clk", | |
1073 | .parent = &dpll_per_m2_ck, | |
1074 | .ops = &clkops_null, | |
1075 | .recalc = &followparent_recalc, | |
972c5427 RN |
1076 | }; |
1077 | ||
1078 | static struct clk func_24mc_fclk = { | |
1079 | .name = "func_24mc_fclk", | |
1080 | .parent = &dpll_per_m2x2_ck, | |
1081 | .ops = &clkops_null, | |
1082 | .recalc = &followparent_recalc, | |
972c5427 RN |
1083 | }; |
1084 | ||
1085 | static const struct clksel_rate div2_4to8_rates[] = { | |
1086 | { .div = 4, .val = 0, .flags = RATE_IN_4430 }, | |
1087 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, | |
1088 | { .div = 0 }, | |
1089 | }; | |
1090 | ||
1091 | static const struct clksel func_48m_fclk_div[] = { | |
1092 | { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates }, | |
1093 | { .parent = NULL }, | |
1094 | }; | |
1095 | ||
1096 | static struct clk func_48m_fclk = { | |
1097 | .name = "func_48m_fclk", | |
1098 | .parent = &dpll_per_m2x2_ck, | |
1099 | .clksel = func_48m_fclk_div, | |
1100 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
1101 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
1102 | .ops = &clkops_null, | |
1103 | .recalc = &omap2_clksel_recalc, | |
1104 | .round_rate = &omap2_clksel_round_rate, | |
1105 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1106 | }; |
1107 | ||
1108 | static struct clk func_48mc_fclk = { | |
1109 | .name = "func_48mc_fclk", | |
1110 | .parent = &dpll_per_m2x2_ck, | |
1111 | .ops = &clkops_null, | |
1112 | .recalc = &followparent_recalc, | |
972c5427 RN |
1113 | }; |
1114 | ||
1115 | static const struct clksel_rate div2_2to4_rates[] = { | |
1116 | { .div = 2, .val = 0, .flags = RATE_IN_4430 }, | |
1117 | { .div = 4, .val = 1, .flags = RATE_IN_4430 }, | |
1118 | { .div = 0 }, | |
1119 | }; | |
1120 | ||
1121 | static const struct clksel func_64m_fclk_div[] = { | |
032b5a7e | 1122 | { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates }, |
972c5427 RN |
1123 | { .parent = NULL }, |
1124 | }; | |
1125 | ||
1126 | static struct clk func_64m_fclk = { | |
1127 | .name = "func_64m_fclk", | |
032b5a7e | 1128 | .parent = &dpll_per_m4x2_ck, |
972c5427 RN |
1129 | .clksel = func_64m_fclk_div, |
1130 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
1131 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
1132 | .ops = &clkops_null, | |
1133 | .recalc = &omap2_clksel_recalc, | |
1134 | .round_rate = &omap2_clksel_round_rate, | |
1135 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1136 | }; |
1137 | ||
1138 | static const struct clksel func_96m_fclk_div[] = { | |
1139 | { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates }, | |
1140 | { .parent = NULL }, | |
1141 | }; | |
1142 | ||
1143 | static struct clk func_96m_fclk = { | |
1144 | .name = "func_96m_fclk", | |
1145 | .parent = &dpll_per_m2x2_ck, | |
1146 | .clksel = func_96m_fclk_div, | |
1147 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
1148 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
1149 | .ops = &clkops_null, | |
1150 | .recalc = &omap2_clksel_recalc, | |
1151 | .round_rate = &omap2_clksel_round_rate, | |
1152 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1153 | }; |
1154 | ||
1155 | static const struct clksel hsmmc6_fclk_sel[] = { | |
1156 | { .parent = &func_64m_fclk, .rates = div_1_0_rates }, | |
1157 | { .parent = &func_96m_fclk, .rates = div_1_1_rates }, | |
1158 | { .parent = NULL }, | |
1159 | }; | |
1160 | ||
1161 | static struct clk hsmmc6_fclk = { | |
1162 | .name = "hsmmc6_fclk", | |
1163 | .parent = &func_64m_fclk, | |
1164 | .ops = &clkops_null, | |
1165 | .recalc = &followparent_recalc, | |
972c5427 RN |
1166 | }; |
1167 | ||
1168 | static const struct clksel_rate div2_1to8_rates[] = { | |
1169 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
1170 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, | |
1171 | { .div = 0 }, | |
1172 | }; | |
1173 | ||
1174 | static const struct clksel init_60m_fclk_div[] = { | |
1175 | { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates }, | |
1176 | { .parent = NULL }, | |
1177 | }; | |
1178 | ||
1179 | static struct clk init_60m_fclk = { | |
1180 | .name = "init_60m_fclk", | |
1181 | .parent = &dpll_usb_m2_ck, | |
1182 | .clksel = init_60m_fclk_div, | |
1183 | .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ, | |
1184 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
1185 | .ops = &clkops_null, | |
1186 | .recalc = &omap2_clksel_recalc, | |
1187 | .round_rate = &omap2_clksel_round_rate, | |
1188 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1189 | }; |
1190 | ||
1191 | static const struct clksel l3_div_div[] = { | |
1192 | { .parent = &div_core_ck, .rates = div2_1to2_rates }, | |
1193 | { .parent = NULL }, | |
1194 | }; | |
1195 | ||
1196 | static struct clk l3_div_ck = { | |
1197 | .name = "l3_div_ck", | |
1198 | .parent = &div_core_ck, | |
1199 | .clksel = l3_div_div, | |
1200 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | |
1201 | .clksel_mask = OMAP4430_CLKSEL_L3_MASK, | |
1202 | .ops = &clkops_null, | |
1203 | .recalc = &omap2_clksel_recalc, | |
1204 | .round_rate = &omap2_clksel_round_rate, | |
1205 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1206 | }; |
1207 | ||
1208 | static const struct clksel l4_div_div[] = { | |
1209 | { .parent = &l3_div_ck, .rates = div2_1to2_rates }, | |
1210 | { .parent = NULL }, | |
1211 | }; | |
1212 | ||
1213 | static struct clk l4_div_ck = { | |
1214 | .name = "l4_div_ck", | |
1215 | .parent = &l3_div_ck, | |
1216 | .clksel = l4_div_div, | |
1217 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | |
1218 | .clksel_mask = OMAP4430_CLKSEL_L4_MASK, | |
1219 | .ops = &clkops_null, | |
1220 | .recalc = &omap2_clksel_recalc, | |
1221 | .round_rate = &omap2_clksel_round_rate, | |
1222 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1223 | }; |
1224 | ||
1225 | static struct clk lp_clk_div_ck = { | |
1226 | .name = "lp_clk_div_ck", | |
1227 | .parent = &dpll_abe_m2x2_ck, | |
1228 | .ops = &clkops_null, | |
1229 | .recalc = &followparent_recalc, | |
972c5427 RN |
1230 | }; |
1231 | ||
1232 | static const struct clksel l4_wkup_clk_mux_sel[] = { | |
1233 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
1234 | { .parent = &lp_clk_div_ck, .rates = div_1_1_rates }, | |
1235 | { .parent = NULL }, | |
1236 | }; | |
1237 | ||
1238 | static struct clk l4_wkup_clk_mux_ck = { | |
1239 | .name = "l4_wkup_clk_mux_ck", | |
1240 | .parent = &sys_clkin_ck, | |
1241 | .clksel = l4_wkup_clk_mux_sel, | |
1242 | .init = &omap2_init_clksel_parent, | |
1243 | .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL, | |
1244 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
1245 | .ops = &clkops_null, | |
1246 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1247 | }; |
1248 | ||
1249 | static const struct clksel per_abe_nc_fclk_div[] = { | |
1250 | { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, | |
1251 | { .parent = NULL }, | |
1252 | }; | |
1253 | ||
1254 | static struct clk per_abe_nc_fclk = { | |
1255 | .name = "per_abe_nc_fclk", | |
1256 | .parent = &dpll_abe_m2_ck, | |
1257 | .clksel = per_abe_nc_fclk_div, | |
1258 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
1259 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
1260 | .ops = &clkops_null, | |
1261 | .recalc = &omap2_clksel_recalc, | |
1262 | .round_rate = &omap2_clksel_round_rate, | |
1263 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1264 | }; |
1265 | ||
1266 | static const struct clksel mcasp2_fclk_sel[] = { | |
1267 | { .parent = &func_96m_fclk, .rates = div_1_0_rates }, | |
1268 | { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, | |
1269 | { .parent = NULL }, | |
1270 | }; | |
1271 | ||
1272 | static struct clk mcasp2_fclk = { | |
1273 | .name = "mcasp2_fclk", | |
1274 | .parent = &func_96m_fclk, | |
1275 | .ops = &clkops_null, | |
1276 | .recalc = &followparent_recalc, | |
972c5427 RN |
1277 | }; |
1278 | ||
1279 | static struct clk mcasp3_fclk = { | |
1280 | .name = "mcasp3_fclk", | |
1281 | .parent = &func_96m_fclk, | |
1282 | .ops = &clkops_null, | |
1283 | .recalc = &followparent_recalc, | |
972c5427 RN |
1284 | }; |
1285 | ||
1286 | static struct clk ocp_abe_iclk = { | |
1287 | .name = "ocp_abe_iclk", | |
1288 | .parent = &aess_fclk, | |
1289 | .ops = &clkops_null, | |
1290 | .recalc = &followparent_recalc, | |
972c5427 RN |
1291 | }; |
1292 | ||
1293 | static struct clk per_abe_24m_fclk = { | |
1294 | .name = "per_abe_24m_fclk", | |
1295 | .parent = &dpll_abe_m2_ck, | |
1296 | .ops = &clkops_null, | |
1297 | .recalc = &followparent_recalc, | |
972c5427 RN |
1298 | }; |
1299 | ||
1300 | static const struct clksel pmd_stm_clock_mux_sel[] = { | |
1301 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
032b5a7e | 1302 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
76cf5295 | 1303 | { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, |
972c5427 RN |
1304 | { .parent = NULL }, |
1305 | }; | |
1306 | ||
1307 | static struct clk pmd_stm_clock_mux_ck = { | |
1308 | .name = "pmd_stm_clock_mux_ck", | |
1309 | .parent = &sys_clkin_ck, | |
1310 | .ops = &clkops_null, | |
1311 | .recalc = &followparent_recalc, | |
972c5427 RN |
1312 | }; |
1313 | ||
1314 | static struct clk pmd_trace_clk_mux_ck = { | |
1315 | .name = "pmd_trace_clk_mux_ck", | |
1316 | .parent = &sys_clkin_ck, | |
1317 | .ops = &clkops_null, | |
1318 | .recalc = &followparent_recalc, | |
972c5427 RN |
1319 | }; |
1320 | ||
76cf5295 RN |
1321 | static const struct clksel syc_clk_div_div[] = { |
1322 | { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, | |
1323 | { .parent = NULL }, | |
1324 | }; | |
1325 | ||
972c5427 RN |
1326 | static struct clk syc_clk_div_ck = { |
1327 | .name = "syc_clk_div_ck", | |
1328 | .parent = &sys_clkin_ck, | |
76cf5295 | 1329 | .clksel = syc_clk_div_div, |
972c5427 RN |
1330 | .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, |
1331 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
1332 | .ops = &clkops_null, | |
1333 | .recalc = &omap2_clksel_recalc, | |
1334 | .round_rate = &omap2_clksel_round_rate, | |
1335 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1336 | }; |
1337 | ||
1338 | /* Leaf clocks controlled by modules */ | |
1339 | ||
54776050 RN |
1340 | static struct clk aes1_fck = { |
1341 | .name = "aes1_fck", | |
972c5427 RN |
1342 | .ops = &clkops_omap2_dflt, |
1343 | .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, | |
1344 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1345 | .clkdm_name = "l4_secure_clkdm", | |
1346 | .parent = &l3_div_ck, | |
1347 | .recalc = &followparent_recalc, | |
1348 | }; | |
1349 | ||
54776050 RN |
1350 | static struct clk aes2_fck = { |
1351 | .name = "aes2_fck", | |
972c5427 RN |
1352 | .ops = &clkops_omap2_dflt, |
1353 | .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, | |
1354 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1355 | .clkdm_name = "l4_secure_clkdm", | |
1356 | .parent = &l3_div_ck, | |
1357 | .recalc = &followparent_recalc, | |
1358 | }; | |
1359 | ||
54776050 RN |
1360 | static struct clk aess_fck = { |
1361 | .name = "aess_fck", | |
972c5427 RN |
1362 | .ops = &clkops_omap2_dflt, |
1363 | .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | |
1364 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1365 | .clkdm_name = "abe_clkdm", | |
1366 | .parent = &aess_fclk, | |
1367 | .recalc = &followparent_recalc, | |
1368 | }; | |
1369 | ||
1c03f42f BC |
1370 | static struct clk bandgap_fclk = { |
1371 | .name = "bandgap_fclk", | |
1372 | .ops = &clkops_omap2_dflt, | |
1373 | .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | |
1374 | .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, | |
1375 | .clkdm_name = "l4_wkup_clkdm", | |
1376 | .parent = &sys_32k_ck, | |
1377 | .recalc = &followparent_recalc, | |
1378 | }; | |
1379 | ||
54776050 RN |
1380 | static struct clk des3des_fck = { |
1381 | .name = "des3des_fck", | |
972c5427 RN |
1382 | .ops = &clkops_omap2_dflt, |
1383 | .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, | |
1384 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1385 | .clkdm_name = "l4_secure_clkdm", | |
1386 | .parent = &l4_div_ck, | |
1387 | .recalc = &followparent_recalc, | |
1388 | }; | |
1389 | ||
1390 | static const struct clksel dmic_sync_mux_sel[] = { | |
1391 | { .parent = &abe_24m_fclk, .rates = div_1_0_rates }, | |
1392 | { .parent = &syc_clk_div_ck, .rates = div_1_1_rates }, | |
1393 | { .parent = &func_24m_clk, .rates = div_1_2_rates }, | |
1394 | { .parent = NULL }, | |
1395 | }; | |
1396 | ||
1397 | static struct clk dmic_sync_mux_ck = { | |
1398 | .name = "dmic_sync_mux_ck", | |
1399 | .parent = &abe_24m_fclk, | |
1400 | .clksel = dmic_sync_mux_sel, | |
1401 | .init = &omap2_init_clksel_parent, | |
1402 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | |
1403 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1404 | .ops = &clkops_null, | |
1405 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1406 | }; |
1407 | ||
1408 | static const struct clksel func_dmic_abe_gfclk_sel[] = { | |
1409 | { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, | |
1410 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1411 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1412 | { .parent = NULL }, | |
1413 | }; | |
1414 | ||
54776050 RN |
1415 | /* Merged func_dmic_abe_gfclk into dmic */ |
1416 | static struct clk dmic_fck = { | |
1417 | .name = "dmic_fck", | |
972c5427 RN |
1418 | .parent = &dmic_sync_mux_ck, |
1419 | .clksel = func_dmic_abe_gfclk_sel, | |
1420 | .init = &omap2_init_clksel_parent, | |
1421 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | |
1422 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1423 | .ops = &clkops_omap2_dflt, | |
1424 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1425 | .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
1426 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1427 | .clkdm_name = "abe_clkdm", | |
1428 | }; | |
1429 | ||
0e433271 BC |
1430 | static struct clk dsp_fck = { |
1431 | .name = "dsp_fck", | |
1432 | .ops = &clkops_omap2_dflt, | |
1433 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, | |
1434 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1435 | .clkdm_name = "tesla_clkdm", | |
032b5a7e | 1436 | .parent = &dpll_iva_m4x2_ck, |
0e433271 BC |
1437 | .recalc = &followparent_recalc, |
1438 | }; | |
1439 | ||
1c03f42f BC |
1440 | static struct clk dss_sys_clk = { |
1441 | .name = "dss_sys_clk", | |
1442 | .ops = &clkops_omap2_dflt, | |
1443 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1444 | .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, | |
1445 | .clkdm_name = "l3_dss_clkdm", | |
1446 | .parent = &syc_clk_div_ck, | |
1447 | .recalc = &followparent_recalc, | |
1448 | }; | |
1449 | ||
1450 | static struct clk dss_tv_clk = { | |
1451 | .name = "dss_tv_clk", | |
1452 | .ops = &clkops_omap2_dflt, | |
1453 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1454 | .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, | |
1455 | .clkdm_name = "l3_dss_clkdm", | |
1456 | .parent = &extalt_clkin_ck, | |
1457 | .recalc = &followparent_recalc, | |
1458 | }; | |
1459 | ||
1460 | static struct clk dss_dss_clk = { | |
1461 | .name = "dss_dss_clk", | |
1462 | .ops = &clkops_omap2_dflt, | |
1463 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1464 | .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, | |
1465 | .clkdm_name = "l3_dss_clkdm", | |
032b5a7e | 1466 | .parent = &dpll_per_m5x2_ck, |
1c03f42f BC |
1467 | .recalc = &followparent_recalc, |
1468 | }; | |
1469 | ||
1470 | static struct clk dss_48mhz_clk = { | |
1471 | .name = "dss_48mhz_clk", | |
1472 | .ops = &clkops_omap2_dflt, | |
1473 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1474 | .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, | |
1475 | .clkdm_name = "l3_dss_clkdm", | |
1476 | .parent = &func_48mc_fclk, | |
1477 | .recalc = &followparent_recalc, | |
1478 | }; | |
1479 | ||
54776050 RN |
1480 | static struct clk dss_fck = { |
1481 | .name = "dss_fck", | |
972c5427 RN |
1482 | .ops = &clkops_omap2_dflt, |
1483 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1484 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1485 | .clkdm_name = "l3_dss_clkdm", | |
1486 | .parent = &l3_div_ck, | |
1487 | .recalc = &followparent_recalc, | |
1488 | }; | |
1489 | ||
0e433271 BC |
1490 | static struct clk efuse_ctrl_cust_fck = { |
1491 | .name = "efuse_ctrl_cust_fck", | |
972c5427 | 1492 | .ops = &clkops_omap2_dflt, |
0e433271 BC |
1493 | .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, |
1494 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1495 | .clkdm_name = "l4_cefuse_clkdm", | |
1496 | .parent = &sys_clkin_ck, | |
972c5427 RN |
1497 | .recalc = &followparent_recalc, |
1498 | }; | |
1499 | ||
0e433271 BC |
1500 | static struct clk emif1_fck = { |
1501 | .name = "emif1_fck", | |
972c5427 RN |
1502 | .ops = &clkops_omap2_dflt, |
1503 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, | |
1504 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
090830b4 | 1505 | .flags = ENABLE_ON_INIT, |
972c5427 RN |
1506 | .clkdm_name = "l3_emif_clkdm", |
1507 | .parent = &ddrphy_ck, | |
1508 | .recalc = &followparent_recalc, | |
1509 | }; | |
1510 | ||
0e433271 BC |
1511 | static struct clk emif2_fck = { |
1512 | .name = "emif2_fck", | |
972c5427 RN |
1513 | .ops = &clkops_omap2_dflt, |
1514 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, | |
1515 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
090830b4 | 1516 | .flags = ENABLE_ON_INIT, |
972c5427 RN |
1517 | .clkdm_name = "l3_emif_clkdm", |
1518 | .parent = &ddrphy_ck, | |
1519 | .recalc = &followparent_recalc, | |
1520 | }; | |
1521 | ||
1522 | static const struct clksel fdif_fclk_div[] = { | |
032b5a7e | 1523 | { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates }, |
972c5427 RN |
1524 | { .parent = NULL }, |
1525 | }; | |
1526 | ||
54776050 RN |
1527 | /* Merged fdif_fclk into fdif */ |
1528 | static struct clk fdif_fck = { | |
1529 | .name = "fdif_fck", | |
032b5a7e | 1530 | .parent = &dpll_per_m4x2_ck, |
972c5427 RN |
1531 | .clksel = fdif_fclk_div, |
1532 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, | |
1533 | .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, | |
1534 | .ops = &clkops_omap2_dflt, | |
1535 | .recalc = &omap2_clksel_recalc, | |
1536 | .round_rate = &omap2_clksel_round_rate, | |
1537 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1538 | .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
1539 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1540 | .clkdm_name = "iss_clkdm", | |
1541 | }; | |
1542 | ||
0e433271 BC |
1543 | static struct clk fpka_fck = { |
1544 | .name = "fpka_fck", | |
972c5427 | 1545 | .ops = &clkops_omap2_dflt, |
0e433271 | 1546 | .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, |
972c5427 | 1547 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
0e433271 BC |
1548 | .clkdm_name = "l4_secure_clkdm", |
1549 | .parent = &l4_div_ck, | |
1550 | .recalc = &followparent_recalc, | |
972c5427 RN |
1551 | }; |
1552 | ||
1c03f42f BC |
1553 | static struct clk gpio1_dbclk = { |
1554 | .name = "gpio1_dbclk", | |
1555 | .ops = &clkops_omap2_dflt, | |
1556 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | |
1557 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1558 | .clkdm_name = "l4_wkup_clkdm", | |
1559 | .parent = &sys_32k_ck, | |
1560 | .recalc = &followparent_recalc, | |
1561 | }; | |
1562 | ||
54776050 RN |
1563 | static struct clk gpio1_ick = { |
1564 | .name = "gpio1_ick", | |
972c5427 RN |
1565 | .ops = &clkops_omap2_dflt, |
1566 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | |
1567 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1568 | .clkdm_name = "l4_wkup_clkdm", | |
1569 | .parent = &l4_wkup_clk_mux_ck, | |
1570 | .recalc = &followparent_recalc, | |
1571 | }; | |
1572 | ||
1c03f42f BC |
1573 | static struct clk gpio2_dbclk = { |
1574 | .name = "gpio2_dbclk", | |
1575 | .ops = &clkops_omap2_dflt, | |
1576 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | |
1577 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1578 | .clkdm_name = "l4_per_clkdm", | |
1579 | .parent = &sys_32k_ck, | |
1580 | .recalc = &followparent_recalc, | |
1581 | }; | |
1582 | ||
54776050 RN |
1583 | static struct clk gpio2_ick = { |
1584 | .name = "gpio2_ick", | |
972c5427 RN |
1585 | .ops = &clkops_omap2_dflt, |
1586 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | |
1587 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1588 | .clkdm_name = "l4_per_clkdm", | |
1589 | .parent = &l4_div_ck, | |
1590 | .recalc = &followparent_recalc, | |
1591 | }; | |
1592 | ||
1c03f42f BC |
1593 | static struct clk gpio3_dbclk = { |
1594 | .name = "gpio3_dbclk", | |
1595 | .ops = &clkops_omap2_dflt, | |
1596 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | |
1597 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1598 | .clkdm_name = "l4_per_clkdm", | |
1599 | .parent = &sys_32k_ck, | |
1600 | .recalc = &followparent_recalc, | |
1601 | }; | |
1602 | ||
54776050 RN |
1603 | static struct clk gpio3_ick = { |
1604 | .name = "gpio3_ick", | |
972c5427 RN |
1605 | .ops = &clkops_omap2_dflt, |
1606 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | |
1607 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1608 | .clkdm_name = "l4_per_clkdm", | |
1609 | .parent = &l4_div_ck, | |
1610 | .recalc = &followparent_recalc, | |
1611 | }; | |
1612 | ||
1c03f42f BC |
1613 | static struct clk gpio4_dbclk = { |
1614 | .name = "gpio4_dbclk", | |
1615 | .ops = &clkops_omap2_dflt, | |
1616 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | |
1617 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1618 | .clkdm_name = "l4_per_clkdm", | |
1619 | .parent = &sys_32k_ck, | |
1620 | .recalc = &followparent_recalc, | |
1621 | }; | |
1622 | ||
54776050 RN |
1623 | static struct clk gpio4_ick = { |
1624 | .name = "gpio4_ick", | |
972c5427 RN |
1625 | .ops = &clkops_omap2_dflt, |
1626 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | |
1627 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1628 | .clkdm_name = "l4_per_clkdm", | |
1629 | .parent = &l4_div_ck, | |
1630 | .recalc = &followparent_recalc, | |
1631 | }; | |
1632 | ||
1c03f42f BC |
1633 | static struct clk gpio5_dbclk = { |
1634 | .name = "gpio5_dbclk", | |
1635 | .ops = &clkops_omap2_dflt, | |
1636 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | |
1637 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1638 | .clkdm_name = "l4_per_clkdm", | |
1639 | .parent = &sys_32k_ck, | |
1640 | .recalc = &followparent_recalc, | |
1641 | }; | |
1642 | ||
54776050 RN |
1643 | static struct clk gpio5_ick = { |
1644 | .name = "gpio5_ick", | |
972c5427 RN |
1645 | .ops = &clkops_omap2_dflt, |
1646 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | |
1647 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1648 | .clkdm_name = "l4_per_clkdm", | |
1649 | .parent = &l4_div_ck, | |
1650 | .recalc = &followparent_recalc, | |
1651 | }; | |
1652 | ||
1c03f42f BC |
1653 | static struct clk gpio6_dbclk = { |
1654 | .name = "gpio6_dbclk", | |
1655 | .ops = &clkops_omap2_dflt, | |
1656 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | |
1657 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1658 | .clkdm_name = "l4_per_clkdm", | |
1659 | .parent = &sys_32k_ck, | |
1660 | .recalc = &followparent_recalc, | |
1661 | }; | |
1662 | ||
54776050 RN |
1663 | static struct clk gpio6_ick = { |
1664 | .name = "gpio6_ick", | |
972c5427 RN |
1665 | .ops = &clkops_omap2_dflt, |
1666 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | |
1667 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1668 | .clkdm_name = "l4_per_clkdm", | |
1669 | .parent = &l4_div_ck, | |
1670 | .recalc = &followparent_recalc, | |
1671 | }; | |
1672 | ||
54776050 RN |
1673 | static struct clk gpmc_ick = { |
1674 | .name = "gpmc_ick", | |
972c5427 RN |
1675 | .ops = &clkops_omap2_dflt, |
1676 | .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, | |
1677 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1678 | .clkdm_name = "l3_2_clkdm", | |
1679 | .parent = &l3_div_ck, | |
1680 | .recalc = &followparent_recalc, | |
1681 | }; | |
1682 | ||
0e433271 | 1683 | static const struct clksel sgx_clk_mux_sel[] = { |
032b5a7e TG |
1684 | { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, |
1685 | { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, | |
972c5427 RN |
1686 | { .parent = NULL }, |
1687 | }; | |
1688 | ||
0e433271 BC |
1689 | /* Merged sgx_clk_mux into gpu */ |
1690 | static struct clk gpu_fck = { | |
1691 | .name = "gpu_fck", | |
032b5a7e | 1692 | .parent = &dpll_core_m7x2_ck, |
0e433271 | 1693 | .clksel = sgx_clk_mux_sel, |
972c5427 | 1694 | .init = &omap2_init_clksel_parent, |
0e433271 BC |
1695 | .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
1696 | .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, | |
972c5427 RN |
1697 | .ops = &clkops_omap2_dflt, |
1698 | .recalc = &omap2_clksel_recalc, | |
0e433271 | 1699 | .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
972c5427 | 1700 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
0e433271 | 1701 | .clkdm_name = "l3_gfx_clkdm", |
972c5427 RN |
1702 | }; |
1703 | ||
54776050 RN |
1704 | static struct clk hdq1w_fck = { |
1705 | .name = "hdq1w_fck", | |
972c5427 RN |
1706 | .ops = &clkops_omap2_dflt, |
1707 | .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, | |
1708 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1709 | .clkdm_name = "l4_per_clkdm", | |
1710 | .parent = &func_12m_fclk, | |
1711 | .recalc = &followparent_recalc, | |
1712 | }; | |
1713 | ||
76cf5295 RN |
1714 | static const struct clksel hsi_fclk_div[] = { |
1715 | { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, | |
1716 | { .parent = NULL }, | |
1717 | }; | |
1718 | ||
54776050 | 1719 | /* Merged hsi_fclk into hsi */ |
0e433271 BC |
1720 | static struct clk hsi_fck = { |
1721 | .name = "hsi_fck", | |
972c5427 | 1722 | .parent = &dpll_per_m2x2_ck, |
76cf5295 | 1723 | .clksel = hsi_fclk_div, |
972c5427 RN |
1724 | .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
1725 | .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, | |
1726 | .ops = &clkops_omap2_dflt, | |
1727 | .recalc = &omap2_clksel_recalc, | |
1728 | .round_rate = &omap2_clksel_round_rate, | |
1729 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1730 | .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
1731 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1732 | .clkdm_name = "l3_init_clkdm", | |
1733 | }; | |
1734 | ||
54776050 RN |
1735 | static struct clk i2c1_fck = { |
1736 | .name = "i2c1_fck", | |
972c5427 RN |
1737 | .ops = &clkops_omap2_dflt, |
1738 | .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, | |
1739 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1740 | .clkdm_name = "l4_per_clkdm", | |
1741 | .parent = &func_96m_fclk, | |
1742 | .recalc = &followparent_recalc, | |
1743 | }; | |
1744 | ||
54776050 RN |
1745 | static struct clk i2c2_fck = { |
1746 | .name = "i2c2_fck", | |
972c5427 RN |
1747 | .ops = &clkops_omap2_dflt, |
1748 | .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, | |
1749 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1750 | .clkdm_name = "l4_per_clkdm", | |
1751 | .parent = &func_96m_fclk, | |
1752 | .recalc = &followparent_recalc, | |
1753 | }; | |
1754 | ||
54776050 RN |
1755 | static struct clk i2c3_fck = { |
1756 | .name = "i2c3_fck", | |
972c5427 RN |
1757 | .ops = &clkops_omap2_dflt, |
1758 | .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, | |
1759 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1760 | .clkdm_name = "l4_per_clkdm", | |
1761 | .parent = &func_96m_fclk, | |
1762 | .recalc = &followparent_recalc, | |
1763 | }; | |
1764 | ||
54776050 RN |
1765 | static struct clk i2c4_fck = { |
1766 | .name = "i2c4_fck", | |
972c5427 RN |
1767 | .ops = &clkops_omap2_dflt, |
1768 | .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, | |
1769 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1770 | .clkdm_name = "l4_per_clkdm", | |
1771 | .parent = &func_96m_fclk, | |
1772 | .recalc = &followparent_recalc, | |
1773 | }; | |
1774 | ||
0e433271 BC |
1775 | static struct clk ipu_fck = { |
1776 | .name = "ipu_fck", | |
1777 | .ops = &clkops_omap2_dflt, | |
1778 | .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, | |
1779 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1780 | .clkdm_name = "ducati_clkdm", | |
1781 | .parent = &ducati_clk_mux_ck, | |
1782 | .recalc = &followparent_recalc, | |
1783 | }; | |
1784 | ||
1c03f42f BC |
1785 | static struct clk iss_ctrlclk = { |
1786 | .name = "iss_ctrlclk", | |
1787 | .ops = &clkops_omap2_dflt, | |
1788 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, | |
1789 | .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, | |
1790 | .clkdm_name = "iss_clkdm", | |
1791 | .parent = &func_96m_fclk, | |
1792 | .recalc = &followparent_recalc, | |
1793 | }; | |
1794 | ||
54776050 RN |
1795 | static struct clk iss_fck = { |
1796 | .name = "iss_fck", | |
972c5427 RN |
1797 | .ops = &clkops_omap2_dflt, |
1798 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, | |
1799 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1800 | .clkdm_name = "iss_clkdm", | |
1801 | .parent = &ducati_clk_mux_ck, | |
1802 | .recalc = &followparent_recalc, | |
1803 | }; | |
1804 | ||
0e433271 BC |
1805 | static struct clk iva_fck = { |
1806 | .name = "iva_fck", | |
972c5427 RN |
1807 | .ops = &clkops_omap2_dflt, |
1808 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, | |
1809 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1810 | .clkdm_name = "ivahd_clkdm", | |
032b5a7e | 1811 | .parent = &dpll_iva_m5x2_ck, |
972c5427 RN |
1812 | .recalc = &followparent_recalc, |
1813 | }; | |
1814 | ||
0e433271 BC |
1815 | static struct clk kbd_fck = { |
1816 | .name = "kbd_fck", | |
972c5427 RN |
1817 | .ops = &clkops_omap2_dflt, |
1818 | .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, | |
1819 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1820 | .clkdm_name = "l4_wkup_clkdm", | |
1821 | .parent = &sys_32k_ck, | |
1822 | .recalc = &followparent_recalc, | |
1823 | }; | |
1824 | ||
0e433271 BC |
1825 | static struct clk l3_instr_ick = { |
1826 | .name = "l3_instr_ick", | |
972c5427 RN |
1827 | .ops = &clkops_omap2_dflt, |
1828 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, | |
1829 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1830 | .clkdm_name = "l3_instr_clkdm", | |
1831 | .parent = &l3_div_ck, | |
1832 | .recalc = &followparent_recalc, | |
1833 | }; | |
1834 | ||
0e433271 BC |
1835 | static struct clk l3_main_3_ick = { |
1836 | .name = "l3_main_3_ick", | |
972c5427 RN |
1837 | .ops = &clkops_omap2_dflt, |
1838 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, | |
1839 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1840 | .clkdm_name = "l3_instr_clkdm", | |
1841 | .parent = &l3_div_ck, | |
1842 | .recalc = &followparent_recalc, | |
1843 | }; | |
1844 | ||
1845 | static struct clk mcasp_sync_mux_ck = { | |
1846 | .name = "mcasp_sync_mux_ck", | |
1847 | .parent = &abe_24m_fclk, | |
1848 | .clksel = dmic_sync_mux_sel, | |
1849 | .init = &omap2_init_clksel_parent, | |
1850 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, | |
1851 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1852 | .ops = &clkops_null, | |
1853 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1854 | }; |
1855 | ||
1856 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { | |
1857 | { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, | |
1858 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1859 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1860 | { .parent = NULL }, | |
1861 | }; | |
1862 | ||
54776050 RN |
1863 | /* Merged func_mcasp_abe_gfclk into mcasp */ |
1864 | static struct clk mcasp_fck = { | |
1865 | .name = "mcasp_fck", | |
972c5427 RN |
1866 | .parent = &mcasp_sync_mux_ck, |
1867 | .clksel = func_mcasp_abe_gfclk_sel, | |
1868 | .init = &omap2_init_clksel_parent, | |
1869 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, | |
1870 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1871 | .ops = &clkops_omap2_dflt, | |
1872 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1873 | .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, |
1874 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1875 | .clkdm_name = "abe_clkdm", | |
1876 | }; | |
1877 | ||
1878 | static struct clk mcbsp1_sync_mux_ck = { | |
1879 | .name = "mcbsp1_sync_mux_ck", | |
1880 | .parent = &abe_24m_fclk, | |
1881 | .clksel = dmic_sync_mux_sel, | |
1882 | .init = &omap2_init_clksel_parent, | |
1883 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | |
1884 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1885 | .ops = &clkops_null, | |
1886 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1887 | }; |
1888 | ||
1889 | static const struct clksel func_mcbsp1_gfclk_sel[] = { | |
1890 | { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, | |
1891 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1892 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1893 | { .parent = NULL }, | |
1894 | }; | |
1895 | ||
54776050 RN |
1896 | /* Merged func_mcbsp1_gfclk into mcbsp1 */ |
1897 | static struct clk mcbsp1_fck = { | |
1898 | .name = "mcbsp1_fck", | |
972c5427 RN |
1899 | .parent = &mcbsp1_sync_mux_ck, |
1900 | .clksel = func_mcbsp1_gfclk_sel, | |
1901 | .init = &omap2_init_clksel_parent, | |
1902 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | |
1903 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1904 | .ops = &clkops_omap2_dflt, | |
1905 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1906 | .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, |
1907 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1908 | .clkdm_name = "abe_clkdm", | |
1909 | }; | |
1910 | ||
1911 | static struct clk mcbsp2_sync_mux_ck = { | |
1912 | .name = "mcbsp2_sync_mux_ck", | |
1913 | .parent = &abe_24m_fclk, | |
1914 | .clksel = dmic_sync_mux_sel, | |
1915 | .init = &omap2_init_clksel_parent, | |
1916 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | |
1917 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1918 | .ops = &clkops_null, | |
1919 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1920 | }; |
1921 | ||
1922 | static const struct clksel func_mcbsp2_gfclk_sel[] = { | |
1923 | { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, | |
1924 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1925 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1926 | { .parent = NULL }, | |
1927 | }; | |
1928 | ||
54776050 RN |
1929 | /* Merged func_mcbsp2_gfclk into mcbsp2 */ |
1930 | static struct clk mcbsp2_fck = { | |
1931 | .name = "mcbsp2_fck", | |
972c5427 RN |
1932 | .parent = &mcbsp2_sync_mux_ck, |
1933 | .clksel = func_mcbsp2_gfclk_sel, | |
1934 | .init = &omap2_init_clksel_parent, | |
1935 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | |
1936 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1937 | .ops = &clkops_omap2_dflt, | |
1938 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1939 | .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, |
1940 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1941 | .clkdm_name = "abe_clkdm", | |
1942 | }; | |
1943 | ||
1944 | static struct clk mcbsp3_sync_mux_ck = { | |
1945 | .name = "mcbsp3_sync_mux_ck", | |
1946 | .parent = &abe_24m_fclk, | |
1947 | .clksel = dmic_sync_mux_sel, | |
1948 | .init = &omap2_init_clksel_parent, | |
1949 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | |
1950 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1951 | .ops = &clkops_null, | |
1952 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1953 | }; |
1954 | ||
1955 | static const struct clksel func_mcbsp3_gfclk_sel[] = { | |
1956 | { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, | |
1957 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1958 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1959 | { .parent = NULL }, | |
1960 | }; | |
1961 | ||
54776050 RN |
1962 | /* Merged func_mcbsp3_gfclk into mcbsp3 */ |
1963 | static struct clk mcbsp3_fck = { | |
1964 | .name = "mcbsp3_fck", | |
972c5427 RN |
1965 | .parent = &mcbsp3_sync_mux_ck, |
1966 | .clksel = func_mcbsp3_gfclk_sel, | |
1967 | .init = &omap2_init_clksel_parent, | |
1968 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | |
1969 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1970 | .ops = &clkops_omap2_dflt, | |
1971 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1972 | .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, |
1973 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1974 | .clkdm_name = "abe_clkdm", | |
1975 | }; | |
1976 | ||
1977 | static struct clk mcbsp4_sync_mux_ck = { | |
1978 | .name = "mcbsp4_sync_mux_ck", | |
1979 | .parent = &func_96m_fclk, | |
1980 | .clksel = mcasp2_fclk_sel, | |
1981 | .init = &omap2_init_clksel_parent, | |
1982 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | |
1983 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1984 | .ops = &clkops_null, | |
1985 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1986 | }; |
1987 | ||
1988 | static const struct clksel per_mcbsp4_gfclk_sel[] = { | |
1989 | { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, | |
1990 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1991 | { .parent = NULL }, | |
1992 | }; | |
1993 | ||
54776050 RN |
1994 | /* Merged per_mcbsp4_gfclk into mcbsp4 */ |
1995 | static struct clk mcbsp4_fck = { | |
1996 | .name = "mcbsp4_fck", | |
972c5427 RN |
1997 | .parent = &mcbsp4_sync_mux_ck, |
1998 | .clksel = per_mcbsp4_gfclk_sel, | |
1999 | .init = &omap2_init_clksel_parent, | |
2000 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | |
2001 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, | |
2002 | .ops = &clkops_omap2_dflt, | |
2003 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
2004 | .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, |
2005 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2006 | .clkdm_name = "l4_per_clkdm", | |
2007 | }; | |
2008 | ||
0e433271 BC |
2009 | static struct clk mcpdm_fck = { |
2010 | .name = "mcpdm_fck", | |
2011 | .ops = &clkops_omap2_dflt, | |
2012 | .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, | |
2013 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2014 | .clkdm_name = "abe_clkdm", | |
2015 | .parent = &pad_clks_ck, | |
2016 | .recalc = &followparent_recalc, | |
2017 | }; | |
2018 | ||
54776050 RN |
2019 | static struct clk mcspi1_fck = { |
2020 | .name = "mcspi1_fck", | |
972c5427 RN |
2021 | .ops = &clkops_omap2_dflt, |
2022 | .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, | |
2023 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2024 | .clkdm_name = "l4_per_clkdm", | |
2025 | .parent = &func_48m_fclk, | |
2026 | .recalc = &followparent_recalc, | |
2027 | }; | |
2028 | ||
54776050 RN |
2029 | static struct clk mcspi2_fck = { |
2030 | .name = "mcspi2_fck", | |
972c5427 RN |
2031 | .ops = &clkops_omap2_dflt, |
2032 | .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, | |
2033 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2034 | .clkdm_name = "l4_per_clkdm", | |
2035 | .parent = &func_48m_fclk, | |
2036 | .recalc = &followparent_recalc, | |
2037 | }; | |
2038 | ||
54776050 RN |
2039 | static struct clk mcspi3_fck = { |
2040 | .name = "mcspi3_fck", | |
972c5427 RN |
2041 | .ops = &clkops_omap2_dflt, |
2042 | .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, | |
2043 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2044 | .clkdm_name = "l4_per_clkdm", | |
2045 | .parent = &func_48m_fclk, | |
2046 | .recalc = &followparent_recalc, | |
2047 | }; | |
2048 | ||
54776050 RN |
2049 | static struct clk mcspi4_fck = { |
2050 | .name = "mcspi4_fck", | |
972c5427 RN |
2051 | .ops = &clkops_omap2_dflt, |
2052 | .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, | |
2053 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2054 | .clkdm_name = "l4_per_clkdm", | |
2055 | .parent = &func_48m_fclk, | |
2056 | .recalc = &followparent_recalc, | |
2057 | }; | |
2058 | ||
54776050 RN |
2059 | /* Merged hsmmc1_fclk into mmc1 */ |
2060 | static struct clk mmc1_fck = { | |
2061 | .name = "mmc1_fck", | |
972c5427 RN |
2062 | .parent = &func_64m_fclk, |
2063 | .clksel = hsmmc6_fclk_sel, | |
2064 | .init = &omap2_init_clksel_parent, | |
2065 | .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, | |
2066 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2067 | .ops = &clkops_omap2_dflt, | |
2068 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
2069 | .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, |
2070 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2071 | .clkdm_name = "l3_init_clkdm", | |
2072 | }; | |
2073 | ||
54776050 RN |
2074 | /* Merged hsmmc2_fclk into mmc2 */ |
2075 | static struct clk mmc2_fck = { | |
2076 | .name = "mmc2_fck", | |
972c5427 RN |
2077 | .parent = &func_64m_fclk, |
2078 | .clksel = hsmmc6_fclk_sel, | |
2079 | .init = &omap2_init_clksel_parent, | |
2080 | .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, | |
2081 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2082 | .ops = &clkops_omap2_dflt, | |
2083 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
2084 | .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, |
2085 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2086 | .clkdm_name = "l3_init_clkdm", | |
2087 | }; | |
2088 | ||
54776050 RN |
2089 | static struct clk mmc3_fck = { |
2090 | .name = "mmc3_fck", | |
972c5427 RN |
2091 | .ops = &clkops_omap2_dflt, |
2092 | .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, | |
2093 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2094 | .clkdm_name = "l4_per_clkdm", | |
2095 | .parent = &func_48m_fclk, | |
2096 | .recalc = &followparent_recalc, | |
2097 | }; | |
2098 | ||
54776050 RN |
2099 | static struct clk mmc4_fck = { |
2100 | .name = "mmc4_fck", | |
972c5427 RN |
2101 | .ops = &clkops_omap2_dflt, |
2102 | .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, | |
2103 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2104 | .clkdm_name = "l4_per_clkdm", | |
2105 | .parent = &func_48m_fclk, | |
2106 | .recalc = &followparent_recalc, | |
2107 | }; | |
2108 | ||
54776050 RN |
2109 | static struct clk mmc5_fck = { |
2110 | .name = "mmc5_fck", | |
972c5427 RN |
2111 | .ops = &clkops_omap2_dflt, |
2112 | .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, | |
2113 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2114 | .clkdm_name = "l4_per_clkdm", | |
2115 | .parent = &func_48m_fclk, | |
2116 | .recalc = &followparent_recalc, | |
2117 | }; | |
2118 | ||
0edc9e85 BC |
2119 | static struct clk ocp2scp_usb_phy_phy_48m = { |
2120 | .name = "ocp2scp_usb_phy_phy_48m", | |
1c03f42f BC |
2121 | .ops = &clkops_omap2_dflt, |
2122 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | |
0edc9e85 | 2123 | .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, |
1c03f42f | 2124 | .clkdm_name = "l3_init_clkdm", |
0edc9e85 | 2125 | .parent = &func_48m_fclk, |
1c03f42f BC |
2126 | .recalc = &followparent_recalc, |
2127 | }; | |
2128 | ||
0edc9e85 BC |
2129 | static struct clk ocp2scp_usb_phy_ick = { |
2130 | .name = "ocp2scp_usb_phy_ick", | |
1c03f42f BC |
2131 | .ops = &clkops_omap2_dflt, |
2132 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | |
0edc9e85 | 2133 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
1c03f42f | 2134 | .clkdm_name = "l3_init_clkdm", |
0edc9e85 | 2135 | .parent = &l4_div_ck, |
1c03f42f BC |
2136 | .recalc = &followparent_recalc, |
2137 | }; | |
2138 | ||
0e433271 BC |
2139 | static struct clk ocp_wp_noc_ick = { |
2140 | .name = "ocp_wp_noc_ick", | |
972c5427 RN |
2141 | .ops = &clkops_omap2_dflt, |
2142 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, | |
2143 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2144 | .clkdm_name = "l3_instr_clkdm", | |
2145 | .parent = &l3_div_ck, | |
2146 | .recalc = &followparent_recalc, | |
2147 | }; | |
2148 | ||
54776050 RN |
2149 | static struct clk rng_ick = { |
2150 | .name = "rng_ick", | |
972c5427 RN |
2151 | .ops = &clkops_omap2_dflt, |
2152 | .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, | |
2153 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2154 | .clkdm_name = "l4_secure_clkdm", | |
2155 | .parent = &l4_div_ck, | |
2156 | .recalc = &followparent_recalc, | |
2157 | }; | |
2158 | ||
0e433271 BC |
2159 | static struct clk sha2md5_fck = { |
2160 | .name = "sha2md5_fck", | |
972c5427 RN |
2161 | .ops = &clkops_omap2_dflt, |
2162 | .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, | |
2163 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2164 | .clkdm_name = "l4_secure_clkdm", | |
2165 | .parent = &l3_div_ck, | |
2166 | .recalc = &followparent_recalc, | |
2167 | }; | |
2168 | ||
0e433271 BC |
2169 | static struct clk sl2if_ick = { |
2170 | .name = "sl2if_ick", | |
972c5427 RN |
2171 | .ops = &clkops_omap2_dflt, |
2172 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, | |
2173 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2174 | .clkdm_name = "ivahd_clkdm", | |
032b5a7e | 2175 | .parent = &dpll_iva_m5x2_ck, |
972c5427 RN |
2176 | .recalc = &followparent_recalc, |
2177 | }; | |
2178 | ||
1c03f42f BC |
2179 | static struct clk slimbus1_fclk_1 = { |
2180 | .name = "slimbus1_fclk_1", | |
2181 | .ops = &clkops_omap2_dflt, | |
2182 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2183 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, | |
2184 | .clkdm_name = "abe_clkdm", | |
2185 | .parent = &func_24m_clk, | |
2186 | .recalc = &followparent_recalc, | |
2187 | }; | |
2188 | ||
2189 | static struct clk slimbus1_fclk_0 = { | |
2190 | .name = "slimbus1_fclk_0", | |
2191 | .ops = &clkops_omap2_dflt, | |
2192 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2193 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, | |
2194 | .clkdm_name = "abe_clkdm", | |
2195 | .parent = &abe_24m_fclk, | |
2196 | .recalc = &followparent_recalc, | |
2197 | }; | |
2198 | ||
2199 | static struct clk slimbus1_fclk_2 = { | |
2200 | .name = "slimbus1_fclk_2", | |
2201 | .ops = &clkops_omap2_dflt, | |
2202 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2203 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, | |
2204 | .clkdm_name = "abe_clkdm", | |
2205 | .parent = &pad_clks_ck, | |
2206 | .recalc = &followparent_recalc, | |
2207 | }; | |
2208 | ||
2209 | static struct clk slimbus1_slimbus_clk = { | |
2210 | .name = "slimbus1_slimbus_clk", | |
2211 | .ops = &clkops_omap2_dflt, | |
2212 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2213 | .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, | |
2214 | .clkdm_name = "abe_clkdm", | |
2215 | .parent = &slimbus_clk, | |
2216 | .recalc = &followparent_recalc, | |
2217 | }; | |
2218 | ||
54776050 RN |
2219 | static struct clk slimbus1_fck = { |
2220 | .name = "slimbus1_fck", | |
972c5427 RN |
2221 | .ops = &clkops_omap2_dflt, |
2222 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2223 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2224 | .clkdm_name = "abe_clkdm", | |
2225 | .parent = &ocp_abe_iclk, | |
2226 | .recalc = &followparent_recalc, | |
2227 | }; | |
2228 | ||
1c03f42f BC |
2229 | static struct clk slimbus2_fclk_1 = { |
2230 | .name = "slimbus2_fclk_1", | |
2231 | .ops = &clkops_omap2_dflt, | |
2232 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2233 | .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, | |
2234 | .clkdm_name = "l4_per_clkdm", | |
2235 | .parent = &per_abe_24m_fclk, | |
2236 | .recalc = &followparent_recalc, | |
2237 | }; | |
2238 | ||
2239 | static struct clk slimbus2_fclk_0 = { | |
2240 | .name = "slimbus2_fclk_0", | |
2241 | .ops = &clkops_omap2_dflt, | |
2242 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2243 | .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, | |
2244 | .clkdm_name = "l4_per_clkdm", | |
2245 | .parent = &func_24mc_fclk, | |
2246 | .recalc = &followparent_recalc, | |
2247 | }; | |
2248 | ||
2249 | static struct clk slimbus2_slimbus_clk = { | |
2250 | .name = "slimbus2_slimbus_clk", | |
2251 | .ops = &clkops_omap2_dflt, | |
2252 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2253 | .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, | |
2254 | .clkdm_name = "l4_per_clkdm", | |
2255 | .parent = &pad_slimbus_core_clks_ck, | |
2256 | .recalc = &followparent_recalc, | |
2257 | }; | |
2258 | ||
54776050 RN |
2259 | static struct clk slimbus2_fck = { |
2260 | .name = "slimbus2_fck", | |
972c5427 RN |
2261 | .ops = &clkops_omap2_dflt, |
2262 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2263 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2264 | .clkdm_name = "l4_per_clkdm", | |
2265 | .parent = &l4_div_ck, | |
2266 | .recalc = &followparent_recalc, | |
2267 | }; | |
2268 | ||
0e433271 BC |
2269 | static struct clk smartreflex_core_fck = { |
2270 | .name = "smartreflex_core_fck", | |
972c5427 RN |
2271 | .ops = &clkops_omap2_dflt, |
2272 | .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, | |
2273 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2274 | .clkdm_name = "l4_ao_clkdm", | |
2275 | .parent = &l4_wkup_clk_mux_ck, | |
2276 | .recalc = &followparent_recalc, | |
2277 | }; | |
2278 | ||
0e433271 BC |
2279 | static struct clk smartreflex_iva_fck = { |
2280 | .name = "smartreflex_iva_fck", | |
972c5427 RN |
2281 | .ops = &clkops_omap2_dflt, |
2282 | .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, | |
2283 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2284 | .clkdm_name = "l4_ao_clkdm", | |
2285 | .parent = &l4_wkup_clk_mux_ck, | |
2286 | .recalc = &followparent_recalc, | |
2287 | }; | |
2288 | ||
0e433271 BC |
2289 | static struct clk smartreflex_mpu_fck = { |
2290 | .name = "smartreflex_mpu_fck", | |
972c5427 RN |
2291 | .ops = &clkops_omap2_dflt, |
2292 | .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, | |
2293 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2294 | .clkdm_name = "l4_ao_clkdm", | |
2295 | .parent = &l4_wkup_clk_mux_ck, | |
2296 | .recalc = &followparent_recalc, | |
2297 | }; | |
2298 | ||
0e433271 BC |
2299 | /* Merged dmt1_clk_mux into timer1 */ |
2300 | static struct clk timer1_fck = { | |
2301 | .name = "timer1_fck", | |
2302 | .parent = &sys_clkin_ck, | |
2303 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2304 | .init = &omap2_init_clksel_parent, | |
2305 | .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | |
2306 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
972c5427 | 2307 | .ops = &clkops_omap2_dflt, |
0e433271 BC |
2308 | .recalc = &omap2_clksel_recalc, |
2309 | .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | |
2310 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2311 | .clkdm_name = "l4_wkup_clkdm", | |
2312 | }; | |
2313 | ||
2314 | /* Merged cm2_dm10_mux into timer10 */ | |
2315 | static struct clk timer10_fck = { | |
2316 | .name = "timer10_fck", | |
2317 | .parent = &sys_clkin_ck, | |
2318 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2319 | .init = &omap2_init_clksel_parent, | |
2320 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | |
2321 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2322 | .ops = &clkops_omap2_dflt, | |
2323 | .recalc = &omap2_clksel_recalc, | |
2324 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | |
2325 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2326 | .clkdm_name = "l4_per_clkdm", | |
2327 | }; | |
2328 | ||
2329 | /* Merged cm2_dm11_mux into timer11 */ | |
2330 | static struct clk timer11_fck = { | |
2331 | .name = "timer11_fck", | |
2332 | .parent = &sys_clkin_ck, | |
2333 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2334 | .init = &omap2_init_clksel_parent, | |
2335 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | |
2336 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2337 | .ops = &clkops_omap2_dflt, | |
2338 | .recalc = &omap2_clksel_recalc, | |
2339 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | |
2340 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2341 | .clkdm_name = "l4_per_clkdm", | |
2342 | }; | |
2343 | ||
2344 | /* Merged cm2_dm2_mux into timer2 */ | |
2345 | static struct clk timer2_fck = { | |
2346 | .name = "timer2_fck", | |
2347 | .parent = &sys_clkin_ck, | |
2348 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2349 | .init = &omap2_init_clksel_parent, | |
2350 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | |
2351 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2352 | .ops = &clkops_omap2_dflt, | |
2353 | .recalc = &omap2_clksel_recalc, | |
2354 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | |
2355 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2356 | .clkdm_name = "l4_per_clkdm", | |
2357 | }; | |
2358 | ||
2359 | /* Merged cm2_dm3_mux into timer3 */ | |
2360 | static struct clk timer3_fck = { | |
2361 | .name = "timer3_fck", | |
2362 | .parent = &sys_clkin_ck, | |
2363 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2364 | .init = &omap2_init_clksel_parent, | |
2365 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | |
2366 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2367 | .ops = &clkops_omap2_dflt, | |
2368 | .recalc = &omap2_clksel_recalc, | |
2369 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | |
2370 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2371 | .clkdm_name = "l4_per_clkdm", | |
2372 | }; | |
2373 | ||
2374 | /* Merged cm2_dm4_mux into timer4 */ | |
2375 | static struct clk timer4_fck = { | |
2376 | .name = "timer4_fck", | |
2377 | .parent = &sys_clkin_ck, | |
2378 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2379 | .init = &omap2_init_clksel_parent, | |
2380 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | |
2381 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2382 | .ops = &clkops_omap2_dflt, | |
2383 | .recalc = &omap2_clksel_recalc, | |
2384 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | |
2385 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2386 | .clkdm_name = "l4_per_clkdm", | |
2387 | }; | |
2388 | ||
2389 | static const struct clksel timer5_sync_mux_sel[] = { | |
2390 | { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, | |
2391 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | |
2392 | { .parent = NULL }, | |
2393 | }; | |
2394 | ||
2395 | /* Merged timer5_sync_mux into timer5 */ | |
2396 | static struct clk timer5_fck = { | |
2397 | .name = "timer5_fck", | |
2398 | .parent = &syc_clk_div_ck, | |
2399 | .clksel = timer5_sync_mux_sel, | |
2400 | .init = &omap2_init_clksel_parent, | |
2401 | .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | |
2402 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2403 | .ops = &clkops_omap2_dflt, | |
2404 | .recalc = &omap2_clksel_recalc, | |
2405 | .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | |
2406 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2407 | .clkdm_name = "abe_clkdm", | |
2408 | }; | |
2409 | ||
2410 | /* Merged timer6_sync_mux into timer6 */ | |
2411 | static struct clk timer6_fck = { | |
2412 | .name = "timer6_fck", | |
2413 | .parent = &syc_clk_div_ck, | |
2414 | .clksel = timer5_sync_mux_sel, | |
2415 | .init = &omap2_init_clksel_parent, | |
2416 | .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | |
2417 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2418 | .ops = &clkops_omap2_dflt, | |
2419 | .recalc = &omap2_clksel_recalc, | |
2420 | .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | |
2421 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2422 | .clkdm_name = "abe_clkdm", | |
2423 | }; | |
2424 | ||
2425 | /* Merged timer7_sync_mux into timer7 */ | |
2426 | static struct clk timer7_fck = { | |
2427 | .name = "timer7_fck", | |
2428 | .parent = &syc_clk_div_ck, | |
2429 | .clksel = timer5_sync_mux_sel, | |
2430 | .init = &omap2_init_clksel_parent, | |
2431 | .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | |
2432 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2433 | .ops = &clkops_omap2_dflt, | |
2434 | .recalc = &omap2_clksel_recalc, | |
2435 | .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | |
2436 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2437 | .clkdm_name = "abe_clkdm", | |
2438 | }; | |
2439 | ||
2440 | /* Merged timer8_sync_mux into timer8 */ | |
2441 | static struct clk timer8_fck = { | |
2442 | .name = "timer8_fck", | |
2443 | .parent = &syc_clk_div_ck, | |
2444 | .clksel = timer5_sync_mux_sel, | |
2445 | .init = &omap2_init_clksel_parent, | |
2446 | .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | |
2447 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2448 | .ops = &clkops_omap2_dflt, | |
2449 | .recalc = &omap2_clksel_recalc, | |
2450 | .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | |
2451 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2452 | .clkdm_name = "abe_clkdm", | |
2453 | }; | |
2454 | ||
2455 | /* Merged cm2_dm9_mux into timer9 */ | |
2456 | static struct clk timer9_fck = { | |
2457 | .name = "timer9_fck", | |
2458 | .parent = &sys_clkin_ck, | |
2459 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2460 | .init = &omap2_init_clksel_parent, | |
2461 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | |
2462 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2463 | .ops = &clkops_omap2_dflt, | |
2464 | .recalc = &omap2_clksel_recalc, | |
2465 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | |
2466 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2467 | .clkdm_name = "l4_per_clkdm", | |
972c5427 RN |
2468 | }; |
2469 | ||
54776050 RN |
2470 | static struct clk uart1_fck = { |
2471 | .name = "uart1_fck", | |
972c5427 RN |
2472 | .ops = &clkops_omap2_dflt, |
2473 | .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, | |
2474 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2475 | .clkdm_name = "l4_per_clkdm", | |
2476 | .parent = &func_48m_fclk, | |
2477 | .recalc = &followparent_recalc, | |
2478 | }; | |
2479 | ||
54776050 RN |
2480 | static struct clk uart2_fck = { |
2481 | .name = "uart2_fck", | |
972c5427 RN |
2482 | .ops = &clkops_omap2_dflt, |
2483 | .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, | |
2484 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2485 | .clkdm_name = "l4_per_clkdm", | |
2486 | .parent = &func_48m_fclk, | |
2487 | .recalc = &followparent_recalc, | |
2488 | }; | |
2489 | ||
54776050 RN |
2490 | static struct clk uart3_fck = { |
2491 | .name = "uart3_fck", | |
972c5427 RN |
2492 | .ops = &clkops_omap2_dflt, |
2493 | .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, | |
2494 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2495 | .clkdm_name = "l4_per_clkdm", | |
2496 | .parent = &func_48m_fclk, | |
2497 | .recalc = &followparent_recalc, | |
2498 | }; | |
2499 | ||
54776050 RN |
2500 | static struct clk uart4_fck = { |
2501 | .name = "uart4_fck", | |
972c5427 RN |
2502 | .ops = &clkops_omap2_dflt, |
2503 | .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, | |
2504 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2505 | .clkdm_name = "l4_per_clkdm", | |
2506 | .parent = &func_48m_fclk, | |
2507 | .recalc = &followparent_recalc, | |
2508 | }; | |
2509 | ||
0e433271 BC |
2510 | static struct clk usb_host_fs_fck = { |
2511 | .name = "usb_host_fs_fck", | |
972c5427 | 2512 | .ops = &clkops_omap2_dflt, |
0e433271 | 2513 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, |
972c5427 RN |
2514 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
2515 | .clkdm_name = "l3_init_clkdm", | |
0e433271 | 2516 | .parent = &func_48mc_fclk, |
972c5427 RN |
2517 | .recalc = &followparent_recalc, |
2518 | }; | |
2519 | ||
1c03f42f BC |
2520 | static const struct clksel utmi_p1_gfclk_sel[] = { |
2521 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, | |
2522 | { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, | |
2523 | { .parent = NULL }, | |
2524 | }; | |
2525 | ||
2526 | static struct clk utmi_p1_gfclk = { | |
2527 | .name = "utmi_p1_gfclk", | |
2528 | .parent = &init_60m_fclk, | |
2529 | .clksel = utmi_p1_gfclk_sel, | |
2530 | .init = &omap2_init_clksel_parent, | |
2531 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2532 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, | |
2533 | .ops = &clkops_null, | |
2534 | .recalc = &omap2_clksel_recalc, | |
2535 | }; | |
2536 | ||
2537 | static struct clk usb_host_hs_utmi_p1_clk = { | |
2538 | .name = "usb_host_hs_utmi_p1_clk", | |
2539 | .ops = &clkops_omap2_dflt, | |
2540 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2541 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, | |
2542 | .clkdm_name = "l3_init_clkdm", | |
2543 | .parent = &utmi_p1_gfclk, | |
2544 | .recalc = &followparent_recalc, | |
2545 | }; | |
2546 | ||
2547 | static const struct clksel utmi_p2_gfclk_sel[] = { | |
2548 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, | |
2549 | { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, | |
2550 | { .parent = NULL }, | |
2551 | }; | |
2552 | ||
2553 | static struct clk utmi_p2_gfclk = { | |
2554 | .name = "utmi_p2_gfclk", | |
2555 | .parent = &init_60m_fclk, | |
2556 | .clksel = utmi_p2_gfclk_sel, | |
2557 | .init = &omap2_init_clksel_parent, | |
2558 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2559 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, | |
2560 | .ops = &clkops_null, | |
2561 | .recalc = &omap2_clksel_recalc, | |
2562 | }; | |
2563 | ||
2564 | static struct clk usb_host_hs_utmi_p2_clk = { | |
2565 | .name = "usb_host_hs_utmi_p2_clk", | |
2566 | .ops = &clkops_omap2_dflt, | |
2567 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2568 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, | |
2569 | .clkdm_name = "l3_init_clkdm", | |
2570 | .parent = &utmi_p2_gfclk, | |
2571 | .recalc = &followparent_recalc, | |
2572 | }; | |
2573 | ||
032b5a7e TG |
2574 | static struct clk usb_host_hs_utmi_p3_clk = { |
2575 | .name = "usb_host_hs_utmi_p3_clk", | |
2576 | .ops = &clkops_omap2_dflt, | |
2577 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2578 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, | |
2579 | .clkdm_name = "l3_init_clkdm", | |
2580 | .parent = &init_60m_fclk, | |
2581 | .recalc = &followparent_recalc, | |
2582 | }; | |
2583 | ||
1c03f42f BC |
2584 | static struct clk usb_host_hs_hsic480m_p1_clk = { |
2585 | .name = "usb_host_hs_hsic480m_p1_clk", | |
2586 | .ops = &clkops_omap2_dflt, | |
2587 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2588 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, | |
2589 | .clkdm_name = "l3_init_clkdm", | |
2590 | .parent = &dpll_usb_m2_ck, | |
2591 | .recalc = &followparent_recalc, | |
2592 | }; | |
2593 | ||
032b5a7e TG |
2594 | static struct clk usb_host_hs_hsic60m_p1_clk = { |
2595 | .name = "usb_host_hs_hsic60m_p1_clk", | |
2596 | .ops = &clkops_omap2_dflt, | |
2597 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2598 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, | |
2599 | .clkdm_name = "l3_init_clkdm", | |
2600 | .parent = &init_60m_fclk, | |
2601 | .recalc = &followparent_recalc, | |
2602 | }; | |
2603 | ||
2604 | static struct clk usb_host_hs_hsic60m_p2_clk = { | |
2605 | .name = "usb_host_hs_hsic60m_p2_clk", | |
2606 | .ops = &clkops_omap2_dflt, | |
2607 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2608 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, | |
2609 | .clkdm_name = "l3_init_clkdm", | |
2610 | .parent = &init_60m_fclk, | |
2611 | .recalc = &followparent_recalc, | |
2612 | }; | |
2613 | ||
1c03f42f BC |
2614 | static struct clk usb_host_hs_hsic480m_p2_clk = { |
2615 | .name = "usb_host_hs_hsic480m_p2_clk", | |
2616 | .ops = &clkops_omap2_dflt, | |
2617 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2618 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, | |
2619 | .clkdm_name = "l3_init_clkdm", | |
2620 | .parent = &dpll_usb_m2_ck, | |
2621 | .recalc = &followparent_recalc, | |
2622 | }; | |
2623 | ||
2624 | static struct clk usb_host_hs_func48mclk = { | |
2625 | .name = "usb_host_hs_func48mclk", | |
2626 | .ops = &clkops_omap2_dflt, | |
2627 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2628 | .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, | |
2629 | .clkdm_name = "l3_init_clkdm", | |
2630 | .parent = &func_48mc_fclk, | |
2631 | .recalc = &followparent_recalc, | |
2632 | }; | |
2633 | ||
0e433271 BC |
2634 | static struct clk usb_host_hs_fck = { |
2635 | .name = "usb_host_hs_fck", | |
972c5427 RN |
2636 | .ops = &clkops_omap2_dflt, |
2637 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2638 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2639 | .clkdm_name = "l3_init_clkdm", | |
2640 | .parent = &init_60m_fclk, | |
2641 | .recalc = &followparent_recalc, | |
2642 | }; | |
2643 | ||
1c03f42f BC |
2644 | static const struct clksel otg_60m_gfclk_sel[] = { |
2645 | { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, | |
2646 | { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, | |
2647 | { .parent = NULL }, | |
2648 | }; | |
2649 | ||
2650 | static struct clk otg_60m_gfclk = { | |
2651 | .name = "otg_60m_gfclk", | |
2652 | .parent = &utmi_phy_clkout_ck, | |
2653 | .clksel = otg_60m_gfclk_sel, | |
2654 | .init = &omap2_init_clksel_parent, | |
2655 | .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
2656 | .clksel_mask = OMAP4430_CLKSEL_60M_MASK, | |
2657 | .ops = &clkops_null, | |
2658 | .recalc = &omap2_clksel_recalc, | |
2659 | }; | |
2660 | ||
2661 | static struct clk usb_otg_hs_xclk = { | |
2662 | .name = "usb_otg_hs_xclk", | |
2663 | .ops = &clkops_omap2_dflt, | |
2664 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
2665 | .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, | |
2666 | .clkdm_name = "l3_init_clkdm", | |
2667 | .parent = &otg_60m_gfclk, | |
2668 | .recalc = &followparent_recalc, | |
2669 | }; | |
2670 | ||
0e433271 BC |
2671 | static struct clk usb_otg_hs_ick = { |
2672 | .name = "usb_otg_hs_ick", | |
972c5427 RN |
2673 | .ops = &clkops_omap2_dflt, |
2674 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
2675 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2676 | .clkdm_name = "l3_init_clkdm", | |
2677 | .parent = &l3_div_ck, | |
2678 | .recalc = &followparent_recalc, | |
2679 | }; | |
2680 | ||
0edc9e85 BC |
2681 | static struct clk usb_phy_cm_clk32k = { |
2682 | .name = "usb_phy_cm_clk32k", | |
2683 | .ops = &clkops_omap2_dflt, | |
2684 | .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, | |
2685 | .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, | |
2686 | .clkdm_name = "l4_ao_clkdm", | |
2687 | .parent = &sys_32k_ck, | |
2688 | .recalc = &followparent_recalc, | |
2689 | }; | |
2690 | ||
1c03f42f BC |
2691 | static struct clk usb_tll_hs_usb_ch2_clk = { |
2692 | .name = "usb_tll_hs_usb_ch2_clk", | |
2693 | .ops = &clkops_omap2_dflt, | |
2694 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2695 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, | |
2696 | .clkdm_name = "l3_init_clkdm", | |
2697 | .parent = &init_60m_fclk, | |
2698 | .recalc = &followparent_recalc, | |
2699 | }; | |
2700 | ||
2701 | static struct clk usb_tll_hs_usb_ch0_clk = { | |
2702 | .name = "usb_tll_hs_usb_ch0_clk", | |
2703 | .ops = &clkops_omap2_dflt, | |
2704 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2705 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, | |
2706 | .clkdm_name = "l3_init_clkdm", | |
2707 | .parent = &init_60m_fclk, | |
2708 | .recalc = &followparent_recalc, | |
2709 | }; | |
2710 | ||
2711 | static struct clk usb_tll_hs_usb_ch1_clk = { | |
2712 | .name = "usb_tll_hs_usb_ch1_clk", | |
2713 | .ops = &clkops_omap2_dflt, | |
2714 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2715 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, | |
2716 | .clkdm_name = "l3_init_clkdm", | |
2717 | .parent = &init_60m_fclk, | |
2718 | .recalc = &followparent_recalc, | |
2719 | }; | |
2720 | ||
0e433271 BC |
2721 | static struct clk usb_tll_hs_ick = { |
2722 | .name = "usb_tll_hs_ick", | |
972c5427 RN |
2723 | .ops = &clkops_omap2_dflt, |
2724 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2725 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2726 | .clkdm_name = "l3_init_clkdm", | |
2727 | .parent = &l4_div_ck, | |
2728 | .recalc = &followparent_recalc, | |
2729 | }; | |
2730 | ||
0edc9e85 BC |
2731 | static const struct clksel_rate div2_14to18_rates[] = { |
2732 | { .div = 14, .val = 0, .flags = RATE_IN_4430 }, | |
2733 | { .div = 18, .val = 1, .flags = RATE_IN_4430 }, | |
2734 | { .div = 0 }, | |
2735 | }; | |
2736 | ||
2737 | static const struct clksel usim_fclk_div[] = { | |
032b5a7e | 2738 | { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates }, |
0edc9e85 BC |
2739 | { .parent = NULL }, |
2740 | }; | |
2741 | ||
2742 | static struct clk usim_ck = { | |
2743 | .name = "usim_ck", | |
032b5a7e | 2744 | .parent = &dpll_per_m4x2_ck, |
0edc9e85 BC |
2745 | .clksel = usim_fclk_div, |
2746 | .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | |
2747 | .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, | |
2748 | .ops = &clkops_null, | |
2749 | .recalc = &omap2_clksel_recalc, | |
2750 | .round_rate = &omap2_clksel_round_rate, | |
2751 | .set_rate = &omap2_clksel_set_rate, | |
2752 | }; | |
2753 | ||
2754 | static struct clk usim_fclk = { | |
2755 | .name = "usim_fclk", | |
2756 | .ops = &clkops_omap2_dflt, | |
2757 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | |
2758 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, | |
2759 | .clkdm_name = "l4_wkup_clkdm", | |
2760 | .parent = &usim_ck, | |
2761 | .recalc = &followparent_recalc, | |
2762 | }; | |
2763 | ||
0e433271 BC |
2764 | static struct clk usim_fck = { |
2765 | .name = "usim_fck", | |
972c5427 RN |
2766 | .ops = &clkops_omap2_dflt, |
2767 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | |
76cf5295 | 2768 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
972c5427 RN |
2769 | .clkdm_name = "l4_wkup_clkdm", |
2770 | .parent = &sys_32k_ck, | |
2771 | .recalc = &followparent_recalc, | |
2772 | }; | |
2773 | ||
0e433271 BC |
2774 | static struct clk wd_timer2_fck = { |
2775 | .name = "wd_timer2_fck", | |
972c5427 RN |
2776 | .ops = &clkops_omap2_dflt, |
2777 | .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, | |
2778 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2779 | .clkdm_name = "l4_wkup_clkdm", | |
2780 | .parent = &sys_32k_ck, | |
2781 | .recalc = &followparent_recalc, | |
2782 | }; | |
2783 | ||
0e433271 BC |
2784 | static struct clk wd_timer3_fck = { |
2785 | .name = "wd_timer3_fck", | |
972c5427 RN |
2786 | .ops = &clkops_omap2_dflt, |
2787 | .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, | |
2788 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2789 | .clkdm_name = "abe_clkdm", | |
2790 | .parent = &sys_32k_ck, | |
2791 | .recalc = &followparent_recalc, | |
2792 | }; | |
2793 | ||
2794 | /* Remaining optional clocks */ | |
972c5427 RN |
2795 | static const struct clksel stm_clk_div_div[] = { |
2796 | { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, | |
2797 | { .parent = NULL }, | |
2798 | }; | |
2799 | ||
2800 | static struct clk stm_clk_div_ck = { | |
2801 | .name = "stm_clk_div_ck", | |
2802 | .parent = &pmd_stm_clock_mux_ck, | |
2803 | .clksel = stm_clk_div_div, | |
2804 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
2805 | .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, | |
2806 | .ops = &clkops_null, | |
2807 | .recalc = &omap2_clksel_recalc, | |
2808 | .round_rate = &omap2_clksel_round_rate, | |
2809 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
2810 | }; |
2811 | ||
2812 | static const struct clksel trace_clk_div_div[] = { | |
2813 | { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, | |
2814 | { .parent = NULL }, | |
2815 | }; | |
2816 | ||
2817 | static struct clk trace_clk_div_ck = { | |
2818 | .name = "trace_clk_div_ck", | |
2819 | .parent = &pmd_trace_clk_mux_ck, | |
2820 | .clksel = trace_clk_div_div, | |
2821 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
2822 | .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, | |
2823 | .ops = &clkops_null, | |
2824 | .recalc = &omap2_clksel_recalc, | |
2825 | .round_rate = &omap2_clksel_round_rate, | |
2826 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
2827 | }; |
2828 | ||
e0cb70c5 RN |
2829 | /* SCRM aux clk nodes */ |
2830 | ||
2831 | static const struct clksel auxclk_sel[] = { | |
2832 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
2833 | { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, | |
2834 | { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, | |
2835 | { .parent = NULL }, | |
2836 | }; | |
2837 | ||
2838 | static struct clk auxclk0_ck = { | |
2839 | .name = "auxclk0_ck", | |
2840 | .parent = &sys_clkin_ck, | |
2841 | .init = &omap2_init_clksel_parent, | |
2842 | .ops = &clkops_omap2_dflt, | |
2843 | .clksel = auxclk_sel, | |
2844 | .clksel_reg = OMAP4_SCRM_AUXCLK0, | |
2845 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2846 | .recalc = &omap2_clksel_recalc, | |
2847 | .enable_reg = OMAP4_SCRM_AUXCLK0, | |
2848 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2849 | }; | |
2850 | ||
2851 | static struct clk auxclk1_ck = { | |
2852 | .name = "auxclk1_ck", | |
2853 | .parent = &sys_clkin_ck, | |
2854 | .init = &omap2_init_clksel_parent, | |
2855 | .ops = &clkops_omap2_dflt, | |
2856 | .clksel = auxclk_sel, | |
2857 | .clksel_reg = OMAP4_SCRM_AUXCLK1, | |
2858 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2859 | .recalc = &omap2_clksel_recalc, | |
2860 | .enable_reg = OMAP4_SCRM_AUXCLK1, | |
2861 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2862 | }; | |
2863 | ||
2864 | static struct clk auxclk2_ck = { | |
2865 | .name = "auxclk2_ck", | |
2866 | .parent = &sys_clkin_ck, | |
2867 | .init = &omap2_init_clksel_parent, | |
2868 | .ops = &clkops_omap2_dflt, | |
2869 | .clksel = auxclk_sel, | |
2870 | .clksel_reg = OMAP4_SCRM_AUXCLK2, | |
2871 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2872 | .recalc = &omap2_clksel_recalc, | |
2873 | .enable_reg = OMAP4_SCRM_AUXCLK2, | |
2874 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2875 | }; | |
2876 | static struct clk auxclk3_ck = { | |
2877 | .name = "auxclk3_ck", | |
2878 | .parent = &sys_clkin_ck, | |
2879 | .init = &omap2_init_clksel_parent, | |
2880 | .ops = &clkops_omap2_dflt, | |
2881 | .clksel = auxclk_sel, | |
2882 | .clksel_reg = OMAP4_SCRM_AUXCLK3, | |
2883 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2884 | .recalc = &omap2_clksel_recalc, | |
2885 | .enable_reg = OMAP4_SCRM_AUXCLK3, | |
2886 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2887 | }; | |
2888 | ||
2889 | static struct clk auxclk4_ck = { | |
2890 | .name = "auxclk4_ck", | |
2891 | .parent = &sys_clkin_ck, | |
2892 | .init = &omap2_init_clksel_parent, | |
2893 | .ops = &clkops_omap2_dflt, | |
2894 | .clksel = auxclk_sel, | |
2895 | .clksel_reg = OMAP4_SCRM_AUXCLK4, | |
2896 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2897 | .recalc = &omap2_clksel_recalc, | |
2898 | .enable_reg = OMAP4_SCRM_AUXCLK4, | |
2899 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2900 | }; | |
2901 | ||
2902 | static struct clk auxclk5_ck = { | |
2903 | .name = "auxclk5_ck", | |
2904 | .parent = &sys_clkin_ck, | |
2905 | .init = &omap2_init_clksel_parent, | |
2906 | .ops = &clkops_omap2_dflt, | |
2907 | .clksel = auxclk_sel, | |
2908 | .clksel_reg = OMAP4_SCRM_AUXCLK5, | |
2909 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2910 | .recalc = &omap2_clksel_recalc, | |
2911 | .enable_reg = OMAP4_SCRM_AUXCLK5, | |
2912 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2913 | }; | |
2914 | ||
2915 | static const struct clksel auxclkreq_sel[] = { | |
2916 | { .parent = &auxclk0_ck, .rates = div_1_0_rates }, | |
2917 | { .parent = &auxclk1_ck, .rates = div_1_1_rates }, | |
2918 | { .parent = &auxclk2_ck, .rates = div_1_2_rates }, | |
2919 | { .parent = &auxclk3_ck, .rates = div_1_3_rates }, | |
2920 | { .parent = &auxclk4_ck, .rates = div_1_4_rates }, | |
2921 | { .parent = &auxclk5_ck, .rates = div_1_5_rates }, | |
2922 | { .parent = NULL }, | |
2923 | }; | |
2924 | ||
2925 | static struct clk auxclkreq0_ck = { | |
2926 | .name = "auxclkreq0_ck", | |
2927 | .parent = &auxclk0_ck, | |
2928 | .init = &omap2_init_clksel_parent, | |
2929 | .ops = &clkops_null, | |
2930 | .clksel = auxclkreq_sel, | |
2931 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ0, | |
2932 | .clksel_mask = OMAP4_MAPPING_MASK, | |
2933 | .recalc = &omap2_clksel_recalc, | |
2934 | }; | |
2935 | ||
2936 | static struct clk auxclkreq1_ck = { | |
2937 | .name = "auxclkreq1_ck", | |
2938 | .parent = &auxclk1_ck, | |
2939 | .init = &omap2_init_clksel_parent, | |
2940 | .ops = &clkops_null, | |
2941 | .clksel = auxclkreq_sel, | |
2942 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ1, | |
2943 | .clksel_mask = OMAP4_MAPPING_MASK, | |
2944 | .recalc = &omap2_clksel_recalc, | |
2945 | }; | |
2946 | ||
2947 | static struct clk auxclkreq2_ck = { | |
2948 | .name = "auxclkreq2_ck", | |
2949 | .parent = &auxclk2_ck, | |
2950 | .init = &omap2_init_clksel_parent, | |
2951 | .ops = &clkops_null, | |
2952 | .clksel = auxclkreq_sel, | |
2953 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ2, | |
2954 | .clksel_mask = OMAP4_MAPPING_MASK, | |
2955 | .recalc = &omap2_clksel_recalc, | |
2956 | }; | |
2957 | ||
2958 | static struct clk auxclkreq3_ck = { | |
2959 | .name = "auxclkreq3_ck", | |
2960 | .parent = &auxclk3_ck, | |
2961 | .init = &omap2_init_clksel_parent, | |
2962 | .ops = &clkops_null, | |
2963 | .clksel = auxclkreq_sel, | |
2964 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ3, | |
2965 | .clksel_mask = OMAP4_MAPPING_MASK, | |
2966 | .recalc = &omap2_clksel_recalc, | |
2967 | }; | |
2968 | ||
2969 | static struct clk auxclkreq4_ck = { | |
2970 | .name = "auxclkreq4_ck", | |
2971 | .parent = &auxclk4_ck, | |
2972 | .init = &omap2_init_clksel_parent, | |
2973 | .ops = &clkops_null, | |
2974 | .clksel = auxclkreq_sel, | |
2975 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ4, | |
2976 | .clksel_mask = OMAP4_MAPPING_MASK, | |
2977 | .recalc = &omap2_clksel_recalc, | |
2978 | }; | |
2979 | ||
2980 | static struct clk auxclkreq5_ck = { | |
2981 | .name = "auxclkreq5_ck", | |
2982 | .parent = &auxclk5_ck, | |
2983 | .init = &omap2_init_clksel_parent, | |
2984 | .ops = &clkops_null, | |
2985 | .clksel = auxclkreq_sel, | |
2986 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ5, | |
2987 | .clksel_mask = OMAP4_MAPPING_MASK, | |
2988 | .recalc = &omap2_clksel_recalc, | |
2989 | }; | |
2990 | ||
972c5427 RN |
2991 | /* |
2992 | * clkdev | |
2993 | */ | |
2994 | ||
2995 | static struct omap_clk omap44xx_clks[] = { | |
2996 | CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), | |
2997 | CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), | |
2998 | CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), | |
2999 | CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), | |
3000 | CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), | |
3001 | CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), | |
3002 | CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), | |
3003 | CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), | |
3004 | CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), | |
3005 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), | |
3006 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), | |
3007 | CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), | |
3008 | CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), | |
3009 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), | |
76cf5295 | 3010 | CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), |
972c5427 RN |
3011 | CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), |
3012 | CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), | |
3013 | CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), | |
3014 | CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), | |
76cf5295 | 3015 | CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), |
972c5427 RN |
3016 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), |
3017 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), | |
032b5a7e | 3018 | CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), |
972c5427 RN |
3019 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), |
3020 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), | |
3021 | CLK(NULL, "abe_clk", &abe_clk, CK_443X), | |
3022 | CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), | |
032b5a7e | 3023 | CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), |
972c5427 RN |
3024 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), |
3025 | CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), | |
032b5a7e TG |
3026 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), |
3027 | CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), | |
972c5427 RN |
3028 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), |
3029 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), | |
3030 | CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), | |
032b5a7e | 3031 | CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), |
972c5427 RN |
3032 | CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), |
3033 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), | |
3034 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), | |
032b5a7e | 3035 | CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), |
972c5427 RN |
3036 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), |
3037 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), | |
032b5a7e TG |
3038 | CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), |
3039 | CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), | |
972c5427 RN |
3040 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), |
3041 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), | |
032b5a7e TG |
3042 | CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), |
3043 | CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), | |
3044 | CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), | |
972c5427 RN |
3045 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), |
3046 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), | |
3047 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), | |
3048 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), | |
3049 | CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), | |
3050 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), | |
032b5a7e | 3051 | CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), |
972c5427 | 3052 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), |
032b5a7e TG |
3053 | CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), |
3054 | CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), | |
3055 | CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), | |
3056 | CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), | |
3057 | CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), | |
972c5427 | 3058 | CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), |
032b5a7e | 3059 | CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X), |
972c5427 RN |
3060 | CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), |
3061 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), | |
3062 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), | |
3063 | CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), | |
3064 | CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), | |
3065 | CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), | |
3066 | CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), | |
3067 | CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), | |
3068 | CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), | |
3069 | CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), | |
3070 | CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), | |
3071 | CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), | |
3072 | CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), | |
3073 | CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X), | |
3074 | CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), | |
3075 | CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), | |
3076 | CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), | |
3077 | CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), | |
3078 | CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), | |
3079 | CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), | |
3080 | CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X), | |
3081 | CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X), | |
3082 | CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), | |
3083 | CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), | |
3084 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), | |
3085 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), | |
3086 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), | |
54776050 RN |
3087 | CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), |
3088 | CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), | |
3089 | CLK(NULL, "aess_fck", &aess_fck, CK_443X), | |
1c03f42f | 3090 | CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), |
54776050 | 3091 | CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), |
972c5427 | 3092 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), |
54776050 | 3093 | CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), |
0e433271 | 3094 | CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), |
1c03f42f BC |
3095 | CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), |
3096 | CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), | |
3097 | CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), | |
3098 | CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), | |
54776050 | 3099 | CLK(NULL, "dss_fck", &dss_fck, CK_443X), |
0e433271 BC |
3100 | CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), |
3101 | CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), | |
3102 | CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), | |
54776050 | 3103 | CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), |
0e433271 | 3104 | CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), |
1c03f42f | 3105 | CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X), |
54776050 | 3106 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), |
1c03f42f | 3107 | CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X), |
54776050 | 3108 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), |
1c03f42f | 3109 | CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X), |
54776050 | 3110 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), |
1c03f42f | 3111 | CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X), |
54776050 | 3112 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), |
1c03f42f | 3113 | CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X), |
54776050 | 3114 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), |
1c03f42f | 3115 | CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X), |
54776050 RN |
3116 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), |
3117 | CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), | |
0e433271 | 3118 | CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), |
54776050 | 3119 | CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), |
0e433271 | 3120 | CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), |
f7bb0d9a BC |
3121 | CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X), |
3122 | CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X), | |
3123 | CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X), | |
3124 | CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X), | |
0e433271 | 3125 | CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), |
1c03f42f | 3126 | CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), |
54776050 | 3127 | CLK(NULL, "iss_fck", &iss_fck, CK_443X), |
0e433271 BC |
3128 | CLK(NULL, "iva_fck", &iva_fck, CK_443X), |
3129 | CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), | |
3130 | CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), | |
3131 | CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), | |
972c5427 | 3132 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), |
54776050 | 3133 | CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), |
972c5427 | 3134 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), |
54776050 | 3135 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X), |
972c5427 | 3136 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), |
54776050 | 3137 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X), |
972c5427 | 3138 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), |
54776050 | 3139 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), |
972c5427 | 3140 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), |
54776050 | 3141 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), |
0e433271 | 3142 | CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), |
54776050 RN |
3143 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), |
3144 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), | |
3145 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), | |
3146 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), | |
3147 | CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X), | |
3148 | CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X), | |
3149 | CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), | |
3150 | CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), | |
3151 | CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), | |
1c03f42f | 3152 | CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), |
0edc9e85 | 3153 | CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), |
0e433271 | 3154 | CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), |
54776050 | 3155 | CLK("omap_rng", "ick", &rng_ick, CK_443X), |
0e433271 BC |
3156 | CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), |
3157 | CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), | |
1c03f42f BC |
3158 | CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), |
3159 | CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), | |
3160 | CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), | |
3161 | CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), | |
54776050 | 3162 | CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), |
1c03f42f BC |
3163 | CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), |
3164 | CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), | |
3165 | CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), | |
54776050 | 3166 | CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), |
0e433271 BC |
3167 | CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), |
3168 | CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), | |
3169 | CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), | |
3170 | CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X), | |
3171 | CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X), | |
3172 | CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X), | |
3173 | CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X), | |
3174 | CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X), | |
3175 | CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X), | |
3176 | CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X), | |
3177 | CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X), | |
3178 | CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X), | |
3179 | CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X), | |
3180 | CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X), | |
54776050 RN |
3181 | CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), |
3182 | CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), | |
3183 | CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), | |
3184 | CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), | |
54776050 | 3185 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), |
1c03f42f BC |
3186 | CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), |
3187 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), | |
3188 | CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), | |
3189 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), | |
032b5a7e | 3190 | CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), |
1c03f42f | 3191 | CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), |
032b5a7e TG |
3192 | CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), |
3193 | CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), | |
1c03f42f BC |
3194 | CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), |
3195 | CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), | |
0e433271 | 3196 | CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), |
1c03f42f BC |
3197 | CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), |
3198 | CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), | |
0e433271 | 3199 | CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X), |
0edc9e85 | 3200 | CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), |
1c03f42f BC |
3201 | CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), |
3202 | CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), | |
3203 | CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), | |
0e433271 | 3204 | CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), |
0edc9e85 BC |
3205 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), |
3206 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), | |
0e433271 BC |
3207 | CLK(NULL, "usim_fck", &usim_fck, CK_443X), |
3208 | CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), | |
3209 | CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), | |
972c5427 RN |
3210 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), |
3211 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), | |
7c43d547 SS |
3212 | CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), |
3213 | CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), | |
3214 | CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), | |
3215 | CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X), | |
3216 | CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X), | |
3217 | CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X), | |
3218 | CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X), | |
3219 | CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X), | |
3220 | CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X), | |
3221 | CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), | |
3222 | CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), | |
3223 | CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), | |
f7bb0d9a BC |
3224 | CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), |
3225 | CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), | |
3226 | CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), | |
3227 | CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), | |
0e433271 BC |
3228 | CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), |
3229 | CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), | |
3230 | CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), | |
3231 | CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), | |
3232 | CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), | |
7c43d547 SS |
3233 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), |
3234 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), | |
3235 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), | |
3236 | CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), | |
0e433271 BC |
3237 | CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), |
3238 | CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), | |
3239 | CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), | |
3240 | CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), | |
7c43d547 SS |
3241 | CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), |
3242 | CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), | |
3243 | CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), | |
3244 | CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), | |
3245 | CLK("omap_wdt", "ick", &dummy_ck, CK_443X), | |
e0cb70c5 RN |
3246 | CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), |
3247 | CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), | |
3248 | CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), | |
3249 | CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), | |
3250 | CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), | |
3251 | CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), | |
3252 | CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), | |
3253 | CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), | |
3254 | CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), | |
3255 | CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), | |
3256 | CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), | |
3257 | CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), | |
972c5427 RN |
3258 | }; |
3259 | ||
e80a9729 | 3260 | int __init omap4xxx_clk_init(void) |
972c5427 | 3261 | { |
972c5427 | 3262 | struct omap_clk *c; |
972c5427 RN |
3263 | u32 cpu_clkflg; |
3264 | ||
3265 | if (cpu_is_omap44xx()) { | |
3266 | cpu_mask = RATE_IN_4430; | |
3267 | cpu_clkflg = CK_443X; | |
3268 | } | |
3269 | ||
3270 | clk_init(&omap2_clk_functions); | |
3271 | ||
3272 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); | |
3273 | c++) | |
3274 | clk_preinit(c->lk.clk); | |
3275 | ||
3276 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); | |
3277 | c++) | |
3278 | if (c->cpu & cpu_clkflg) { | |
3279 | clkdev_add(&c->lk); | |
3280 | clk_register(c->lk.clk); | |
972c5427 | 3281 | omap2_init_clk_clkdm(c->lk.clk); |
972c5427 RN |
3282 | } |
3283 | ||
3284 | recalculate_root_clocks(); | |
3285 | ||
3286 | /* | |
3287 | * Only enable those clocks we will need, let the drivers | |
3288 | * enable other clocks as necessary | |
3289 | */ | |
3290 | clk_enable_init_clocks(); | |
3291 | ||
3292 | return 0; | |
3293 | } |