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OMAP3 clock: add support for 192Mhz DPLL4M2 output
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / clock44xx_data.c
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972c5427
RN		 1/*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/clk.h>
25
26#include <plat/control.h>
27#include <plat/clkdev_omap.h>
28
29#include "clock.h"
30#include "clock44xx.h"
31#include "cm.h"
32#include "cm-regbits-44xx.h"
33#include "prm.h"
34#include "prm-regbits-44xx.h"
35
36/* Root clocks */
37
38static struct clk extalt_clkin_ck = {
39 .name = "extalt_clkin_ck",
40 .rate = 59000000,
41 .ops = &clkops_null,
42 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
43};
44
45static struct clk pad_clks_ck = {
46 .name = "pad_clks_ck",
47 .rate = 12000000,
48 .ops = &clkops_null,
49 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
50};
51
52static struct clk pad_slimbus_core_clks_ck = {
53 .name = "pad_slimbus_core_clks_ck",
54 .rate = 12000000,
55 .ops = &clkops_null,
56 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
57};
58
59static struct clk secure_32k_clk_src_ck = {
60 .name = "secure_32k_clk_src_ck",
61 .rate = 32768,
62 .ops = &clkops_null,
63 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
64};
65
66static struct clk slimbus_clk = {
67 .name = "slimbus_clk",
68 .rate = 12000000,
69 .ops = &clkops_null,
70 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
71};
72
73static struct clk sys_32k_ck = {
74 .name = "sys_32k_ck",
75 .rate = 32768,
76 .ops = &clkops_null,
77 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
78};
79
80static struct clk virt_12000000_ck = {
81 .name = "virt_12000000_ck",
82 .ops = &clkops_null,
83 .rate = 12000000,
84};
85
86static struct clk virt_13000000_ck = {
87 .name = "virt_13000000_ck",
88 .ops = &clkops_null,
89 .rate = 13000000,
90};
91
92static struct clk virt_16800000_ck = {
93 .name = "virt_16800000_ck",
94 .ops = &clkops_null,
95 .rate = 16800000,
96};
97
98static struct clk virt_19200000_ck = {
99 .name = "virt_19200000_ck",
100 .ops = &clkops_null,
101 .rate = 19200000,
102};
103
104static struct clk virt_26000000_ck = {
105 .name = "virt_26000000_ck",
106 .ops = &clkops_null,
107 .rate = 26000000,
108};
109
110static struct clk virt_27000000_ck = {
111 .name = "virt_27000000_ck",
112 .ops = &clkops_null,
113 .rate = 27000000,
114};
115
116static struct clk virt_38400000_ck = {
117 .name = "virt_38400000_ck",
118 .ops = &clkops_null,
119 .rate = 38400000,
120};
121
122static const struct clksel_rate div_1_0_rates[] = {
123 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
124 { .div = 0 },
125};
126
127static const struct clksel_rate div_1_1_rates[] = {
128 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
129 { .div = 0 },
130};
131
132static const struct clksel_rate div_1_2_rates[] = {
133 { .div = 1, .val = 2, .flags = RATE_IN_4430 },
134 { .div = 0 },
135};
136
137static const struct clksel_rate div_1_3_rates[] = {
138 { .div = 1, .val = 3, .flags = RATE_IN_4430 },
139 { .div = 0 },
140};
141
142static const struct clksel_rate div_1_4_rates[] = {
143 { .div = 1, .val = 4, .flags = RATE_IN_4430 },
144 { .div = 0 },
145};
146
147static const struct clksel_rate div_1_5_rates[] = {
148 { .div = 1, .val = 5, .flags = RATE_IN_4430 },
149 { .div = 0 },
150};
151
152static const struct clksel_rate div_1_6_rates[] = {
153 { .div = 1, .val = 6, .flags = RATE_IN_4430 },
154 { .div = 0 },
155};
156
157static const struct clksel_rate div_1_7_rates[] = {
158 { .div = 1, .val = 7, .flags = RATE_IN_4430 },
159 { .div = 0 },
160};
161
162static const struct clksel sys_clkin_sel[] = {
163 { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
164 { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
165 { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
166 { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
167 { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
168 { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
169 { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
170 { .parent = NULL },
171};
172
173static struct clk sys_clkin_ck = {
174 .name = "sys_clkin_ck",
175 .rate = 38400000,
176 .clksel = sys_clkin_sel,
177 .init = &omap2_init_clksel_parent,
178 .clksel_reg = OMAP4430_CM_SYS_CLKSEL,
179 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
180 .ops = &clkops_null,
181 .recalc = &omap2_clksel_recalc,
182 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
183};
184
185static struct clk utmi_phy_clkout_ck = {
186 .name = "utmi_phy_clkout_ck",
187 .rate = 12000000,
188 .ops = &clkops_null,
189 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
190};
191
192static struct clk xclk60mhsp1_ck = {
193 .name = "xclk60mhsp1_ck",
194 .rate = 12000000,
195 .ops = &clkops_null,
196 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
197};
198
199static struct clk xclk60mhsp2_ck = {
200 .name = "xclk60mhsp2_ck",
201 .rate = 12000000,
202 .ops = &clkops_null,
203 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
204};
205
206static struct clk xclk60motg_ck = {
207 .name = "xclk60motg_ck",
208 .rate = 60000000,
209 .ops = &clkops_null,
210 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
211};
212
213/* Module clocks and DPLL outputs */
214
215static const struct clksel_rate div2_1to2_rates[] = {
216 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
217 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
218 { .div = 0 },
219};
220
221static const struct clksel dpll_sys_ref_clk_div[] = {
222 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
223 { .parent = NULL },
224};
225
226static struct clk dpll_sys_ref_clk = {
227 .name = "dpll_sys_ref_clk",
228 .parent = &sys_clkin_ck,
229 .clksel = dpll_sys_ref_clk_div,
230 .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
231 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
232 .ops = &clkops_null,
233 .recalc = &omap2_clksel_recalc,
234 .round_rate = &omap2_clksel_round_rate,
235 .set_rate = &omap2_clksel_set_rate,
236 .flags = CLOCK_IN_OMAP4430,
237};
238
239static const struct clksel abe_dpll_refclk_mux_sel[] = {
240 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
241 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
242 { .parent = NULL },
243};
244
245static struct clk abe_dpll_refclk_mux_ck = {
246 .name = "abe_dpll_refclk_mux_ck",
247 .parent = &dpll_sys_ref_clk,
248 .clksel = abe_dpll_refclk_mux_sel,
249 .init = &omap2_init_clksel_parent,
250 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
251 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
252 .ops = &clkops_null,
253 .recalc = &omap2_clksel_recalc,
254 .flags = CLOCK_IN_OMAP4430,
255};
256
257/* DPLL_ABE */
258static struct dpll_data dpll_abe_dd = {
259 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
260 .clk_bypass = &sys_clkin_ck,
261 .clk_ref = &abe_dpll_refclk_mux_ck,
262 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
263 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
264 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
265 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
266 .mult_mask = OMAP4430_DPLL_MULT_MASK,
267 .div1_mask = OMAP4430_DPLL_DIV_MASK,
268 .enable_mask = OMAP4430_DPLL_EN_MASK,
269 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
270 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
271 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
272 .max_divider = OMAP4430_MAX_DPLL_DIV,
273 .min_divider = 1,
274};
275
276
277static struct clk dpll_abe_ck = {
278 .name = "dpll_abe_ck",
279 .parent = &abe_dpll_refclk_mux_ck,
280 .dpll_data = &dpll_abe_dd,
911bd739 281 .init = &omap2_init_dpll_parent,
4751227d 282 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 283 .recalc = &omap3_dpll_recalc,
284 .round_rate = &omap2_dpll_round_rate,
285 .set_rate = &omap3_noncore_dpll_set_rate,
286 .flags = CLOCK_IN_OMAP4430,
287};
288
289static struct clk dpll_abe_m2x2_ck = {
290 .name = "dpll_abe_m2x2_ck",
291 .parent = &dpll_abe_ck,
292 .ops = &clkops_null,
293 .recalc = &followparent_recalc,
294 .flags = CLOCK_IN_OMAP4430,
295};
296
297static struct clk abe_24m_fclk = {
298 .name = "abe_24m_fclk",
299 .parent = &dpll_abe_m2x2_ck,
300 .ops = &clkops_null,
301 .recalc = &followparent_recalc,
302 .flags = CLOCK_IN_OMAP4430,
303};
304
305static const struct clksel_rate div3_1to4_rates[] = {
306 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
307 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
308 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
309 { .div = 0 },
310};
311
312static const struct clksel abe_clk_div[] = {
313 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
314 { .parent = NULL },
315};
316
317static struct clk abe_clk = {
318 .name = "abe_clk",
319 .parent = &dpll_abe_m2x2_ck,
320 .clksel = abe_clk_div,
321 .clksel_reg = OMAP4430_CM_CLKSEL_ABE,
322 .clksel_mask = OMAP4430_CLKSEL_OPP_MASK,
323 .ops = &clkops_null,
324 .recalc = &omap2_clksel_recalc,
325 .round_rate = &omap2_clksel_round_rate,
326 .set_rate = &omap2_clksel_set_rate,
327 .flags = CLOCK_IN_OMAP4430,
328};
329
330static const struct clksel aess_fclk_div[] = {
331 { .parent = &abe_clk, .rates = div2_1to2_rates },
332 { .parent = NULL },
333};
334
335static struct clk aess_fclk = {
336 .name = "aess_fclk",
337 .parent = &abe_clk,
338 .clksel = aess_fclk_div,
339 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
340 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
341 .ops = &clkops_null,
342 .recalc = &omap2_clksel_recalc,
343 .round_rate = &omap2_clksel_round_rate,
344 .set_rate = &omap2_clksel_set_rate,
345 .flags = CLOCK_IN_OMAP4430,
346};
347
348static const struct clksel_rate div31_1to31_rates[] = {
ecbb0659
RN		 349 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
350 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
351 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
352 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
353 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
354 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
355 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
356 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
357 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
358 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
359 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
360 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
361 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
362 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
363 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
364 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
365 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
366 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
367 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
368 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
369 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
370 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
371 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
372 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
373 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
374 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
375 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
376 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
377 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
378 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
379 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
972c5427
RN		 380 { .div = 0 },
381};
382
383static const struct clksel dpll_abe_m3_div[] = {
384 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
385 { .parent = NULL },
386};
387
388static struct clk dpll_abe_m3_ck = {
389 .name = "dpll_abe_m3_ck",
390 .parent = &dpll_abe_ck,
391 .clksel = dpll_abe_m3_div,
392 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
393 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
394 .ops = &clkops_null,
395 .recalc = &omap2_clksel_recalc,
396 .round_rate = &omap2_clksel_round_rate,
397 .set_rate = &omap2_clksel_set_rate,
398 .flags = CLOCK_IN_OMAP4430,
399};
400
401static const struct clksel core_hsd_byp_clk_mux_sel[] = {
402 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
403 { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
404 { .parent = NULL },
405};
406
407static struct clk core_hsd_byp_clk_mux_ck = {
408 .name = "core_hsd_byp_clk_mux_ck",
409 .parent = &dpll_sys_ref_clk,
410 .clksel = core_hsd_byp_clk_mux_sel,
411 .init = &omap2_init_clksel_parent,
412 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
413 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
414 .ops = &clkops_null,
415 .recalc = &omap2_clksel_recalc,
416 .flags = CLOCK_IN_OMAP4430,
417};
418
419/* DPLL_CORE */
420static struct dpll_data dpll_core_dd = {
421 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
422 .clk_bypass = &core_hsd_byp_clk_mux_ck,
423 .clk_ref = &dpll_sys_ref_clk,
424 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
425 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
426 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
427 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
428 .mult_mask = OMAP4430_DPLL_MULT_MASK,
429 .div1_mask = OMAP4430_DPLL_DIV_MASK,
430 .enable_mask = OMAP4430_DPLL_EN_MASK,
431 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
432 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
433 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
434 .max_divider = OMAP4430_MAX_DPLL_DIV,
435 .min_divider = 1,
436};
437
438
439static struct clk dpll_core_ck = {
440 .name = "dpll_core_ck",
441 .parent = &dpll_sys_ref_clk,
442 .dpll_data = &dpll_core_dd,
911bd739 443 .init = &omap2_init_dpll_parent,
972c5427
RN		 444 .ops = &clkops_null,
445 .recalc = &omap3_dpll_recalc,
446 .flags = CLOCK_IN_OMAP4430,
447};
448
449static const struct clksel dpll_core_m6_div[] = {
450 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
451 { .parent = NULL },
452};
453
454static struct clk dpll_core_m6_ck = {
455 .name = "dpll_core_m6_ck",
456 .parent = &dpll_core_ck,
457 .clksel = dpll_core_m6_div,
458 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
459 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
460 .ops = &clkops_null,
461 .recalc = &omap2_clksel_recalc,
462 .round_rate = &omap2_clksel_round_rate,
463 .set_rate = &omap2_clksel_set_rate,
464 .flags = CLOCK_IN_OMAP4430,
465};
466
467static const struct clksel dbgclk_mux_sel[] = {
468 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
469 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
470 { .parent = NULL },
471};
472
473static struct clk dbgclk_mux_ck = {
474 .name = "dbgclk_mux_ck",
475 .parent = &sys_clkin_ck,
476 .ops = &clkops_null,
477 .recalc = &followparent_recalc,
478 .flags = CLOCK_IN_OMAP4430,
479};
480
481static struct clk dpll_core_m2_ck = {
482 .name = "dpll_core_m2_ck",
483 .parent = &dpll_core_ck,
484 .clksel = dpll_core_m6_div,
485 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
486 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
487 .ops = &clkops_null,
488 .recalc = &omap2_clksel_recalc,
489 .round_rate = &omap2_clksel_round_rate,
490 .set_rate = &omap2_clksel_set_rate,
491 .flags = CLOCK_IN_OMAP4430,
492};
493
494static struct clk ddrphy_ck = {
495 .name = "ddrphy_ck",
496 .parent = &dpll_core_m2_ck,
497 .ops = &clkops_null,
498 .recalc = &followparent_recalc,
499 .flags = CLOCK_IN_OMAP4430,
500};
501
502static struct clk dpll_core_m5_ck = {
503 .name = "dpll_core_m5_ck",
504 .parent = &dpll_core_ck,
505 .clksel = dpll_core_m6_div,
506 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
507 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
508 .ops = &clkops_null,
509 .recalc = &omap2_clksel_recalc,
510 .round_rate = &omap2_clksel_round_rate,
511 .set_rate = &omap2_clksel_set_rate,
512 .flags = CLOCK_IN_OMAP4430,
513};
514
515static const struct clksel div_core_div[] = {
516 { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
517 { .parent = NULL },
518};
519
520static struct clk div_core_ck = {
521 .name = "div_core_ck",
522 .parent = &dpll_core_m5_ck,
523 .clksel = div_core_div,
524 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
525 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
526 .ops = &clkops_null,
527 .recalc = &omap2_clksel_recalc,
528 .round_rate = &omap2_clksel_round_rate,
529 .set_rate = &omap2_clksel_set_rate,
530 .flags = CLOCK_IN_OMAP4430,
531};
532
533static const struct clksel_rate div4_1to8_rates[] = {
534 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
535 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
536 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
537 { .div = 8, .val = 3, .flags = RATE_IN_4430 },
538 { .div = 0 },
539};
540
541static const struct clksel div_iva_hs_clk_div[] = {
542 { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
543 { .parent = NULL },
544};
545
546static struct clk div_iva_hs_clk = {
547 .name = "div_iva_hs_clk",
548 .parent = &dpll_core_m5_ck,
549 .clksel = div_iva_hs_clk_div,
550 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
551 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
552 .ops = &clkops_null,
553 .recalc = &omap2_clksel_recalc,
554 .round_rate = &omap2_clksel_round_rate,
555 .set_rate = &omap2_clksel_set_rate,
556 .flags = CLOCK_IN_OMAP4430,
557};
558
559static struct clk div_mpu_hs_clk = {
560 .name = "div_mpu_hs_clk",
561 .parent = &dpll_core_m5_ck,
562 .clksel = div_iva_hs_clk_div,
563 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
564 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
565 .ops = &clkops_null,
566 .recalc = &omap2_clksel_recalc,
567 .round_rate = &omap2_clksel_round_rate,
568 .set_rate = &omap2_clksel_set_rate,
569 .flags = CLOCK_IN_OMAP4430,
570};
571
572static struct clk dpll_core_m4_ck = {
573 .name = "dpll_core_m4_ck",
574 .parent = &dpll_core_ck,
575 .clksel = dpll_core_m6_div,
576 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
577 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
578 .ops = &clkops_null,
579 .recalc = &omap2_clksel_recalc,
580 .round_rate = &omap2_clksel_round_rate,
581 .set_rate = &omap2_clksel_set_rate,
582 .flags = CLOCK_IN_OMAP4430,
583};
584
585static struct clk dll_clk_div_ck = {
586 .name = "dll_clk_div_ck",
587 .parent = &dpll_core_m4_ck,
588 .ops = &clkops_null,
589 .recalc = &followparent_recalc,
590 .flags = CLOCK_IN_OMAP4430,
591};
592
593static struct clk dpll_abe_m2_ck = {
594 .name = "dpll_abe_m2_ck",
595 .parent = &dpll_abe_ck,
596 .clksel = dpll_abe_m3_div,
597 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
598 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
599 .ops = &clkops_null,
600 .recalc = &omap2_clksel_recalc,
601 .round_rate = &omap2_clksel_round_rate,
602 .set_rate = &omap2_clksel_set_rate,
603 .flags = CLOCK_IN_OMAP4430,
604};
605
606static struct clk dpll_core_m3_ck = {
607 .name = "dpll_core_m3_ck",
608 .parent = &dpll_core_ck,
609 .clksel = dpll_core_m6_div,
610 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
611 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
612 .ops = &clkops_null,
613 .recalc = &omap2_clksel_recalc,
614 .round_rate = &omap2_clksel_round_rate,
615 .set_rate = &omap2_clksel_set_rate,
616 .flags = CLOCK_IN_OMAP4430,
617};
618
619static struct clk dpll_core_m7_ck = {
620 .name = "dpll_core_m7_ck",
621 .parent = &dpll_core_ck,
622 .clksel = dpll_core_m6_div,
623 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
624 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
625 .ops = &clkops_null,
626 .recalc = &omap2_clksel_recalc,
627 .round_rate = &omap2_clksel_round_rate,
628 .set_rate = &omap2_clksel_set_rate,
629 .flags = CLOCK_IN_OMAP4430,
630};
631
632static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
633 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
634 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
635 { .parent = NULL },
636};
637
638static struct clk iva_hsd_byp_clk_mux_ck = {
639 .name = "iva_hsd_byp_clk_mux_ck",
640 .parent = &dpll_sys_ref_clk,
641 .ops = &clkops_null,
642 .recalc = &followparent_recalc,
643 .flags = CLOCK_IN_OMAP4430,
644};
645
646/* DPLL_IVA */
647static struct dpll_data dpll_iva_dd = {
648 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
649 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
650 .clk_ref = &dpll_sys_ref_clk,
651 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
652 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
653 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
654 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
655 .mult_mask = OMAP4430_DPLL_MULT_MASK,
656 .div1_mask = OMAP4430_DPLL_DIV_MASK,
657 .enable_mask = OMAP4430_DPLL_EN_MASK,
658 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
659 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
660 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
661 .max_divider = OMAP4430_MAX_DPLL_DIV,
662 .min_divider = 1,
663};
664
665
666static struct clk dpll_iva_ck = {
667 .name = "dpll_iva_ck",
668 .parent = &dpll_sys_ref_clk,
669 .dpll_data = &dpll_iva_dd,
911bd739 670 .init = &omap2_init_dpll_parent,
4751227d 671 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 672 .recalc = &omap3_dpll_recalc,
673 .round_rate = &omap2_dpll_round_rate,
674 .set_rate = &omap3_noncore_dpll_set_rate,
675 .flags = CLOCK_IN_OMAP4430,
676};
677
678static const struct clksel dpll_iva_m4_div[] = {
679 { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
680 { .parent = NULL },
681};
682
683static struct clk dpll_iva_m4_ck = {
684 .name = "dpll_iva_m4_ck",
685 .parent = &dpll_iva_ck,
686 .clksel = dpll_iva_m4_div,
687 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
688 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
689 .ops = &clkops_null,
690 .recalc = &omap2_clksel_recalc,
691 .round_rate = &omap2_clksel_round_rate,
692 .set_rate = &omap2_clksel_set_rate,
693 .flags = CLOCK_IN_OMAP4430,
694};
695
696static struct clk dpll_iva_m5_ck = {
697 .name = "dpll_iva_m5_ck",
698 .parent = &dpll_iva_ck,
699 .clksel = dpll_iva_m4_div,
700 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
701 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
702 .ops = &clkops_null,
703 .recalc = &omap2_clksel_recalc,
704 .round_rate = &omap2_clksel_round_rate,
705 .set_rate = &omap2_clksel_set_rate,
706 .flags = CLOCK_IN_OMAP4430,
707};
708
709/* DPLL_MPU */
710static struct dpll_data dpll_mpu_dd = {
711 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
712 .clk_bypass = &div_mpu_hs_clk,
713 .clk_ref = &dpll_sys_ref_clk,
714 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
715 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
716 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
717 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
718 .mult_mask = OMAP4430_DPLL_MULT_MASK,
719 .div1_mask = OMAP4430_DPLL_DIV_MASK,
720 .enable_mask = OMAP4430_DPLL_EN_MASK,
721 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
722 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
723 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
724 .max_divider = OMAP4430_MAX_DPLL_DIV,
725 .min_divider = 1,
726};
727
728
729static struct clk dpll_mpu_ck = {
730 .name = "dpll_mpu_ck",
731 .parent = &dpll_sys_ref_clk,
732 .dpll_data = &dpll_mpu_dd,
911bd739 733 .init = &omap2_init_dpll_parent,
4751227d 734 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 735 .recalc = &omap3_dpll_recalc,
736 .round_rate = &omap2_dpll_round_rate,
737 .set_rate = &omap3_noncore_dpll_set_rate,
738 .flags = CLOCK_IN_OMAP4430,
739};
740
741static const struct clksel dpll_mpu_m2_div[] = {
742 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
743 { .parent = NULL },
744};
745
746static struct clk dpll_mpu_m2_ck = {
747 .name = "dpll_mpu_m2_ck",
748 .parent = &dpll_mpu_ck,
749 .clksel = dpll_mpu_m2_div,
750 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
751 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
752 .ops = &clkops_null,
753 .recalc = &omap2_clksel_recalc,
754 .round_rate = &omap2_clksel_round_rate,
755 .set_rate = &omap2_clksel_set_rate,
756 .flags = CLOCK_IN_OMAP4430,
757};
758
759static struct clk per_hs_clk_div_ck = {
760 .name = "per_hs_clk_div_ck",
761 .parent = &dpll_abe_m3_ck,
762 .ops = &clkops_null,
763 .recalc = &followparent_recalc,
764 .flags = CLOCK_IN_OMAP4430,
765};
766
767static const struct clksel per_hsd_byp_clk_mux_sel[] = {
768 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
769 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
770 { .parent = NULL },
771};
772
773static struct clk per_hsd_byp_clk_mux_ck = {
774 .name = "per_hsd_byp_clk_mux_ck",
775 .parent = &dpll_sys_ref_clk,
776 .clksel = per_hsd_byp_clk_mux_sel,
777 .init = &omap2_init_clksel_parent,
778 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
779 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
780 .ops = &clkops_null,
781 .recalc = &omap2_clksel_recalc,
782 .flags = CLOCK_IN_OMAP4430,
783};
784
785/* DPLL_PER */
786static struct dpll_data dpll_per_dd = {
787 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
788 .clk_bypass = &per_hsd_byp_clk_mux_ck,
789 .clk_ref = &dpll_sys_ref_clk,
790 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
791 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
792 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
793 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
794 .mult_mask = OMAP4430_DPLL_MULT_MASK,
795 .div1_mask = OMAP4430_DPLL_DIV_MASK,
796 .enable_mask = OMAP4430_DPLL_EN_MASK,
797 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
798 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
799 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
800 .max_divider = OMAP4430_MAX_DPLL_DIV,
801 .min_divider = 1,
802};
803
804
805static struct clk dpll_per_ck = {
806 .name = "dpll_per_ck",
807 .parent = &dpll_sys_ref_clk,
808 .dpll_data = &dpll_per_dd,
911bd739 809 .init = &omap2_init_dpll_parent,
4751227d 810 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 811 .recalc = &omap3_dpll_recalc,
812 .round_rate = &omap2_dpll_round_rate,
813 .set_rate = &omap3_noncore_dpll_set_rate,
814 .flags = CLOCK_IN_OMAP4430,
815};
816
817static const struct clksel dpll_per_m2_div[] = {
818 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
819 { .parent = NULL },
820};
821
822static struct clk dpll_per_m2_ck = {
823 .name = "dpll_per_m2_ck",
824 .parent = &dpll_per_ck,
825 .clksel = dpll_per_m2_div,
826 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
827 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
828 .ops = &clkops_null,
829 .recalc = &omap2_clksel_recalc,
830 .round_rate = &omap2_clksel_round_rate,
831 .set_rate = &omap2_clksel_set_rate,
832 .flags = CLOCK_IN_OMAP4430,
833};
834
835static struct clk dpll_per_m2x2_ck = {
836 .name = "dpll_per_m2x2_ck",
837 .parent = &dpll_per_ck,
838 .ops = &clkops_null,
839 .recalc = &followparent_recalc,
840 .flags = CLOCK_IN_OMAP4430,
841};
842
843static struct clk dpll_per_m3_ck = {
844 .name = "dpll_per_m3_ck",
845 .parent = &dpll_per_ck,
846 .clksel = dpll_per_m2_div,
847 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
848 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
849 .ops = &clkops_null,
850 .recalc = &omap2_clksel_recalc,
851 .round_rate = &omap2_clksel_round_rate,
852 .set_rate = &omap2_clksel_set_rate,
853 .flags = CLOCK_IN_OMAP4430,
854};
855
856static struct clk dpll_per_m4_ck = {
857 .name = "dpll_per_m4_ck",
858 .parent = &dpll_per_ck,
859 .clksel = dpll_per_m2_div,
860 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
861 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
862 .ops = &clkops_null,
863 .recalc = &omap2_clksel_recalc,
864 .round_rate = &omap2_clksel_round_rate,
865 .set_rate = &omap2_clksel_set_rate,
866 .flags = CLOCK_IN_OMAP4430,
867};
868
869static struct clk dpll_per_m5_ck = {
870 .name = "dpll_per_m5_ck",
871 .parent = &dpll_per_ck,
872 .clksel = dpll_per_m2_div,
873 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
874 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
875 .ops = &clkops_null,
876 .recalc = &omap2_clksel_recalc,
877 .round_rate = &omap2_clksel_round_rate,
878 .set_rate = &omap2_clksel_set_rate,
879 .flags = CLOCK_IN_OMAP4430,
880};
881
882static struct clk dpll_per_m6_ck = {
883 .name = "dpll_per_m6_ck",
884 .parent = &dpll_per_ck,
885 .clksel = dpll_per_m2_div,
886 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
887 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
888 .ops = &clkops_null,
889 .recalc = &omap2_clksel_recalc,
890 .round_rate = &omap2_clksel_round_rate,
891 .set_rate = &omap2_clksel_set_rate,
892 .flags = CLOCK_IN_OMAP4430,
893};
894
895static struct clk dpll_per_m7_ck = {
896 .name = "dpll_per_m7_ck",
897 .parent = &dpll_per_ck,
898 .clksel = dpll_per_m2_div,
899 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
900 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
901 .ops = &clkops_null,
902 .recalc = &omap2_clksel_recalc,
903 .round_rate = &omap2_clksel_round_rate,
904 .set_rate = &omap2_clksel_set_rate,
905 .flags = CLOCK_IN_OMAP4430,
906};
907
908/* DPLL_UNIPRO */
909static struct dpll_data dpll_unipro_dd = {
910 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
911 .clk_bypass = &dpll_sys_ref_clk,
912 .clk_ref = &dpll_sys_ref_clk,
913 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
914 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
915 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
916 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
917 .mult_mask = OMAP4430_DPLL_MULT_MASK,
918 .div1_mask = OMAP4430_DPLL_DIV_MASK,
919 .enable_mask = OMAP4430_DPLL_EN_MASK,
920 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
921 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
922 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
923 .max_divider = OMAP4430_MAX_DPLL_DIV,
924 .min_divider = 1,
925};
926
927
928static struct clk dpll_unipro_ck = {
929 .name = "dpll_unipro_ck",
930 .parent = &dpll_sys_ref_clk,
931 .dpll_data = &dpll_unipro_dd,
911bd739 932 .init = &omap2_init_dpll_parent,
4751227d 933 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 934 .recalc = &omap3_dpll_recalc,
935 .round_rate = &omap2_dpll_round_rate,
936 .set_rate = &omap3_noncore_dpll_set_rate,
937 .flags = CLOCK_IN_OMAP4430,
938};
939
940static const struct clksel dpll_unipro_m2x2_div[] = {
941 { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
942 { .parent = NULL },
943};
944
945static struct clk dpll_unipro_m2x2_ck = {
946 .name = "dpll_unipro_m2x2_ck",
947 .parent = &dpll_unipro_ck,
948 .clksel = dpll_unipro_m2x2_div,
949 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
950 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
951 .ops = &clkops_null,
952 .recalc = &omap2_clksel_recalc,
953 .round_rate = &omap2_clksel_round_rate,
954 .set_rate = &omap2_clksel_set_rate,
955 .flags = CLOCK_IN_OMAP4430,
956};
957
958static struct clk usb_hs_clk_div_ck = {
959 .name = "usb_hs_clk_div_ck",
960 .parent = &dpll_abe_m3_ck,
961 .ops = &clkops_null,
962 .recalc = &followparent_recalc,
963 .flags = CLOCK_IN_OMAP4430,
964};
965
966/* DPLL_USB */
967static struct dpll_data dpll_usb_dd = {
968 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
969 .clk_bypass = &usb_hs_clk_div_ck,
970 .clk_ref = &dpll_sys_ref_clk,
971 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
972 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
973 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
974 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
975 .mult_mask = OMAP4430_DPLL_MULT_MASK,
976 .div1_mask = OMAP4430_DPLL_DIV_MASK,
977 .enable_mask = OMAP4430_DPLL_EN_MASK,
978 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
979 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
980 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
981 .max_divider = OMAP4430_MAX_DPLL_DIV,
982 .min_divider = 1,
358965d7 983 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL
972c5427
RN		 984};
985
986
987static struct clk dpll_usb_ck = {
988 .name = "dpll_usb_ck",
989 .parent = &dpll_sys_ref_clk,
990 .dpll_data = &dpll_usb_dd,
911bd739 991 .init = &omap2_init_dpll_parent,
4751227d 992 .ops = &omap4_clkops_noncore_dpll_ops,
972c5427
RN		 993 .recalc = &omap3_dpll_recalc,
994 .round_rate = &omap2_dpll_round_rate,
995 .set_rate = &omap3_noncore_dpll_set_rate,
996 .flags = CLOCK_IN_OMAP4430,
997};
998
999static struct clk dpll_usb_clkdcoldo_ck = {
1000 .name = "dpll_usb_clkdcoldo_ck",
1001 .parent = &dpll_usb_ck,
1002 .ops = &clkops_null,
1003 .recalc = &followparent_recalc,
1004 .flags = CLOCK_IN_OMAP4430,
1005};
1006
1007static const struct clksel dpll_usb_m2_div[] = {
1008 { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
1009 { .parent = NULL },
1010};
1011
1012static struct clk dpll_usb_m2_ck = {
1013 .name = "dpll_usb_m2_ck",
1014 .parent = &dpll_usb_ck,
1015 .clksel = dpll_usb_m2_div,
1016 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
1017 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1018 .ops = &clkops_null,
1019 .recalc = &omap2_clksel_recalc,
1020 .round_rate = &omap2_clksel_round_rate,
1021 .set_rate = &omap2_clksel_set_rate,
1022 .flags = CLOCK_IN_OMAP4430,
1023};
1024
1025static const struct clksel ducati_clk_mux_sel[] = {
1026 { .parent = &div_core_ck, .rates = div_1_0_rates },
1027 { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
1028 { .parent = NULL },
1029};
1030
1031static struct clk ducati_clk_mux_ck = {
1032 .name = "ducati_clk_mux_ck",
1033 .parent = &div_core_ck,
1034 .clksel = ducati_clk_mux_sel,
1035 .init = &omap2_init_clksel_parent,
1036 .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1037 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1038 .ops = &clkops_null,
1039 .recalc = &omap2_clksel_recalc,
1040 .flags = CLOCK_IN_OMAP4430,
1041};
1042
1043static struct clk func_12m_fclk = {
1044 .name = "func_12m_fclk",
1045 .parent = &dpll_per_m2x2_ck,
1046 .ops = &clkops_null,
1047 .recalc = &followparent_recalc,
1048 .flags = CLOCK_IN_OMAP4430,
1049};
1050
1051static struct clk func_24m_clk = {
1052 .name = "func_24m_clk",
1053 .parent = &dpll_per_m2_ck,
1054 .ops = &clkops_null,
1055 .recalc = &followparent_recalc,
1056 .flags = CLOCK_IN_OMAP4430,
1057};
1058
1059static struct clk func_24mc_fclk = {
1060 .name = "func_24mc_fclk",
1061 .parent = &dpll_per_m2x2_ck,
1062 .ops = &clkops_null,
1063 .recalc = &followparent_recalc,
1064 .flags = CLOCK_IN_OMAP4430,
1065};
1066
1067static const struct clksel_rate div2_4to8_rates[] = {
1068 { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1069 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1070 { .div = 0 },
1071};
1072
1073static const struct clksel func_48m_fclk_div[] = {
1074 { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1075 { .parent = NULL },
1076};
1077
1078static struct clk func_48m_fclk = {
1079 .name = "func_48m_fclk",
1080 .parent = &dpll_per_m2x2_ck,
1081 .clksel = func_48m_fclk_div,
1082 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1083 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1084 .ops = &clkops_null,
1085 .recalc = &omap2_clksel_recalc,
1086 .round_rate = &omap2_clksel_round_rate,
1087 .set_rate = &omap2_clksel_set_rate,
1088 .flags = CLOCK_IN_OMAP4430,
1089};
1090
1091static struct clk func_48mc_fclk = {
1092 .name = "func_48mc_fclk",
1093 .parent = &dpll_per_m2x2_ck,
1094 .ops = &clkops_null,
1095 .recalc = &followparent_recalc,
1096 .flags = CLOCK_IN_OMAP4430,
1097};
1098
1099static const struct clksel_rate div2_2to4_rates[] = {
1100 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1101 { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1102 { .div = 0 },
1103};
1104
1105static const struct clksel func_64m_fclk_div[] = {
1106 { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
1107 { .parent = NULL },
1108};
1109
1110static struct clk func_64m_fclk = {
1111 .name = "func_64m_fclk",
1112 .parent = &dpll_per_m4_ck,
1113 .clksel = func_64m_fclk_div,
1114 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1115 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1116 .ops = &clkops_null,
1117 .recalc = &omap2_clksel_recalc,
1118 .round_rate = &omap2_clksel_round_rate,
1119 .set_rate = &omap2_clksel_set_rate,
1120 .flags = CLOCK_IN_OMAP4430,
1121};
1122
1123static const struct clksel func_96m_fclk_div[] = {
1124 { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1125 { .parent = NULL },
1126};
1127
1128static struct clk func_96m_fclk = {
1129 .name = "func_96m_fclk",
1130 .parent = &dpll_per_m2x2_ck,
1131 .clksel = func_96m_fclk_div,
1132 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1133 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1134 .ops = &clkops_null,
1135 .recalc = &omap2_clksel_recalc,
1136 .round_rate = &omap2_clksel_round_rate,
1137 .set_rate = &omap2_clksel_set_rate,
1138 .flags = CLOCK_IN_OMAP4430,
1139};
1140
1141static const struct clksel hsmmc6_fclk_sel[] = {
1142 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1143 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1144 { .parent = NULL },
1145};
1146
1147static struct clk hsmmc6_fclk = {
1148 .name = "hsmmc6_fclk",
1149 .parent = &func_64m_fclk,
1150 .ops = &clkops_null,
1151 .recalc = &followparent_recalc,
1152 .flags = CLOCK_IN_OMAP4430,
1153};
1154
1155static const struct clksel_rate div2_1to8_rates[] = {
1156 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1157 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1158 { .div = 0 },
1159};
1160
1161static const struct clksel init_60m_fclk_div[] = {
1162 { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1163 { .parent = NULL },
1164};
1165
1166static struct clk init_60m_fclk = {
1167 .name = "init_60m_fclk",
1168 .parent = &dpll_usb_m2_ck,
1169 .clksel = init_60m_fclk_div,
1170 .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ,
1171 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1172 .ops = &clkops_null,
1173 .recalc = &omap2_clksel_recalc,
1174 .round_rate = &omap2_clksel_round_rate,
1175 .set_rate = &omap2_clksel_set_rate,
1176 .flags = CLOCK_IN_OMAP4430,
1177};
1178
1179static const struct clksel l3_div_div[] = {
1180 { .parent = &div_core_ck, .rates = div2_1to2_rates },
1181 { .parent = NULL },
1182};
1183
1184static struct clk l3_div_ck = {
1185 .name = "l3_div_ck",
1186 .parent = &div_core_ck,
1187 .clksel = l3_div_div,
1188 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1189 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
1190 .ops = &clkops_null,
1191 .recalc = &omap2_clksel_recalc,
1192 .round_rate = &omap2_clksel_round_rate,
1193 .set_rate = &omap2_clksel_set_rate,
1194 .flags = CLOCK_IN_OMAP4430,
1195};
1196
1197static const struct clksel l4_div_div[] = {
1198 { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1199 { .parent = NULL },
1200};
1201
1202static struct clk l4_div_ck = {
1203 .name = "l4_div_ck",
1204 .parent = &l3_div_ck,
1205 .clksel = l4_div_div,
1206 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1207 .clksel_mask = OMAP4430_CLKSEL_L4_MASK,
1208 .ops = &clkops_null,
1209 .recalc = &omap2_clksel_recalc,
1210 .round_rate = &omap2_clksel_round_rate,
1211 .set_rate = &omap2_clksel_set_rate,
1212 .flags = CLOCK_IN_OMAP4430,
1213};
1214
1215static struct clk lp_clk_div_ck = {
1216 .name = "lp_clk_div_ck",
1217 .parent = &dpll_abe_m2x2_ck,
1218 .ops = &clkops_null,
1219 .recalc = &followparent_recalc,
1220 .flags = CLOCK_IN_OMAP4430,
1221};
1222
1223static const struct clksel l4_wkup_clk_mux_sel[] = {
1224 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1225 { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1226 { .parent = NULL },
1227};
1228
1229static struct clk l4_wkup_clk_mux_ck = {
1230 .name = "l4_wkup_clk_mux_ck",
1231 .parent = &sys_clkin_ck,
1232 .clksel = l4_wkup_clk_mux_sel,
1233 .init = &omap2_init_clksel_parent,
1234 .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL,
1235 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1236 .ops = &clkops_null,
1237 .recalc = &omap2_clksel_recalc,
1238 .flags = CLOCK_IN_OMAP4430,
1239};
1240
1241static const struct clksel per_abe_nc_fclk_div[] = {
1242 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1243 { .parent = NULL },
1244};
1245
1246static struct clk per_abe_nc_fclk = {
1247 .name = "per_abe_nc_fclk",
1248 .parent = &dpll_abe_m2_ck,
1249 .clksel = per_abe_nc_fclk_div,
1250 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1251 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1252 .ops = &clkops_null,
1253 .recalc = &omap2_clksel_recalc,
1254 .round_rate = &omap2_clksel_round_rate,
1255 .set_rate = &omap2_clksel_set_rate,
1256 .flags = CLOCK_IN_OMAP4430,
1257};
1258
1259static const struct clksel mcasp2_fclk_sel[] = {
1260 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1261 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1262 { .parent = NULL },
1263};
1264
1265static struct clk mcasp2_fclk = {
1266 .name = "mcasp2_fclk",
1267 .parent = &func_96m_fclk,
1268 .ops = &clkops_null,
1269 .recalc = &followparent_recalc,
1270 .flags = CLOCK_IN_OMAP4430,
1271};
1272
1273static struct clk mcasp3_fclk = {
1274 .name = "mcasp3_fclk",
1275 .parent = &func_96m_fclk,
1276 .ops = &clkops_null,
1277 .recalc = &followparent_recalc,
1278 .flags = CLOCK_IN_OMAP4430,
1279};
1280
1281static struct clk ocp_abe_iclk = {
1282 .name = "ocp_abe_iclk",
1283 .parent = &aess_fclk,
1284 .ops = &clkops_null,
1285 .recalc = &followparent_recalc,
1286 .flags = CLOCK_IN_OMAP4430,
1287};
1288
1289static struct clk per_abe_24m_fclk = {
1290 .name = "per_abe_24m_fclk",
1291 .parent = &dpll_abe_m2_ck,
1292 .ops = &clkops_null,
1293 .recalc = &followparent_recalc,
1294 .flags = CLOCK_IN_OMAP4430,
1295};
1296
1297static const struct clksel pmd_stm_clock_mux_sel[] = {
1298 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1299 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
1300 { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates },
1301 { .parent = NULL },
1302};
1303
1304static struct clk pmd_stm_clock_mux_ck = {
1305 .name = "pmd_stm_clock_mux_ck",
1306 .parent = &sys_clkin_ck,
1307 .ops = &clkops_null,
1308 .recalc = &followparent_recalc,
1309 .flags = CLOCK_IN_OMAP4430,
1310};
1311
1312static struct clk pmd_trace_clk_mux_ck = {
1313 .name = "pmd_trace_clk_mux_ck",
1314 .parent = &sys_clkin_ck,
1315 .ops = &clkops_null,
1316 .recalc = &followparent_recalc,
1317 .flags = CLOCK_IN_OMAP4430,
1318};
1319
1320static struct clk syc_clk_div_ck = {
1321 .name = "syc_clk_div_ck",
1322 .parent = &sys_clkin_ck,
1323 .clksel = dpll_sys_ref_clk_div,
1324 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1325 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1326 .ops = &clkops_null,
1327 .recalc = &omap2_clksel_recalc,
1328 .round_rate = &omap2_clksel_round_rate,
1329 .set_rate = &omap2_clksel_set_rate,
1330 .flags = CLOCK_IN_OMAP4430,
1331};
1332
1333/* Leaf clocks controlled by modules */
1334
1335static struct clk aes1_ck = {
1336 .name = "aes1_ck",
1337 .ops = &clkops_omap2_dflt,
1338 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1339 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1340 .clkdm_name = "l4_secure_clkdm",
1341 .parent = &l3_div_ck,
1342 .recalc = &followparent_recalc,
1343};
1344
1345static struct clk aes2_ck = {
1346 .name = "aes2_ck",
1347 .ops = &clkops_omap2_dflt,
1348 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1349 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1350 .clkdm_name = "l4_secure_clkdm",
1351 .parent = &l3_div_ck,
1352 .recalc = &followparent_recalc,
1353};
1354
1355static struct clk aess_ck = {
1356 .name = "aess_ck",
1357 .ops = &clkops_omap2_dflt,
1358 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1359 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1360 .clkdm_name = "abe_clkdm",
1361 .parent = &aess_fclk,
1362 .recalc = &followparent_recalc,
1363};
1364
1365static struct clk cust_efuse_ck = {
1366 .name = "cust_efuse_ck",
1367 .ops = &clkops_omap2_dflt,
1368 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1369 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1370 .clkdm_name = "l4_cefuse_clkdm",
1371 .parent = &sys_clkin_ck,
1372 .recalc = &followparent_recalc,
1373};
1374
1375static struct clk des3des_ck = {
1376 .name = "des3des_ck",
1377 .ops = &clkops_omap2_dflt,
1378 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1379 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1380 .clkdm_name = "l4_secure_clkdm",
1381 .parent = &l4_div_ck,
1382 .recalc = &followparent_recalc,
1383};
1384
1385static const struct clksel dmic_sync_mux_sel[] = {
1386 { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1387 { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1388 { .parent = &func_24m_clk, .rates = div_1_2_rates },
1389 { .parent = NULL },
1390};
1391
1392static struct clk dmic_sync_mux_ck = {
1393 .name = "dmic_sync_mux_ck",
1394 .parent = &abe_24m_fclk,
1395 .clksel = dmic_sync_mux_sel,
1396 .init = &omap2_init_clksel_parent,
1397 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1398 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1399 .ops = &clkops_null,
1400 .recalc = &omap2_clksel_recalc,
1401 .flags = CLOCK_IN_OMAP4430,
1402};
1403
1404static const struct clksel func_dmic_abe_gfclk_sel[] = {
1405 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1406 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1407 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1408 { .parent = NULL },
1409};
1410
1411/* Merged func_dmic_abe_gfclk into dmic_ck */
1412static struct clk dmic_ck = {
1413 .name = "dmic_ck",
1414 .parent = &dmic_sync_mux_ck,
1415 .clksel = func_dmic_abe_gfclk_sel,
1416 .init = &omap2_init_clksel_parent,
1417 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1418 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1419 .ops = &clkops_omap2_dflt,
1420 .recalc = &omap2_clksel_recalc,
1421 .flags = CLOCK_IN_OMAP4430,
1422 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1423 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1424 .clkdm_name = "abe_clkdm",
1425};
1426
1427static struct clk dss_ck = {
1428 .name = "dss_ck",
1429 .ops = &clkops_omap2_dflt,
1430 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1431 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1432 .clkdm_name = "l3_dss_clkdm",
1433 .parent = &l3_div_ck,
1434 .recalc = &followparent_recalc,
1435};
1436
1437static struct clk ducati_ck = {
1438 .name = "ducati_ck",
1439 .ops = &clkops_omap2_dflt,
1440 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1441 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1442 .clkdm_name = "ducati_clkdm",
1443 .parent = &ducati_clk_mux_ck,
1444 .recalc = &followparent_recalc,
1445};
1446
1447static struct clk emif1_ck = {
1448 .name = "emif1_ck",
1449 .ops = &clkops_omap2_dflt,
1450 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1451 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1452 .clkdm_name = "l3_emif_clkdm",
1453 .parent = &ddrphy_ck,
1454 .recalc = &followparent_recalc,
1455};
1456
1457static struct clk emif2_ck = {
1458 .name = "emif2_ck",
1459 .ops = &clkops_omap2_dflt,
1460 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1461 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1462 .clkdm_name = "l3_emif_clkdm",
1463 .parent = &ddrphy_ck,
1464 .recalc = &followparent_recalc,
1465};
1466
1467static const struct clksel fdif_fclk_div[] = {
1468 { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
1469 { .parent = NULL },
1470};
1471
1472/* Merged fdif_fclk into fdif_ck */
1473static struct clk fdif_ck = {
1474 .name = "fdif_ck",
1475 .parent = &dpll_per_m4_ck,
1476 .clksel = fdif_fclk_div,
1477 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1478 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
1479 .ops = &clkops_omap2_dflt,
1480 .recalc = &omap2_clksel_recalc,
1481 .round_rate = &omap2_clksel_round_rate,
1482 .set_rate = &omap2_clksel_set_rate,
1483 .flags = CLOCK_IN_OMAP4430,
1484 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1485 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1486 .clkdm_name = "iss_clkdm",
1487};
1488
1489static const struct clksel per_sgx_fclk_div[] = {
1490 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1491 { .parent = NULL },
1492};
1493
1494static struct clk per_sgx_fclk = {
1495 .name = "per_sgx_fclk",
1496 .parent = &dpll_per_m2x2_ck,
1497 .clksel = per_sgx_fclk_div,
1498 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1499 .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK,
1500 .ops = &clkops_null,
1501 .recalc = &omap2_clksel_recalc,
1502 .round_rate = &omap2_clksel_round_rate,
1503 .set_rate = &omap2_clksel_set_rate,
1504 .flags = CLOCK_IN_OMAP4430,
1505};
1506
1507static const struct clksel sgx_clk_mux_sel[] = {
1508 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1509 { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
1510 { .parent = NULL },
1511};
1512
1513/* Merged sgx_clk_mux into gfx_ck */
1514static struct clk gfx_ck = {
1515 .name = "gfx_ck",
1516 .parent = &dpll_core_m7_ck,
1517 .clksel = sgx_clk_mux_sel,
1518 .init = &omap2_init_clksel_parent,
1519 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1520 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1521 .ops = &clkops_omap2_dflt,
1522 .recalc = &omap2_clksel_recalc,
1523 .flags = CLOCK_IN_OMAP4430,
1524 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1525 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1526 .clkdm_name = "l3_gfx_clkdm",
1527};
1528
1529static struct clk gpio1_ck = {
1530 .name = "gpio1_ck",
1531 .ops = &clkops_omap2_dflt,
1532 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1533 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1534 .clkdm_name = "l4_wkup_clkdm",
1535 .parent = &l4_wkup_clk_mux_ck,
1536 .recalc = &followparent_recalc,
1537};
1538
1539static struct clk gpio2_ck = {
1540 .name = "gpio2_ck",
1541 .ops = &clkops_omap2_dflt,
1542 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1543 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1544 .clkdm_name = "l4_per_clkdm",
1545 .parent = &l4_div_ck,
1546 .recalc = &followparent_recalc,
1547};
1548
1549static struct clk gpio3_ck = {
1550 .name = "gpio3_ck",
1551 .ops = &clkops_omap2_dflt,
1552 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1553 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1554 .clkdm_name = "l4_per_clkdm",
1555 .parent = &l4_div_ck,
1556 .recalc = &followparent_recalc,
1557};
1558
1559static struct clk gpio4_ck = {
1560 .name = "gpio4_ck",
1561 .ops = &clkops_omap2_dflt,
1562 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1563 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1564 .clkdm_name = "l4_per_clkdm",
1565 .parent = &l4_div_ck,
1566 .recalc = &followparent_recalc,
1567};
1568
1569static struct clk gpio5_ck = {
1570 .name = "gpio5_ck",
1571 .ops = &clkops_omap2_dflt,
1572 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1573 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1574 .clkdm_name = "l4_per_clkdm",
1575 .parent = &l4_div_ck,
1576 .recalc = &followparent_recalc,
1577};
1578
1579static struct clk gpio6_ck = {
1580 .name = "gpio6_ck",
1581 .ops = &clkops_omap2_dflt,
1582 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1583 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1584 .clkdm_name = "l4_per_clkdm",
1585 .parent = &l4_div_ck,
1586 .recalc = &followparent_recalc,
1587};
1588
1589static struct clk gpmc_ck = {
1590 .name = "gpmc_ck",
1591 .ops = &clkops_omap2_dflt,
1592 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1593 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1594 .clkdm_name = "l3_2_clkdm",
1595 .parent = &l3_div_ck,
1596 .recalc = &followparent_recalc,
1597};
1598
1599static const struct clksel dmt1_clk_mux_sel[] = {
1600 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1601 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1602 { .parent = NULL },
1603};
1604
1605/* Merged dmt1_clk_mux into gptimer1_ck */
1606static struct clk gptimer1_ck = {
1607 .name = "gptimer1_ck",
1608 .parent = &sys_clkin_ck,
1609 .clksel = dmt1_clk_mux_sel,
1610 .init = &omap2_init_clksel_parent,
1611 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1612 .clksel_mask = OMAP4430_CLKSEL_MASK,
1613 .ops = &clkops_omap2_dflt,
1614 .recalc = &omap2_clksel_recalc,
1615 .flags = CLOCK_IN_OMAP4430,
1616 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1617 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1618 .clkdm_name = "l4_wkup_clkdm",
1619};
1620
1621/* Merged cm2_dm10_mux into gptimer10_ck */
1622static struct clk gptimer10_ck = {
1623 .name = "gptimer10_ck",
1624 .parent = &sys_clkin_ck,
1625 .clksel = dmt1_clk_mux_sel,
1626 .init = &omap2_init_clksel_parent,
1627 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1628 .clksel_mask = OMAP4430_CLKSEL_MASK,
1629 .ops = &clkops_omap2_dflt,
1630 .recalc = &omap2_clksel_recalc,
1631 .flags = CLOCK_IN_OMAP4430,
1632 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1633 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1634 .clkdm_name = "l4_per_clkdm",
1635};
1636
1637/* Merged cm2_dm11_mux into gptimer11_ck */
1638static struct clk gptimer11_ck = {
1639 .name = "gptimer11_ck",
1640 .parent = &sys_clkin_ck,
1641 .clksel = dmt1_clk_mux_sel,
1642 .init = &omap2_init_clksel_parent,
1643 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1644 .clksel_mask = OMAP4430_CLKSEL_MASK,
1645 .ops = &clkops_omap2_dflt,
1646 .recalc = &omap2_clksel_recalc,
1647 .flags = CLOCK_IN_OMAP4430,
1648 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1649 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1650 .clkdm_name = "l4_per_clkdm",
1651};
1652
1653/* Merged cm2_dm2_mux into gptimer2_ck */
1654static struct clk gptimer2_ck = {
1655 .name = "gptimer2_ck",
1656 .parent = &sys_clkin_ck,
1657 .clksel = dmt1_clk_mux_sel,
1658 .init = &omap2_init_clksel_parent,
1659 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1660 .clksel_mask = OMAP4430_CLKSEL_MASK,
1661 .ops = &clkops_omap2_dflt,
1662 .recalc = &omap2_clksel_recalc,
1663 .flags = CLOCK_IN_OMAP4430,
1664 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1665 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1666 .clkdm_name = "l4_per_clkdm",
1667};
1668
1669/* Merged cm2_dm3_mux into gptimer3_ck */
1670static struct clk gptimer3_ck = {
1671 .name = "gptimer3_ck",
1672 .parent = &sys_clkin_ck,
1673 .clksel = dmt1_clk_mux_sel,
1674 .init = &omap2_init_clksel_parent,
1675 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1676 .clksel_mask = OMAP4430_CLKSEL_MASK,
1677 .ops = &clkops_omap2_dflt,
1678 .recalc = &omap2_clksel_recalc,
1679 .flags = CLOCK_IN_OMAP4430,
1680 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1681 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1682 .clkdm_name = "l4_per_clkdm",
1683};
1684
1685/* Merged cm2_dm4_mux into gptimer4_ck */
1686static struct clk gptimer4_ck = {
1687 .name = "gptimer4_ck",
1688 .parent = &sys_clkin_ck,
1689 .clksel = dmt1_clk_mux_sel,
1690 .init = &omap2_init_clksel_parent,
1691 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1692 .clksel_mask = OMAP4430_CLKSEL_MASK,
1693 .ops = &clkops_omap2_dflt,
1694 .recalc = &omap2_clksel_recalc,
1695 .flags = CLOCK_IN_OMAP4430,
1696 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1697 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1698 .clkdm_name = "l4_per_clkdm",
1699};
1700
1701static const struct clksel timer5_sync_mux_sel[] = {
1702 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1703 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1704 { .parent = NULL },
1705};
1706
1707/* Merged timer5_sync_mux into gptimer5_ck */
1708static struct clk gptimer5_ck = {
1709 .name = "gptimer5_ck",
1710 .parent = &syc_clk_div_ck,
1711 .clksel = timer5_sync_mux_sel,
1712 .init = &omap2_init_clksel_parent,
1713 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1714 .clksel_mask = OMAP4430_CLKSEL_MASK,
1715 .ops = &clkops_omap2_dflt,
1716 .recalc = &omap2_clksel_recalc,
1717 .flags = CLOCK_IN_OMAP4430,
1718 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1719 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1720 .clkdm_name = "abe_clkdm",
1721};
1722
1723/* Merged timer6_sync_mux into gptimer6_ck */
1724static struct clk gptimer6_ck = {
1725 .name = "gptimer6_ck",
1726 .parent = &syc_clk_div_ck,
1727 .clksel = timer5_sync_mux_sel,
1728 .init = &omap2_init_clksel_parent,
1729 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1730 .clksel_mask = OMAP4430_CLKSEL_MASK,
1731 .ops = &clkops_omap2_dflt,
1732 .recalc = &omap2_clksel_recalc,
1733 .flags = CLOCK_IN_OMAP4430,
1734 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1735 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1736 .clkdm_name = "abe_clkdm",
1737};
1738
1739/* Merged timer7_sync_mux into gptimer7_ck */
1740static struct clk gptimer7_ck = {
1741 .name = "gptimer7_ck",
1742 .parent = &syc_clk_div_ck,
1743 .clksel = timer5_sync_mux_sel,
1744 .init = &omap2_init_clksel_parent,
1745 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1746 .clksel_mask = OMAP4430_CLKSEL_MASK,
1747 .ops = &clkops_omap2_dflt,
1748 .recalc = &omap2_clksel_recalc,
1749 .flags = CLOCK_IN_OMAP4430,
1750 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1751 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1752 .clkdm_name = "abe_clkdm",
1753};
1754
1755/* Merged timer8_sync_mux into gptimer8_ck */
1756static struct clk gptimer8_ck = {
1757 .name = "gptimer8_ck",
1758 .parent = &syc_clk_div_ck,
1759 .clksel = timer5_sync_mux_sel,
1760 .init = &omap2_init_clksel_parent,
1761 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1762 .clksel_mask = OMAP4430_CLKSEL_MASK,
1763 .ops = &clkops_omap2_dflt,
1764 .recalc = &omap2_clksel_recalc,
1765 .flags = CLOCK_IN_OMAP4430,
1766 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1767 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1768 .clkdm_name = "abe_clkdm",
1769};
1770
1771/* Merged cm2_dm9_mux into gptimer9_ck */
1772static struct clk gptimer9_ck = {
1773 .name = "gptimer9_ck",
1774 .parent = &sys_clkin_ck,
1775 .clksel = dmt1_clk_mux_sel,
1776 .init = &omap2_init_clksel_parent,
1777 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1778 .clksel_mask = OMAP4430_CLKSEL_MASK,
1779 .ops = &clkops_omap2_dflt,
1780 .recalc = &omap2_clksel_recalc,
1781 .flags = CLOCK_IN_OMAP4430,
1782 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1783 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1784 .clkdm_name = "l4_per_clkdm",
1785};
1786
1787static struct clk hdq1w_ck = {
1788 .name = "hdq1w_ck",
1789 .ops = &clkops_omap2_dflt,
1790 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1791 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1792 .clkdm_name = "l4_per_clkdm",
1793 .parent = &func_12m_fclk,
1794 .recalc = &followparent_recalc,
1795};
1796
1797/* Merged hsi_fclk into hsi_ck */
1798static struct clk hsi_ck = {
1799 .name = "hsi_ck",
1800 .parent = &dpll_per_m2x2_ck,
1801 .clksel = per_sgx_fclk_div,
1802 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1803 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1804 .ops = &clkops_omap2_dflt,
1805 .recalc = &omap2_clksel_recalc,
1806 .round_rate = &omap2_clksel_round_rate,
1807 .set_rate = &omap2_clksel_set_rate,
1808 .flags = CLOCK_IN_OMAP4430,
1809 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1810 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1811 .clkdm_name = "l3_init_clkdm",
1812};
1813
1814static struct clk i2c1_ck = {
1815 .name = "i2c1_ck",
1816 .ops = &clkops_omap2_dflt,
1817 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1818 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1819 .clkdm_name = "l4_per_clkdm",
1820 .parent = &func_96m_fclk,
1821 .recalc = &followparent_recalc,
1822};
1823
1824static struct clk i2c2_ck = {
1825 .name = "i2c2_ck",
1826 .ops = &clkops_omap2_dflt,
1827 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1828 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1829 .clkdm_name = "l4_per_clkdm",
1830 .parent = &func_96m_fclk,
1831 .recalc = &followparent_recalc,
1832};
1833
1834static struct clk i2c3_ck = {
1835 .name = "i2c3_ck",
1836 .ops = &clkops_omap2_dflt,
1837 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1838 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1839 .clkdm_name = "l4_per_clkdm",
1840 .parent = &func_96m_fclk,
1841 .recalc = &followparent_recalc,
1842};
1843
1844static struct clk i2c4_ck = {
1845 .name = "i2c4_ck",
1846 .ops = &clkops_omap2_dflt,
1847 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1848 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1849 .clkdm_name = "l4_per_clkdm",
1850 .parent = &func_96m_fclk,
1851 .recalc = &followparent_recalc,
1852};
1853
1854static struct clk iss_ck = {
1855 .name = "iss_ck",
1856 .ops = &clkops_omap2_dflt,
1857 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1858 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1859 .clkdm_name = "iss_clkdm",
1860 .parent = &ducati_clk_mux_ck,
1861 .recalc = &followparent_recalc,
1862};
1863
1864static struct clk ivahd_ck = {
1865 .name = "ivahd_ck",
1866 .ops = &clkops_omap2_dflt,
1867 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1868 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1869 .clkdm_name = "ivahd_clkdm",
1870 .parent = &dpll_iva_m5_ck,
1871 .recalc = &followparent_recalc,
1872};
1873
1874static struct clk keyboard_ck = {
1875 .name = "keyboard_ck",
1876 .ops = &clkops_omap2_dflt,
1877 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1878 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1879 .clkdm_name = "l4_wkup_clkdm",
1880 .parent = &sys_32k_ck,
1881 .recalc = &followparent_recalc,
1882};
1883
1884static struct clk l3_instr_interconnect_ck = {
1885 .name = "l3_instr_interconnect_ck",
1886 .ops = &clkops_omap2_dflt,
1887 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1888 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1889 .clkdm_name = "l3_instr_clkdm",
1890 .parent = &l3_div_ck,
1891 .recalc = &followparent_recalc,
1892};
1893
1894static struct clk l3_interconnect_3_ck = {
1895 .name = "l3_interconnect_3_ck",
1896 .ops = &clkops_omap2_dflt,
1897 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1898 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1899 .clkdm_name = "l3_instr_clkdm",
1900 .parent = &l3_div_ck,
1901 .recalc = &followparent_recalc,
1902};
1903
1904static struct clk mcasp_sync_mux_ck = {
1905 .name = "mcasp_sync_mux_ck",
1906 .parent = &abe_24m_fclk,
1907 .clksel = dmic_sync_mux_sel,
1908 .init = &omap2_init_clksel_parent,
1909 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1910 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1911 .ops = &clkops_null,
1912 .recalc = &omap2_clksel_recalc,
1913 .flags = CLOCK_IN_OMAP4430,
1914};
1915
1916static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1917 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1918 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1919 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1920 { .parent = NULL },
1921};
1922
1923/* Merged func_mcasp_abe_gfclk into mcasp_ck */
1924static struct clk mcasp_ck = {
1925 .name = "mcasp_ck",
1926 .parent = &mcasp_sync_mux_ck,
1927 .clksel = func_mcasp_abe_gfclk_sel,
1928 .init = &omap2_init_clksel_parent,
1929 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1930 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1931 .ops = &clkops_omap2_dflt,
1932 .recalc = &omap2_clksel_recalc,
1933 .flags = CLOCK_IN_OMAP4430,
1934 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1935 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1936 .clkdm_name = "abe_clkdm",
1937};
1938
1939static struct clk mcbsp1_sync_mux_ck = {
1940 .name = "mcbsp1_sync_mux_ck",
1941 .parent = &abe_24m_fclk,
1942 .clksel = dmic_sync_mux_sel,
1943 .init = &omap2_init_clksel_parent,
1944 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1945 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1946 .ops = &clkops_null,
1947 .recalc = &omap2_clksel_recalc,
1948 .flags = CLOCK_IN_OMAP4430,
1949};
1950
1951static const struct clksel func_mcbsp1_gfclk_sel[] = {
1952 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1953 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1954 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1955 { .parent = NULL },
1956};
1957
1958/* Merged func_mcbsp1_gfclk into mcbsp1_ck */
1959static struct clk mcbsp1_ck = {
1960 .name = "mcbsp1_ck",
1961 .parent = &mcbsp1_sync_mux_ck,
1962 .clksel = func_mcbsp1_gfclk_sel,
1963 .init = &omap2_init_clksel_parent,
1964 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1965 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1966 .ops = &clkops_omap2_dflt,
1967 .recalc = &omap2_clksel_recalc,
1968 .flags = CLOCK_IN_OMAP4430,
1969 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1970 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1971 .clkdm_name = "abe_clkdm",
1972};
1973
1974static struct clk mcbsp2_sync_mux_ck = {
1975 .name = "mcbsp2_sync_mux_ck",
1976 .parent = &abe_24m_fclk,
1977 .clksel = dmic_sync_mux_sel,
1978 .init = &omap2_init_clksel_parent,
1979 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1980 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1981 .ops = &clkops_null,
1982 .recalc = &omap2_clksel_recalc,
1983 .flags = CLOCK_IN_OMAP4430,
1984};
1985
1986static const struct clksel func_mcbsp2_gfclk_sel[] = {
1987 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1988 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1989 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1990 { .parent = NULL },
1991};
1992
1993/* Merged func_mcbsp2_gfclk into mcbsp2_ck */
1994static struct clk mcbsp2_ck = {
1995 .name = "mcbsp2_ck",
1996 .parent = &mcbsp2_sync_mux_ck,
1997 .clksel = func_mcbsp2_gfclk_sel,
1998 .init = &omap2_init_clksel_parent,
1999 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2000 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
2001 .ops = &clkops_omap2_dflt,
2002 .recalc = &omap2_clksel_recalc,
2003 .flags = CLOCK_IN_OMAP4430,
2004 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2005 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2006 .clkdm_name = "abe_clkdm",
2007};
2008
2009static struct clk mcbsp3_sync_mux_ck = {
2010 .name = "mcbsp3_sync_mux_ck",
2011 .parent = &abe_24m_fclk,
2012 .clksel = dmic_sync_mux_sel,
2013 .init = &omap2_init_clksel_parent,
2014 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2015 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
2016 .ops = &clkops_null,
2017 .recalc = &omap2_clksel_recalc,
2018 .flags = CLOCK_IN_OMAP4430,
2019};
2020
2021static const struct clksel func_mcbsp3_gfclk_sel[] = {
2022 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
2023 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
2024 { .parent = &slimbus_clk, .rates = div_1_2_rates },
2025 { .parent = NULL },
2026};
2027
2028/* Merged func_mcbsp3_gfclk into mcbsp3_ck */
2029static struct clk mcbsp3_ck = {
2030 .name = "mcbsp3_ck",
2031 .parent = &mcbsp3_sync_mux_ck,
2032 .clksel = func_mcbsp3_gfclk_sel,
2033 .init = &omap2_init_clksel_parent,
2034 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2035 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
2036 .ops = &clkops_omap2_dflt,
2037 .recalc = &omap2_clksel_recalc,
2038 .flags = CLOCK_IN_OMAP4430,
2039 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2040 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2041 .clkdm_name = "abe_clkdm",
2042};
2043
2044static struct clk mcbsp4_sync_mux_ck = {
2045 .name = "mcbsp4_sync_mux_ck",
2046 .parent = &func_96m_fclk,
2047 .clksel = mcasp2_fclk_sel,
2048 .init = &omap2_init_clksel_parent,
2049 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2050 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
2051 .ops = &clkops_null,
2052 .recalc = &omap2_clksel_recalc,
2053 .flags = CLOCK_IN_OMAP4430,
2054};
2055
2056static const struct clksel per_mcbsp4_gfclk_sel[] = {
2057 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
2058 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
2059 { .parent = NULL },
2060};
2061
2062/* Merged per_mcbsp4_gfclk into mcbsp4_ck */
2063static struct clk mcbsp4_ck = {
2064 .name = "mcbsp4_ck",
2065 .parent = &mcbsp4_sync_mux_ck,
2066 .clksel = per_mcbsp4_gfclk_sel,
2067 .init = &omap2_init_clksel_parent,
2068 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2069 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2070 .ops = &clkops_omap2_dflt,
2071 .recalc = &omap2_clksel_recalc,
2072 .flags = CLOCK_IN_OMAP4430,
2073 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2074 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2075 .clkdm_name = "l4_per_clkdm",
2076};
2077
2078static struct clk mcspi1_ck = {
2079 .name = "mcspi1_ck",
2080 .ops = &clkops_omap2_dflt,
2081 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2082 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2083 .clkdm_name = "l4_per_clkdm",
2084 .parent = &func_48m_fclk,
2085 .recalc = &followparent_recalc,
2086};
2087
2088static struct clk mcspi2_ck = {
2089 .name = "mcspi2_ck",
2090 .ops = &clkops_omap2_dflt,
2091 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2092 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2093 .clkdm_name = "l4_per_clkdm",
2094 .parent = &func_48m_fclk,
2095 .recalc = &followparent_recalc,
2096};
2097
2098static struct clk mcspi3_ck = {
2099 .name = "mcspi3_ck",
2100 .ops = &clkops_omap2_dflt,
2101 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2102 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2103 .clkdm_name = "l4_per_clkdm",
2104 .parent = &func_48m_fclk,
2105 .recalc = &followparent_recalc,
2106};
2107
2108static struct clk mcspi4_ck = {
2109 .name = "mcspi4_ck",
2110 .ops = &clkops_omap2_dflt,
2111 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2112 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2113 .clkdm_name = "l4_per_clkdm",
2114 .parent = &func_48m_fclk,
2115 .recalc = &followparent_recalc,
2116};
2117
2118/* Merged hsmmc1_fclk into mmc1_ck */
2119static struct clk mmc1_ck = {
2120 .name = "mmc1_ck",
2121 .parent = &func_64m_fclk,
2122 .clksel = hsmmc6_fclk_sel,
2123 .init = &omap2_init_clksel_parent,
2124 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2125 .clksel_mask = OMAP4430_CLKSEL_MASK,
2126 .ops = &clkops_omap2_dflt,
2127 .recalc = &omap2_clksel_recalc,
2128 .flags = CLOCK_IN_OMAP4430,
2129 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2130 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2131 .clkdm_name = "l3_init_clkdm",
2132};
2133
2134/* Merged hsmmc2_fclk into mmc2_ck */
2135static struct clk mmc2_ck = {
2136 .name = "mmc2_ck",
2137 .parent = &func_64m_fclk,
2138 .clksel = hsmmc6_fclk_sel,
2139 .init = &omap2_init_clksel_parent,
2140 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2141 .clksel_mask = OMAP4430_CLKSEL_MASK,
2142 .ops = &clkops_omap2_dflt,
2143 .recalc = &omap2_clksel_recalc,
2144 .flags = CLOCK_IN_OMAP4430,
2145 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2146 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2147 .clkdm_name = "l3_init_clkdm",
2148};
2149
2150static struct clk mmc3_ck = {
2151 .name = "mmc3_ck",
2152 .ops = &clkops_omap2_dflt,
2153 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2154 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2155 .clkdm_name = "l4_per_clkdm",
2156 .parent = &func_48m_fclk,
2157 .recalc = &followparent_recalc,
2158};
2159
2160static struct clk mmc4_ck = {
2161 .name = "mmc4_ck",
2162 .ops = &clkops_omap2_dflt,
2163 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2164 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2165 .clkdm_name = "l4_per_clkdm",
2166 .parent = &func_48m_fclk,
2167 .recalc = &followparent_recalc,
2168};
2169
2170static struct clk mmc5_ck = {
2171 .name = "mmc5_ck",
2172 .ops = &clkops_omap2_dflt,
2173 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2174 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2175 .clkdm_name = "l4_per_clkdm",
2176 .parent = &func_48m_fclk,
2177 .recalc = &followparent_recalc,
2178};
2179
2180static struct clk ocp_wp1_ck = {
2181 .name = "ocp_wp1_ck",
2182 .ops = &clkops_omap2_dflt,
2183 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2184 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2185 .clkdm_name = "l3_instr_clkdm",
2186 .parent = &l3_div_ck,
2187 .recalc = &followparent_recalc,
2188};
2189
2190static struct clk pdm_ck = {
2191 .name = "pdm_ck",
2192 .ops = &clkops_omap2_dflt,
2193 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2194 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2195 .clkdm_name = "abe_clkdm",
2196 .parent = &pad_clks_ck,
2197 .recalc = &followparent_recalc,
2198};
2199
2200static struct clk pkaeip29_ck = {
2201 .name = "pkaeip29_ck",
2202 .ops = &clkops_omap2_dflt,
2203 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
2204 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2205 .clkdm_name = "l4_secure_clkdm",
2206 .parent = &l4_div_ck,
2207 .recalc = &followparent_recalc,
2208};
2209
2210static struct clk rng_ck = {
2211 .name = "rng_ck",
2212 .ops = &clkops_omap2_dflt,
2213 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2214 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2215 .clkdm_name = "l4_secure_clkdm",
2216 .parent = &l4_div_ck,
2217 .recalc = &followparent_recalc,
2218};
2219
2220static struct clk sha2md51_ck = {
2221 .name = "sha2md51_ck",
2222 .ops = &clkops_omap2_dflt,
2223 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2224 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2225 .clkdm_name = "l4_secure_clkdm",
2226 .parent = &l3_div_ck,
2227 .recalc = &followparent_recalc,
2228};
2229
2230static struct clk sl2_ck = {
2231 .name = "sl2_ck",
2232 .ops = &clkops_omap2_dflt,
2233 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2234 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2235 .clkdm_name = "ivahd_clkdm",
2236 .parent = &dpll_iva_m5_ck,
2237 .recalc = &followparent_recalc,
2238};
2239
2240static struct clk slimbus1_ck = {
2241 .name = "slimbus1_ck",
2242 .ops = &clkops_omap2_dflt,
2243 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2244 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2245 .clkdm_name = "abe_clkdm",
2246 .parent = &ocp_abe_iclk,
2247 .recalc = &followparent_recalc,
2248};
2249
2250static struct clk slimbus2_ck = {
2251 .name = "slimbus2_ck",
2252 .ops = &clkops_omap2_dflt,
2253 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2254 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2255 .clkdm_name = "l4_per_clkdm",
2256 .parent = &l4_div_ck,
2257 .recalc = &followparent_recalc,
2258};
2259
2260static struct clk sr_core_ck = {
2261 .name = "sr_core_ck",
2262 .ops = &clkops_omap2_dflt,
2263 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2264 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2265 .clkdm_name = "l4_ao_clkdm",
2266 .parent = &l4_wkup_clk_mux_ck,
2267 .recalc = &followparent_recalc,
2268};
2269
2270static struct clk sr_iva_ck = {
2271 .name = "sr_iva_ck",
2272 .ops = &clkops_omap2_dflt,
2273 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2274 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2275 .clkdm_name = "l4_ao_clkdm",
2276 .parent = &l4_wkup_clk_mux_ck,
2277 .recalc = &followparent_recalc,
2278};
2279
2280static struct clk sr_mpu_ck = {
2281 .name = "sr_mpu_ck",
2282 .ops = &clkops_omap2_dflt,
2283 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2284 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2285 .clkdm_name = "l4_ao_clkdm",
2286 .parent = &l4_wkup_clk_mux_ck,
2287 .recalc = &followparent_recalc,
2288};
2289
2290static struct clk tesla_ck = {
2291 .name = "tesla_ck",
2292 .ops = &clkops_omap2_dflt,
2293 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
2294 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2295 .clkdm_name = "tesla_clkdm",
2296 .parent = &dpll_iva_m4_ck,
2297 .recalc = &followparent_recalc,
2298};
2299
2300static struct clk uart1_ck = {
2301 .name = "uart1_ck",
2302 .ops = &clkops_omap2_dflt,
2303 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2304 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2305 .clkdm_name = "l4_per_clkdm",
2306 .parent = &func_48m_fclk,
2307 .recalc = &followparent_recalc,
2308};
2309
2310static struct clk uart2_ck = {
2311 .name = "uart2_ck",
2312 .ops = &clkops_omap2_dflt,
2313 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2314 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2315 .clkdm_name = "l4_per_clkdm",
2316 .parent = &func_48m_fclk,
2317 .recalc = &followparent_recalc,
2318};
2319
2320static struct clk uart3_ck = {
2321 .name = "uart3_ck",
2322 .ops = &clkops_omap2_dflt,
2323 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2324 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2325 .clkdm_name = "l4_per_clkdm",
2326 .parent = &func_48m_fclk,
2327 .recalc = &followparent_recalc,
2328};
2329
2330static struct clk uart4_ck = {
2331 .name = "uart4_ck",
2332 .ops = &clkops_omap2_dflt,
2333 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2334 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2335 .clkdm_name = "l4_per_clkdm",
2336 .parent = &func_48m_fclk,
2337 .recalc = &followparent_recalc,
2338};
2339
2340static struct clk unipro1_ck = {
2341 .name = "unipro1_ck",
2342 .ops = &clkops_omap2_dflt,
2343 .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
2344 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2345 .clkdm_name = "l3_init_clkdm",
2346 .parent = &func_96m_fclk,
2347 .recalc = &followparent_recalc,
2348};
2349
2350static struct clk usb_host_ck = {
2351 .name = "usb_host_ck",
2352 .ops = &clkops_omap2_dflt,
2353 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2354 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2355 .clkdm_name = "l3_init_clkdm",
2356 .parent = &init_60m_fclk,
2357 .recalc = &followparent_recalc,
2358};
2359
2360static struct clk usb_host_fs_ck = {
2361 .name = "usb_host_fs_ck",
2362 .ops = &clkops_omap2_dflt,
2363 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2364 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2365 .clkdm_name = "l3_init_clkdm",
2366 .parent = &func_48mc_fclk,
2367 .recalc = &followparent_recalc,
2368};
2369
2370static struct clk usb_otg_ck = {
2371 .name = "usb_otg_ck",
2372 .ops = &clkops_omap2_dflt,
2373 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2374 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2375 .clkdm_name = "l3_init_clkdm",
2376 .parent = &l3_div_ck,
2377 .recalc = &followparent_recalc,
2378};
2379
2380static struct clk usb_tll_ck = {
2381 .name = "usb_tll_ck",
2382 .ops = &clkops_omap2_dflt,
2383 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2384 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2385 .clkdm_name = "l3_init_clkdm",
2386 .parent = &l4_div_ck,
2387 .recalc = &followparent_recalc,
2388};
2389
2390static struct clk usbphyocp2scp_ck = {
2391 .name = "usbphyocp2scp_ck",
2392 .ops = &clkops_omap2_dflt,
2393 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2394 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2395 .clkdm_name = "l3_init_clkdm",
2396 .parent = &l4_div_ck,
2397 .recalc = &followparent_recalc,
2398};
2399
2400static struct clk usim_ck = {
2401 .name = "usim_ck",
2402 .ops = &clkops_omap2_dflt,
2403 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2404 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2405 .clkdm_name = "l4_wkup_clkdm",
2406 .parent = &sys_32k_ck,
2407 .recalc = &followparent_recalc,
2408};
2409
2410static struct clk wdt2_ck = {
2411 .name = "wdt2_ck",
2412 .ops = &clkops_omap2_dflt,
2413 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2414 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2415 .clkdm_name = "l4_wkup_clkdm",
2416 .parent = &sys_32k_ck,
2417 .recalc = &followparent_recalc,
2418};
2419
2420static struct clk wdt3_ck = {
2421 .name = "wdt3_ck",
2422 .ops = &clkops_omap2_dflt,
2423 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2424 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2425 .clkdm_name = "abe_clkdm",
2426 .parent = &sys_32k_ck,
2427 .recalc = &followparent_recalc,
2428};
2429
2430/* Remaining optional clocks */
2431static const struct clksel otg_60m_gfclk_sel[] = {
2432 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2433 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2434 { .parent = NULL },
2435};
2436
2437static struct clk otg_60m_gfclk_ck = {
2438 .name = "otg_60m_gfclk_ck",
2439 .parent = &utmi_phy_clkout_ck,
2440 .clksel = otg_60m_gfclk_sel,
2441 .init = &omap2_init_clksel_parent,
2442 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2443 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2444 .ops = &clkops_null,
2445 .recalc = &omap2_clksel_recalc,
2446 .flags = CLOCK_IN_OMAP4430,
2447};
2448
2449static const struct clksel stm_clk_div_div[] = {
2450 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2451 { .parent = NULL },
2452};
2453
2454static struct clk stm_clk_div_ck = {
2455 .name = "stm_clk_div_ck",
2456 .parent = &pmd_stm_clock_mux_ck,
2457 .clksel = stm_clk_div_div,
2458 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2459 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2460 .ops = &clkops_null,
2461 .recalc = &omap2_clksel_recalc,
2462 .round_rate = &omap2_clksel_round_rate,
2463 .set_rate = &omap2_clksel_set_rate,
2464 .flags = CLOCK_IN_OMAP4430,
2465};
2466
2467static const struct clksel trace_clk_div_div[] = {
2468 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2469 { .parent = NULL },
2470};
2471
2472static struct clk trace_clk_div_ck = {
2473 .name = "trace_clk_div_ck",
2474 .parent = &pmd_trace_clk_mux_ck,
2475 .clksel = trace_clk_div_div,
2476 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2477 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2478 .ops = &clkops_null,
2479 .recalc = &omap2_clksel_recalc,
2480 .round_rate = &omap2_clksel_round_rate,
2481 .set_rate = &omap2_clksel_set_rate,
2482 .flags = CLOCK_IN_OMAP4430,
2483};
2484
2485static const struct clksel_rate div2_14to18_rates[] = {
2486 { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2487 { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2488 { .div = 0 },
2489};
2490
2491static const struct clksel usim_fclk_div[] = {
2492 { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
2493 { .parent = NULL },
2494};
2495
2496static struct clk usim_fclk = {
2497 .name = "usim_fclk",
2498 .parent = &dpll_per_m4_ck,
2499 .clksel = usim_fclk_div,
2500 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2501 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2502 .ops = &clkops_null,
2503 .recalc = &omap2_clksel_recalc,
2504 .round_rate = &omap2_clksel_round_rate,
2505 .set_rate = &omap2_clksel_set_rate,
2506 .flags = CLOCK_IN_OMAP4430,
2507};
2508
2509static const struct clksel utmi_p1_gfclk_sel[] = {
2510 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2511 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2512 { .parent = NULL },
2513};
2514
2515static struct clk utmi_p1_gfclk_ck = {
2516 .name = "utmi_p1_gfclk_ck",
2517 .parent = &init_60m_fclk,
2518 .clksel = utmi_p1_gfclk_sel,
2519 .init = &omap2_init_clksel_parent,
2520 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2521 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2522 .ops = &clkops_null,
2523 .recalc = &omap2_clksel_recalc,
2524 .flags = CLOCK_IN_OMAP4430,
2525};
2526
2527static const struct clksel utmi_p2_gfclk_sel[] = {
2528 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2529 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2530 { .parent = NULL },
2531};
2532
2533static struct clk utmi_p2_gfclk_ck = {
2534 .name = "utmi_p2_gfclk_ck",
2535 .parent = &init_60m_fclk,
2536 .clksel = utmi_p2_gfclk_sel,
2537 .init = &omap2_init_clksel_parent,
2538 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2539 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2540 .ops = &clkops_null,
2541 .recalc = &omap2_clksel_recalc,
2542 .flags = CLOCK_IN_OMAP4430,
2543};
2544
2545/*
2546 * clkdev
2547 */
2548
2549static struct omap_clk omap44xx_clks[] = {
2550 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
2551 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
2552 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
2553 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
2554 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
2555 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
2556 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
2557 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
2558 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
2559 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
2560 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
2561 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
2562 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
2563 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
2564 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
2565 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
2566 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
2567 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
2568 CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X),
2569 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
2570 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
2571 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
2572 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
2573 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
2574 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
2575 CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X),
2576 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
2577 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
2578 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X),
2579 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
2580 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
2581 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
2582 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X),
2583 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
2584 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
2585 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
2586 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X),
2587 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
2588 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
2589 CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X),
2590 CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X),
2591 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
2592 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
2593 CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X),
2594 CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X),
2595 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
2596 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
2597 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
2598 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
2599 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
2600 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
2601 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
2602 CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X),
2603 CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X),
2604 CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X),
2605 CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X),
2606 CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X),
2607 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
2608 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
2609 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
2610 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
2611 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
2612 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
2613 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
2614 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
2615 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
2616 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
2617 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
2618 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
2619 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
2620 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
2621 CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
2622 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
2623 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
2624 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
2625 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
2626 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
2627 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
2628 CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
2629 CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
2630 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
2631 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
2632 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
2633 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
2634 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
2635 CLK(NULL, "aes1_ck", &aes1_ck, CK_443X),
2636 CLK(NULL, "aes2_ck", &aes2_ck, CK_443X),
2637 CLK(NULL, "aess_ck", &aess_ck, CK_443X),
2638 CLK(NULL, "cust_efuse_ck", &cust_efuse_ck, CK_443X),
2639 CLK(NULL, "des3des_ck", &des3des_ck, CK_443X),
2640 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
2641 CLK(NULL, "dmic_ck", &dmic_ck, CK_443X),
2642 CLK(NULL, "dss_ck", &dss_ck, CK_443X),
2643 CLK(NULL, "ducati_ck", &ducati_ck, CK_443X),
2644 CLK(NULL, "emif1_ck", &emif1_ck, CK_443X),
2645 CLK(NULL, "emif2_ck", &emif2_ck, CK_443X),
2646 CLK(NULL, "fdif_ck", &fdif_ck, CK_443X),
2647 CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X),
2648 CLK(NULL, "gfx_ck", &gfx_ck, CK_443X),
2649 CLK(NULL, "gpio1_ck", &gpio1_ck, CK_443X),
2650 CLK(NULL, "gpio2_ck", &gpio2_ck, CK_443X),
2651 CLK(NULL, "gpio3_ck", &gpio3_ck, CK_443X),
2652 CLK(NULL, "gpio4_ck", &gpio4_ck, CK_443X),
2653 CLK(NULL, "gpio5_ck", &gpio5_ck, CK_443X),
2654 CLK(NULL, "gpio6_ck", &gpio6_ck, CK_443X),
2655 CLK(NULL, "gpmc_ck", &gpmc_ck, CK_443X),
2656 CLK(NULL, "gptimer1_ck", &gptimer1_ck, CK_443X),
2657 CLK(NULL, "gptimer10_ck", &gptimer10_ck, CK_443X),
2658 CLK(NULL, "gptimer11_ck", &gptimer11_ck, CK_443X),
2659 CLK(NULL, "gptimer2_ck", &gptimer2_ck, CK_443X),
2660 CLK(NULL, "gptimer3_ck", &gptimer3_ck, CK_443X),
2661 CLK(NULL, "gptimer4_ck", &gptimer4_ck, CK_443X),
2662 CLK(NULL, "gptimer5_ck", &gptimer5_ck, CK_443X),
2663 CLK(NULL, "gptimer6_ck", &gptimer6_ck, CK_443X),
2664 CLK(NULL, "gptimer7_ck", &gptimer7_ck, CK_443X),
2665 CLK(NULL, "gptimer8_ck", &gptimer8_ck, CK_443X),
2666 CLK(NULL, "gptimer9_ck", &gptimer9_ck, CK_443X),
2667 CLK("omap2_hdq.0", "ick", &hdq1w_ck, CK_443X),
2668 CLK(NULL, "hsi_ck", &hsi_ck, CK_443X),
2669 CLK("i2c_omap.1", "ick", &i2c1_ck, CK_443X),
2670 CLK("i2c_omap.2", "ick", &i2c2_ck, CK_443X),
2671 CLK("i2c_omap.3", "ick", &i2c3_ck, CK_443X),
2672 CLK("i2c_omap.4", "ick", &i2c4_ck, CK_443X),
2673 CLK(NULL, "iss_ck", &iss_ck, CK_443X),
2674 CLK(NULL, "ivahd_ck", &ivahd_ck, CK_443X),
2675 CLK(NULL, "keyboard_ck", &keyboard_ck, CK_443X),
2676 CLK(NULL, "l3_instr_interconnect_ck", &l3_instr_interconnect_ck, CK_443X),
2677 CLK(NULL, "l3_interconnect_3_ck", &l3_interconnect_3_ck, CK_443X),
2678 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
2679 CLK(NULL, "mcasp_ck", &mcasp_ck, CK_443X),
2680 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
2681 CLK("omap-mcbsp.1", "fck", &mcbsp1_ck, CK_443X),
2682 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
2683 CLK("omap-mcbsp.2", "fck", &mcbsp2_ck, CK_443X),
2684 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
2685 CLK("omap-mcbsp.3", "fck", &mcbsp3_ck, CK_443X),
2686 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
2687 CLK("omap-mcbsp.4", "fck", &mcbsp4_ck, CK_443X),
2688 CLK("omap2_mcspi.1", "fck", &mcspi1_ck, CK_443X),
2689 CLK("omap2_mcspi.2", "fck", &mcspi2_ck, CK_443X),
2690 CLK("omap2_mcspi.3", "fck", &mcspi3_ck, CK_443X),
2691 CLK("omap2_mcspi.4", "fck", &mcspi4_ck, CK_443X),
2692 CLK("mmci-omap-hs.0", "fck", &mmc1_ck, CK_443X),
2693 CLK("mmci-omap-hs.1", "fck", &mmc2_ck, CK_443X),
2694 CLK("mmci-omap-hs.2", "fck", &mmc3_ck, CK_443X),
2695 CLK("mmci-omap-hs.3", "fck", &mmc4_ck, CK_443X),
2696 CLK("mmci-omap-hs.4", "fck", &mmc5_ck, CK_443X),
2697 CLK(NULL, "ocp_wp1_ck", &ocp_wp1_ck, CK_443X),
2698 CLK(NULL, "pdm_ck", &pdm_ck, CK_443X),
2699 CLK(NULL, "pkaeip29_ck", &pkaeip29_ck, CK_443X),
2700 CLK("omap_rng", "ick", &rng_ck, CK_443X),
2701 CLK(NULL, "sha2md51_ck", &sha2md51_ck, CK_443X),
2702 CLK(NULL, "sl2_ck", &sl2_ck, CK_443X),
2703 CLK(NULL, "slimbus1_ck", &slimbus1_ck, CK_443X),
2704 CLK(NULL, "slimbus2_ck", &slimbus2_ck, CK_443X),
2705 CLK(NULL, "sr_core_ck", &sr_core_ck, CK_443X),
2706 CLK(NULL, "sr_iva_ck", &sr_iva_ck, CK_443X),
2707 CLK(NULL, "sr_mpu_ck", &sr_mpu_ck, CK_443X),
2708 CLK(NULL, "tesla_ck", &tesla_ck, CK_443X),
2709 CLK(NULL, "uart1_ck", &uart1_ck, CK_443X),
2710 CLK(NULL, "uart2_ck", &uart2_ck, CK_443X),
2711 CLK(NULL, "uart3_ck", &uart3_ck, CK_443X),
2712 CLK(NULL, "uart4_ck", &uart4_ck, CK_443X),
2713 CLK(NULL, "unipro1_ck", &unipro1_ck, CK_443X),
2714 CLK(NULL, "usb_host_ck", &usb_host_ck, CK_443X),
2715 CLK(NULL, "usb_host_fs_ck", &usb_host_fs_ck, CK_443X),
2716 CLK("musb_hdrc", "ick", &usb_otg_ck, CK_443X),
2717 CLK(NULL, "usb_tll_ck", &usb_tll_ck, CK_443X),
2718 CLK(NULL, "usbphyocp2scp_ck", &usbphyocp2scp_ck, CK_443X),
2719 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
2720 CLK("omap_wdt", "fck", &wdt2_ck, CK_443X),
2721 CLK(NULL, "wdt3_ck", &wdt3_ck, CK_443X),
2722 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X),
2723 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2724 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
2725 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2726 CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X),
2727 CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X),
2728};
2729
e80a9729 2730int __init omap4xxx_clk_init(void)
972c5427 2731{
972c5427 2732 struct omap_clk *c;
972c5427
RN		 2733 u32 cpu_clkflg;
2734
2735 if (cpu_is_omap44xx()) {
2736 cpu_mask = RATE_IN_4430;
2737 cpu_clkflg = CK_443X;
2738 }
2739
2740 clk_init(&omap2_clk_functions);
2741
2742 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2743 c++)
2744 clk_preinit(c->lk.clk);
2745
2746 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2747 c++)
2748 if (c->cpu & cpu_clkflg) {
2749 clkdev_add(&c->lk);
2750 clk_register(c->lk.clk);
972c5427 2751 omap2_init_clk_clkdm(c->lk.clk);
972c5427
RN		 2752 }
2753
2754 recalculate_root_clocks();
2755
2756 /*
2757 * Only enable those clocks we will need, let the drivers
2758 * enable other clocks as necessary
2759 */
2760 clk_enable_init_clocks();
2761
2762 return 0;
2763}
kernel source for telekom puls (alcatel/mediatek)