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b045d080 PW |
1 | /* |
2 | * OMAP3 clock framework | |
3 | * | |
4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
5 | * Copyright (C) 2007-2008 Nokia Corporation | |
6 | * | |
7 | * Written by Paul Walmsley | |
542313cc PW |
8 | * With many device clock fixes by Kevin Hilman and Jouni Högander |
9 | * DPLL bypass clock support added by Roman Tereshonkov | |
10 | * | |
11 | */ | |
12 | ||
13 | /* | |
14 | * Virtual clocks are introduced as convenient tools. | |
15 | * They are sources for other clocks and not supposed | |
16 | * to be requested from drivers directly. | |
b045d080 PW |
17 | */ |
18 | ||
19 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | |
20 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | |
21 | ||
a09e64fb | 22 | #include <mach/control.h> |
b045d080 PW |
23 | |
24 | #include "clock.h" | |
25 | #include "cm.h" | |
26 | #include "cm-regbits-34xx.h" | |
27 | #include "prm.h" | |
28 | #include "prm-regbits-34xx.h" | |
29 | ||
30 | static void omap3_dpll_recalc(struct clk *clk); | |
31 | static void omap3_clkoutx2_recalc(struct clk *clk); | |
542313cc PW |
32 | static void omap3_dpll_allow_idle(struct clk *clk); |
33 | static void omap3_dpll_deny_idle(struct clk *clk); | |
34 | static u32 omap3_dpll_autoidle_read(struct clk *clk); | |
35 | static int omap3_noncore_dpll_enable(struct clk *clk); | |
36 | static void omap3_noncore_dpll_disable(struct clk *clk); | |
b045d080 | 37 | |
88b8ba90 PW |
38 | /* Maximum DPLL multiplier, divider values for OMAP3 */ |
39 | #define OMAP3_MAX_DPLL_MULT 2048 | |
40 | #define OMAP3_MAX_DPLL_DIV 128 | |
41 | ||
b045d080 PW |
42 | /* |
43 | * DPLL1 supplies clock to the MPU. | |
44 | * DPLL2 supplies clock to the IVA2. | |
45 | * DPLL3 supplies CORE domain clocks. | |
46 | * DPLL4 supplies peripheral clocks. | |
47 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). | |
48 | */ | |
49 | ||
542313cc PW |
50 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
51 | #define DPLL_LOW_POWER_STOP 0x1 | |
52 | #define DPLL_LOW_POWER_BYPASS 0x5 | |
53 | #define DPLL_LOCKED 0x7 | |
54 | ||
b045d080 PW |
55 | /* PRM CLOCKS */ |
56 | ||
57 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ | |
58 | static struct clk omap_32k_fck = { | |
59 | .name = "omap_32k_fck", | |
60 | .rate = 32768, | |
61 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
62 | ALWAYS_ENABLED, | |
63 | .recalc = &propagate_rate, | |
64 | }; | |
65 | ||
66 | static struct clk secure_32k_fck = { | |
67 | .name = "secure_32k_fck", | |
68 | .rate = 32768, | |
69 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
70 | ALWAYS_ENABLED, | |
71 | .recalc = &propagate_rate, | |
72 | }; | |
73 | ||
74 | /* Virtual source clocks for osc_sys_ck */ | |
75 | static struct clk virt_12m_ck = { | |
76 | .name = "virt_12m_ck", | |
77 | .rate = 12000000, | |
78 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
79 | ALWAYS_ENABLED, | |
80 | .recalc = &propagate_rate, | |
81 | }; | |
82 | ||
83 | static struct clk virt_13m_ck = { | |
84 | .name = "virt_13m_ck", | |
85 | .rate = 13000000, | |
86 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
87 | ALWAYS_ENABLED, | |
88 | .recalc = &propagate_rate, | |
89 | }; | |
90 | ||
91 | static struct clk virt_16_8m_ck = { | |
92 | .name = "virt_16_8m_ck", | |
93 | .rate = 16800000, | |
94 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | | |
95 | ALWAYS_ENABLED, | |
96 | .recalc = &propagate_rate, | |
97 | }; | |
98 | ||
99 | static struct clk virt_19_2m_ck = { | |
100 | .name = "virt_19_2m_ck", | |
101 | .rate = 19200000, | |
102 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
103 | ALWAYS_ENABLED, | |
104 | .recalc = &propagate_rate, | |
105 | }; | |
106 | ||
107 | static struct clk virt_26m_ck = { | |
108 | .name = "virt_26m_ck", | |
109 | .rate = 26000000, | |
110 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
111 | ALWAYS_ENABLED, | |
112 | .recalc = &propagate_rate, | |
113 | }; | |
114 | ||
115 | static struct clk virt_38_4m_ck = { | |
116 | .name = "virt_38_4m_ck", | |
117 | .rate = 38400000, | |
118 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
119 | ALWAYS_ENABLED, | |
120 | .recalc = &propagate_rate, | |
121 | }; | |
122 | ||
123 | static const struct clksel_rate osc_sys_12m_rates[] = { | |
124 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
125 | { .div = 0 } | |
126 | }; | |
127 | ||
128 | static const struct clksel_rate osc_sys_13m_rates[] = { | |
129 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
130 | { .div = 0 } | |
131 | }; | |
132 | ||
133 | static const struct clksel_rate osc_sys_16_8m_rates[] = { | |
134 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, | |
135 | { .div = 0 } | |
136 | }; | |
137 | ||
138 | static const struct clksel_rate osc_sys_19_2m_rates[] = { | |
139 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
140 | { .div = 0 } | |
141 | }; | |
142 | ||
143 | static const struct clksel_rate osc_sys_26m_rates[] = { | |
144 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
145 | { .div = 0 } | |
146 | }; | |
147 | ||
148 | static const struct clksel_rate osc_sys_38_4m_rates[] = { | |
149 | { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
150 | { .div = 0 } | |
151 | }; | |
152 | ||
153 | static const struct clksel osc_sys_clksel[] = { | |
154 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, | |
155 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, | |
156 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, | |
157 | { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, | |
158 | { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, | |
159 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, | |
160 | { .parent = NULL }, | |
161 | }; | |
162 | ||
163 | /* Oscillator clock */ | |
164 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ | |
165 | static struct clk osc_sys_ck = { | |
166 | .name = "osc_sys_ck", | |
167 | .init = &omap2_init_clksel_parent, | |
168 | .clksel_reg = OMAP3430_PRM_CLKSEL, | |
169 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | |
170 | .clksel = osc_sys_clksel, | |
171 | /* REVISIT: deal with autoextclkmode? */ | |
172 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
173 | ALWAYS_ENABLED, | |
174 | .recalc = &omap2_clksel_recalc, | |
175 | }; | |
176 | ||
177 | static const struct clksel_rate div2_rates[] = { | |
178 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
179 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
180 | { .div = 0 } | |
181 | }; | |
182 | ||
183 | static const struct clksel sys_clksel[] = { | |
184 | { .parent = &osc_sys_ck, .rates = div2_rates }, | |
185 | { .parent = NULL } | |
186 | }; | |
187 | ||
188 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ | |
189 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ | |
190 | static struct clk sys_ck = { | |
191 | .name = "sys_ck", | |
192 | .parent = &osc_sys_ck, | |
193 | .init = &omap2_init_clksel_parent, | |
194 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, | |
195 | .clksel_mask = OMAP_SYSCLKDIV_MASK, | |
196 | .clksel = sys_clksel, | |
197 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
198 | .recalc = &omap2_clksel_recalc, | |
199 | }; | |
200 | ||
201 | static struct clk sys_altclk = { | |
202 | .name = "sys_altclk", | |
203 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
204 | .recalc = &propagate_rate, | |
205 | }; | |
206 | ||
207 | /* Optional external clock input for some McBSPs */ | |
208 | static struct clk mcbsp_clks = { | |
209 | .name = "mcbsp_clks", | |
210 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
211 | .recalc = &propagate_rate, | |
212 | }; | |
213 | ||
214 | /* PRM EXTERNAL CLOCK OUTPUT */ | |
215 | ||
216 | static struct clk sys_clkout1 = { | |
217 | .name = "sys_clkout1", | |
218 | .parent = &osc_sys_ck, | |
219 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, | |
220 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, | |
221 | .flags = CLOCK_IN_OMAP343X, | |
222 | .recalc = &followparent_recalc, | |
223 | }; | |
224 | ||
225 | /* DPLLS */ | |
226 | ||
227 | /* CM CLOCKS */ | |
228 | ||
3760d31f RT |
229 | static const struct clksel_rate dpll_bypass_rates[] = { |
230 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
231 | { .div = 0 } | |
232 | }; | |
233 | ||
234 | static const struct clksel_rate dpll_locked_rates[] = { | |
235 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
236 | { .div = 0 } | |
237 | }; | |
238 | ||
239 | static const struct clksel_rate div16_dpll_rates[] = { | |
240 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
241 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
242 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
243 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
244 | { .div = 5, .val = 5, .flags = RATE_IN_343X }, | |
245 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
246 | { .div = 7, .val = 7, .flags = RATE_IN_343X }, | |
247 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
248 | { .div = 9, .val = 9, .flags = RATE_IN_343X }, | |
249 | { .div = 10, .val = 10, .flags = RATE_IN_343X }, | |
250 | { .div = 11, .val = 11, .flags = RATE_IN_343X }, | |
251 | { .div = 12, .val = 12, .flags = RATE_IN_343X }, | |
252 | { .div = 13, .val = 13, .flags = RATE_IN_343X }, | |
253 | { .div = 14, .val = 14, .flags = RATE_IN_343X }, | |
254 | { .div = 15, .val = 15, .flags = RATE_IN_343X }, | |
255 | { .div = 16, .val = 16, .flags = RATE_IN_343X }, | |
256 | { .div = 0 } | |
257 | }; | |
258 | ||
b045d080 PW |
259 | /* DPLL1 */ |
260 | /* MPU clock source */ | |
261 | /* Type: DPLL */ | |
88b8ba90 | 262 | static struct dpll_data dpll1_dd = { |
b045d080 PW |
263 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
264 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, | |
265 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, | |
b045d080 PW |
266 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), |
267 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, | |
542313cc | 268 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
b045d080 PW |
269 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, |
270 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, | |
271 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, | |
542313cc PW |
272 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
273 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, | |
274 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | |
275 | .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, | |
88b8ba90 PW |
276 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
277 | .max_divider = OMAP3_MAX_DPLL_DIV, | |
278 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
b045d080 PW |
279 | }; |
280 | ||
281 | static struct clk dpll1_ck = { | |
282 | .name = "dpll1_ck", | |
283 | .parent = &sys_ck, | |
284 | .dpll_data = &dpll1_dd, | |
285 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
88b8ba90 | 286 | .round_rate = &omap2_dpll_round_rate, |
b045d080 PW |
287 | .recalc = &omap3_dpll_recalc, |
288 | }; | |
289 | ||
290 | /* | |
3760d31f RT |
291 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
292 | * DPLL isn't bypassed. | |
b045d080 | 293 | */ |
3760d31f RT |
294 | static struct clk dpll1_x2_ck = { |
295 | .name = "dpll1_x2_ck", | |
b045d080 PW |
296 | .parent = &dpll1_ck, |
297 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
298 | PARENT_CONTROLS_CLOCK, | |
3760d31f RT |
299 | .recalc = &omap3_clkoutx2_recalc, |
300 | }; | |
301 | ||
302 | /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ | |
303 | static const struct clksel div16_dpll1_x2m2_clksel[] = { | |
304 | { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, | |
305 | { .parent = NULL } | |
306 | }; | |
307 | ||
308 | /* | |
309 | * Does not exist in the TRM - needed to separate the M2 divider from | |
310 | * bypass selection in mpu_ck | |
311 | */ | |
312 | static struct clk dpll1_x2m2_ck = { | |
313 | .name = "dpll1_x2m2_ck", | |
314 | .parent = &dpll1_x2_ck, | |
315 | .init = &omap2_init_clksel_parent, | |
316 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), | |
317 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, | |
318 | .clksel = div16_dpll1_x2m2_clksel, | |
319 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
320 | PARENT_CONTROLS_CLOCK, | |
321 | .recalc = &omap2_clksel_recalc, | |
b045d080 PW |
322 | }; |
323 | ||
324 | /* DPLL2 */ | |
325 | /* IVA2 clock source */ | |
326 | /* Type: DPLL */ | |
327 | ||
88b8ba90 | 328 | static struct dpll_data dpll2_dd = { |
b045d080 PW |
329 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
330 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, | |
331 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, | |
b045d080 PW |
332 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), |
333 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, | |
542313cc PW |
334 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | |
335 | (1 << DPLL_LOW_POWER_BYPASS), | |
b045d080 PW |
336 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, |
337 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, | |
338 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, | |
542313cc PW |
339 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
340 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, | |
341 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), | |
88b8ba90 PW |
342 | .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, |
343 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | |
344 | .max_divider = OMAP3_MAX_DPLL_DIV, | |
345 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
b045d080 PW |
346 | }; |
347 | ||
348 | static struct clk dpll2_ck = { | |
349 | .name = "dpll2_ck", | |
350 | .parent = &sys_ck, | |
351 | .dpll_data = &dpll2_dd, | |
542313cc PW |
352 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
353 | .enable = &omap3_noncore_dpll_enable, | |
354 | .disable = &omap3_noncore_dpll_disable, | |
88b8ba90 | 355 | .round_rate = &omap2_dpll_round_rate, |
b045d080 PW |
356 | .recalc = &omap3_dpll_recalc, |
357 | }; | |
358 | ||
3760d31f RT |
359 | static const struct clksel div16_dpll2_m2x2_clksel[] = { |
360 | { .parent = &dpll2_ck, .rates = div16_dpll_rates }, | |
361 | { .parent = NULL } | |
362 | }; | |
363 | ||
364 | /* | |
365 | * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT | |
366 | * or CLKOUTX2. CLKOUT seems most plausible. | |
367 | */ | |
368 | static struct clk dpll2_m2_ck = { | |
369 | .name = "dpll2_m2_ck", | |
370 | .parent = &dpll2_ck, | |
371 | .init = &omap2_init_clksel_parent, | |
372 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | |
373 | OMAP3430_CM_CLKSEL2_PLL), | |
374 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, | |
375 | .clksel = div16_dpll2_m2x2_clksel, | |
376 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
377 | PARENT_CONTROLS_CLOCK, | |
378 | .recalc = &omap2_clksel_recalc, | |
379 | }; | |
380 | ||
542313cc PW |
381 | /* |
382 | * DPLL3 | |
383 | * Source clock for all interfaces and for some device fclks | |
384 | * REVISIT: Also supports fast relock bypass - not included below | |
385 | */ | |
88b8ba90 | 386 | static struct dpll_data dpll3_dd = { |
b045d080 PW |
387 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
388 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, | |
389 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, | |
b045d080 PW |
390 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
391 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, | |
392 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, | |
393 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, | |
394 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, | |
542313cc PW |
395 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
396 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, | |
88b8ba90 PW |
397 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
398 | .max_divider = OMAP3_MAX_DPLL_DIV, | |
399 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
b045d080 PW |
400 | }; |
401 | ||
402 | static struct clk dpll3_ck = { | |
403 | .name = "dpll3_ck", | |
404 | .parent = &sys_ck, | |
405 | .dpll_data = &dpll3_dd, | |
406 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
88b8ba90 | 407 | .round_rate = &omap2_dpll_round_rate, |
b045d080 PW |
408 | .recalc = &omap3_dpll_recalc, |
409 | }; | |
410 | ||
3760d31f RT |
411 | /* |
412 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | |
413 | * DPLL isn't bypassed | |
414 | */ | |
415 | static struct clk dpll3_x2_ck = { | |
416 | .name = "dpll3_x2_ck", | |
417 | .parent = &dpll3_ck, | |
418 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
419 | PARENT_CONTROLS_CLOCK, | |
420 | .recalc = &omap3_clkoutx2_recalc, | |
b045d080 PW |
421 | }; |
422 | ||
423 | static const struct clksel_rate div31_dpll3_rates[] = { | |
424 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
425 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
426 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, | |
427 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, | |
428 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, | |
429 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, | |
430 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, | |
431 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, | |
432 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, | |
433 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, | |
434 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, | |
435 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, | |
436 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, | |
437 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, | |
438 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, | |
439 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, | |
440 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, | |
441 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, | |
442 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, | |
443 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, | |
444 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, | |
445 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, | |
446 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, | |
447 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, | |
448 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, | |
449 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, | |
450 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, | |
451 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, | |
452 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, | |
453 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, | |
454 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, | |
455 | { .div = 0 }, | |
456 | }; | |
457 | ||
458 | static const struct clksel div31_dpll3m2_clksel[] = { | |
459 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, | |
460 | { .parent = NULL } | |
461 | }; | |
462 | ||
463 | /* | |
3760d31f RT |
464 | * DPLL3 output M2 |
465 | * REVISIT: This DPLL output divider must be changed in SRAM, so until | |
466 | * that code is ready, this should remain a 'read-only' clksel clock. | |
b045d080 PW |
467 | */ |
468 | static struct clk dpll3_m2_ck = { | |
469 | .name = "dpll3_m2_ck", | |
470 | .parent = &dpll3_ck, | |
471 | .init = &omap2_init_clksel_parent, | |
472 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
473 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, | |
474 | .clksel = div31_dpll3m2_clksel, | |
475 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
476 | PARENT_CONTROLS_CLOCK, | |
477 | .recalc = &omap2_clksel_recalc, | |
478 | }; | |
479 | ||
3760d31f | 480 | static const struct clksel core_ck_clksel[] = { |
333943ba | 481 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
3760d31f RT |
482 | { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, |
483 | { .parent = NULL } | |
484 | }; | |
485 | ||
b045d080 PW |
486 | static struct clk core_ck = { |
487 | .name = "core_ck", | |
3760d31f RT |
488 | .init = &omap2_init_clksel_parent, |
489 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 490 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
3760d31f | 491 | .clksel = core_ck_clksel, |
b045d080 PW |
492 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
493 | PARENT_CONTROLS_CLOCK, | |
3760d31f | 494 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
495 | }; |
496 | ||
3760d31f | 497 | static const struct clksel dpll3_m2x2_ck_clksel[] = { |
333943ba | 498 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
3760d31f RT |
499 | { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, |
500 | { .parent = NULL } | |
b045d080 PW |
501 | }; |
502 | ||
503 | static struct clk dpll3_m2x2_ck = { | |
504 | .name = "dpll3_m2x2_ck", | |
3760d31f RT |
505 | .init = &omap2_init_clksel_parent, |
506 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 507 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
3760d31f | 508 | .clksel = dpll3_m2x2_ck_clksel, |
b045d080 PW |
509 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
510 | PARENT_CONTROLS_CLOCK, | |
3760d31f RT |
511 | .recalc = &omap2_clksel_recalc, |
512 | }; | |
513 | ||
514 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
515 | static const struct clksel div16_dpll3_clksel[] = { | |
516 | { .parent = &dpll3_ck, .rates = div16_dpll_rates }, | |
517 | { .parent = NULL } | |
518 | }; | |
519 | ||
520 | /* This virtual clock is the source for dpll3_m3x2_ck */ | |
521 | static struct clk dpll3_m3_ck = { | |
522 | .name = "dpll3_m3_ck", | |
523 | .parent = &dpll3_ck, | |
524 | .init = &omap2_init_clksel_parent, | |
525 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
526 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, | |
527 | .clksel = div16_dpll3_clksel, | |
528 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
529 | PARENT_CONTROLS_CLOCK, | |
530 | .recalc = &omap2_clksel_recalc, | |
b045d080 PW |
531 | }; |
532 | ||
533 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
534 | static struct clk dpll3_m3x2_ck = { | |
535 | .name = "dpll3_m3x2_ck", | |
3760d31f | 536 | .parent = &dpll3_m3_ck, |
b045d080 PW |
537 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
538 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, | |
539 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | |
3760d31f | 540 | .recalc = &omap3_clkoutx2_recalc, |
b045d080 PW |
541 | }; |
542 | ||
3760d31f | 543 | static const struct clksel emu_core_alwon_ck_clksel[] = { |
333943ba | 544 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
3760d31f | 545 | { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, |
b045d080 PW |
546 | { .parent = NULL } |
547 | }; | |
548 | ||
549 | static struct clk emu_core_alwon_ck = { | |
550 | .name = "emu_core_alwon_ck", | |
3760d31f | 551 | .parent = &dpll3_m3x2_ck, |
b045d080 | 552 | .init = &omap2_init_clksel_parent, |
3760d31f | 553 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
542313cc | 554 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
3760d31f RT |
555 | .clksel = emu_core_alwon_ck_clksel, |
556 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
557 | PARENT_CONTROLS_CLOCK, | |
558 | .recalc = &omap2_clksel_recalc, | |
b045d080 PW |
559 | }; |
560 | ||
561 | /* DPLL4 */ | |
562 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ | |
563 | /* Type: DPLL */ | |
88b8ba90 | 564 | static struct dpll_data dpll4_dd = { |
b045d080 PW |
565 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), |
566 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | |
567 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | |
568 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
569 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | |
542313cc | 570 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
b045d080 PW |
571 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, |
572 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, | |
573 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, | |
542313cc PW |
574 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
575 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, | |
576 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
577 | .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, | |
88b8ba90 PW |
578 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
579 | .max_divider = OMAP3_MAX_DPLL_DIV, | |
580 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
b045d080 PW |
581 | }; |
582 | ||
583 | static struct clk dpll4_ck = { | |
584 | .name = "dpll4_ck", | |
585 | .parent = &sys_ck, | |
586 | .dpll_data = &dpll4_dd, | |
542313cc PW |
587 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
588 | .enable = &omap3_noncore_dpll_enable, | |
589 | .disable = &omap3_noncore_dpll_disable, | |
88b8ba90 | 590 | .round_rate = &omap2_dpll_round_rate, |
b045d080 PW |
591 | .recalc = &omap3_dpll_recalc, |
592 | }; | |
593 | ||
594 | /* | |
595 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | |
3760d31f RT |
596 | * DPLL isn't bypassed -- |
597 | * XXX does this serve any downstream clocks? | |
b045d080 PW |
598 | */ |
599 | static struct clk dpll4_x2_ck = { | |
600 | .name = "dpll4_x2_ck", | |
601 | .parent = &dpll4_ck, | |
602 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
603 | PARENT_CONTROLS_CLOCK, | |
604 | .recalc = &omap3_clkoutx2_recalc, | |
605 | }; | |
606 | ||
607 | static const struct clksel div16_dpll4_clksel[] = { | |
3760d31f | 608 | { .parent = &dpll4_ck, .rates = div16_dpll_rates }, |
b045d080 PW |
609 | { .parent = NULL } |
610 | }; | |
611 | ||
3760d31f RT |
612 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
613 | static struct clk dpll4_m2_ck = { | |
614 | .name = "dpll4_m2_ck", | |
615 | .parent = &dpll4_ck, | |
616 | .init = &omap2_init_clksel_parent, | |
617 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | |
618 | .clksel_mask = OMAP3430_DIV_96M_MASK, | |
619 | .clksel = div16_dpll4_clksel, | |
620 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
621 | PARENT_CONTROLS_CLOCK, | |
622 | .recalc = &omap2_clksel_recalc, | |
623 | }; | |
624 | ||
b045d080 PW |
625 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
626 | static struct clk dpll4_m2x2_ck = { | |
627 | .name = "dpll4_m2x2_ck", | |
3760d31f | 628 | .parent = &dpll4_m2_ck, |
b045d080 PW |
629 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
630 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, | |
b045d080 | 631 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
3760d31f RT |
632 | .recalc = &omap3_clkoutx2_recalc, |
633 | }; | |
634 | ||
635 | static const struct clksel omap_96m_alwon_fck_clksel[] = { | |
333943ba | 636 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
3760d31f RT |
637 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, |
638 | { .parent = NULL } | |
b045d080 PW |
639 | }; |
640 | ||
641 | static struct clk omap_96m_alwon_fck = { | |
642 | .name = "omap_96m_alwon_fck", | |
643 | .parent = &dpll4_m2x2_ck, | |
3760d31f RT |
644 | .init = &omap2_init_clksel_parent, |
645 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 646 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
3760d31f | 647 | .clksel = omap_96m_alwon_fck_clksel, |
b045d080 PW |
648 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
649 | PARENT_CONTROLS_CLOCK, | |
3760d31f | 650 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
651 | }; |
652 | ||
653 | static struct clk omap_96m_fck = { | |
654 | .name = "omap_96m_fck", | |
655 | .parent = &omap_96m_alwon_fck, | |
656 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
657 | PARENT_CONTROLS_CLOCK, | |
658 | .recalc = &followparent_recalc, | |
659 | }; | |
660 | ||
3760d31f | 661 | static const struct clksel cm_96m_fck_clksel[] = { |
333943ba | 662 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
3760d31f RT |
663 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, |
664 | { .parent = NULL } | |
665 | }; | |
666 | ||
b045d080 PW |
667 | static struct clk cm_96m_fck = { |
668 | .name = "cm_96m_fck", | |
669 | .parent = &dpll4_m2x2_ck, | |
3760d31f RT |
670 | .init = &omap2_init_clksel_parent, |
671 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 672 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
3760d31f | 673 | .clksel = cm_96m_fck_clksel, |
b045d080 PW |
674 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
675 | PARENT_CONTROLS_CLOCK, | |
3760d31f RT |
676 | .recalc = &omap2_clksel_recalc, |
677 | }; | |
678 | ||
679 | /* This virtual clock is the source for dpll4_m3x2_ck */ | |
680 | static struct clk dpll4_m3_ck = { | |
681 | .name = "dpll4_m3_ck", | |
682 | .parent = &dpll4_ck, | |
683 | .init = &omap2_init_clksel_parent, | |
684 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | |
685 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, | |
686 | .clksel = div16_dpll4_clksel, | |
687 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
688 | PARENT_CONTROLS_CLOCK, | |
689 | .recalc = &omap2_clksel_recalc, | |
b045d080 PW |
690 | }; |
691 | ||
692 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
693 | static struct clk dpll4_m3x2_ck = { | |
694 | .name = "dpll4_m3x2_ck", | |
3760d31f | 695 | .parent = &dpll4_m3_ck, |
b045d080 PW |
696 | .init = &omap2_init_clksel_parent, |
697 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
698 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, | |
b045d080 | 699 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
3760d31f RT |
700 | .recalc = &omap3_clkoutx2_recalc, |
701 | }; | |
702 | ||
703 | static const struct clksel virt_omap_54m_fck_clksel[] = { | |
333943ba | 704 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
3760d31f RT |
705 | { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, |
706 | { .parent = NULL } | |
707 | }; | |
708 | ||
709 | static struct clk virt_omap_54m_fck = { | |
710 | .name = "virt_omap_54m_fck", | |
711 | .parent = &dpll4_m3x2_ck, | |
712 | .init = &omap2_init_clksel_parent, | |
713 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 714 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
3760d31f RT |
715 | .clksel = virt_omap_54m_fck_clksel, |
716 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
717 | PARENT_CONTROLS_CLOCK, | |
b045d080 PW |
718 | .recalc = &omap2_clksel_recalc, |
719 | }; | |
720 | ||
721 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { | |
722 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
723 | { .div = 0 } | |
724 | }; | |
725 | ||
726 | static const struct clksel_rate omap_54m_alt_rates[] = { | |
727 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
728 | { .div = 0 } | |
729 | }; | |
730 | ||
731 | static const struct clksel omap_54m_clksel[] = { | |
3760d31f | 732 | { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, |
b045d080 PW |
733 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, |
734 | { .parent = NULL } | |
735 | }; | |
736 | ||
737 | static struct clk omap_54m_fck = { | |
738 | .name = "omap_54m_fck", | |
739 | .init = &omap2_init_clksel_parent, | |
740 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
741 | .clksel_mask = OMAP3430_SOURCE_54M, | |
742 | .clksel = omap_54m_clksel, | |
743 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
744 | PARENT_CONTROLS_CLOCK, | |
745 | .recalc = &omap2_clksel_recalc, | |
746 | }; | |
747 | ||
748 | static const struct clksel_rate omap_48m_96md2_rates[] = { | |
749 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
750 | { .div = 0 } | |
751 | }; | |
752 | ||
753 | static const struct clksel_rate omap_48m_alt_rates[] = { | |
754 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
755 | { .div = 0 } | |
756 | }; | |
757 | ||
758 | static const struct clksel omap_48m_clksel[] = { | |
759 | { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, | |
760 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, | |
761 | { .parent = NULL } | |
762 | }; | |
763 | ||
764 | static struct clk omap_48m_fck = { | |
765 | .name = "omap_48m_fck", | |
766 | .init = &omap2_init_clksel_parent, | |
767 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
768 | .clksel_mask = OMAP3430_SOURCE_48M, | |
769 | .clksel = omap_48m_clksel, | |
770 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
771 | PARENT_CONTROLS_CLOCK, | |
772 | .recalc = &omap2_clksel_recalc, | |
773 | }; | |
774 | ||
775 | static struct clk omap_12m_fck = { | |
776 | .name = "omap_12m_fck", | |
777 | .parent = &omap_48m_fck, | |
778 | .fixed_div = 4, | |
779 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
780 | PARENT_CONTROLS_CLOCK, | |
781 | .recalc = &omap2_fixed_divisor_recalc, | |
782 | }; | |
783 | ||
3760d31f RT |
784 | /* This virstual clock is the source for dpll4_m4x2_ck */ |
785 | static struct clk dpll4_m4_ck = { | |
786 | .name = "dpll4_m4_ck", | |
787 | .parent = &dpll4_ck, | |
788 | .init = &omap2_init_clksel_parent, | |
789 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | |
790 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, | |
791 | .clksel = div16_dpll4_clksel, | |
792 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
793 | PARENT_CONTROLS_CLOCK, | |
794 | .recalc = &omap2_clksel_recalc, | |
795 | }; | |
796 | ||
b045d080 PW |
797 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
798 | static struct clk dpll4_m4x2_ck = { | |
799 | .name = "dpll4_m4x2_ck", | |
3760d31f | 800 | .parent = &dpll4_m4_ck, |
b045d080 PW |
801 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
802 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | |
b045d080 | 803 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
3760d31f RT |
804 | .recalc = &omap3_clkoutx2_recalc, |
805 | }; | |
806 | ||
807 | /* This virtual clock is the source for dpll4_m5x2_ck */ | |
808 | static struct clk dpll4_m5_ck = { | |
809 | .name = "dpll4_m5_ck", | |
810 | .parent = &dpll4_ck, | |
811 | .init = &omap2_init_clksel_parent, | |
812 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | |
813 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, | |
814 | .clksel = div16_dpll4_clksel, | |
815 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
816 | PARENT_CONTROLS_CLOCK, | |
b045d080 PW |
817 | .recalc = &omap2_clksel_recalc, |
818 | }; | |
819 | ||
820 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
821 | static struct clk dpll4_m5x2_ck = { | |
822 | .name = "dpll4_m5x2_ck", | |
3760d31f | 823 | .parent = &dpll4_m5_ck, |
b045d080 PW |
824 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
825 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | |
b045d080 | 826 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
3760d31f RT |
827 | .recalc = &omap3_clkoutx2_recalc, |
828 | }; | |
829 | ||
830 | /* This virtual clock is the source for dpll4_m6x2_ck */ | |
831 | static struct clk dpll4_m6_ck = { | |
832 | .name = "dpll4_m6_ck", | |
833 | .parent = &dpll4_ck, | |
834 | .init = &omap2_init_clksel_parent, | |
835 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
836 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, | |
837 | .clksel = div16_dpll4_clksel, | |
838 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
839 | PARENT_CONTROLS_CLOCK, | |
b045d080 PW |
840 | .recalc = &omap2_clksel_recalc, |
841 | }; | |
842 | ||
843 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
844 | static struct clk dpll4_m6x2_ck = { | |
845 | .name = "dpll4_m6x2_ck", | |
3760d31f | 846 | .parent = &dpll4_m6_ck, |
b045d080 PW |
847 | .init = &omap2_init_clksel_parent, |
848 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
849 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, | |
b045d080 | 850 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
3760d31f | 851 | .recalc = &omap3_clkoutx2_recalc, |
b045d080 PW |
852 | }; |
853 | ||
854 | static struct clk emu_per_alwon_ck = { | |
855 | .name = "emu_per_alwon_ck", | |
856 | .parent = &dpll4_m6x2_ck, | |
857 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
858 | PARENT_CONTROLS_CLOCK, | |
859 | .recalc = &followparent_recalc, | |
860 | }; | |
861 | ||
862 | /* DPLL5 */ | |
863 | /* Supplies 120MHz clock, USIM source clock */ | |
864 | /* Type: DPLL */ | |
865 | /* 3430ES2 only */ | |
88b8ba90 | 866 | static struct dpll_data dpll5_dd = { |
b045d080 PW |
867 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), |
868 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, | |
869 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, | |
870 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), | |
871 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, | |
542313cc | 872 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
b045d080 PW |
873 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, |
874 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, | |
875 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, | |
542313cc PW |
876 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), |
877 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, | |
878 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | |
879 | .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, | |
88b8ba90 PW |
880 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
881 | .max_divider = OMAP3_MAX_DPLL_DIV, | |
882 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
b045d080 PW |
883 | }; |
884 | ||
885 | static struct clk dpll5_ck = { | |
886 | .name = "dpll5_ck", | |
887 | .parent = &sys_ck, | |
888 | .dpll_data = &dpll5_dd, | |
542313cc PW |
889 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, |
890 | .enable = &omap3_noncore_dpll_enable, | |
891 | .disable = &omap3_noncore_dpll_disable, | |
88b8ba90 | 892 | .round_rate = &omap2_dpll_round_rate, |
b045d080 PW |
893 | .recalc = &omap3_dpll_recalc, |
894 | }; | |
895 | ||
3760d31f | 896 | static const struct clksel div16_dpll5_clksel[] = { |
b045d080 PW |
897 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, |
898 | { .parent = NULL } | |
899 | }; | |
900 | ||
901 | static struct clk dpll5_m2_ck = { | |
902 | .name = "dpll5_m2_ck", | |
903 | .parent = &dpll5_ck, | |
904 | .init = &omap2_init_clksel_parent, | |
905 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), | |
906 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, | |
3760d31f | 907 | .clksel = div16_dpll5_clksel, |
d756f54e HJ |
908 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | |
909 | PARENT_CONTROLS_CLOCK, | |
b045d080 PW |
910 | .recalc = &omap2_clksel_recalc, |
911 | }; | |
912 | ||
3760d31f | 913 | static const struct clksel omap_120m_fck_clksel[] = { |
333943ba | 914 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
3760d31f RT |
915 | { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, |
916 | { .parent = NULL } | |
917 | }; | |
918 | ||
b045d080 PW |
919 | static struct clk omap_120m_fck = { |
920 | .name = "omap_120m_fck", | |
921 | .parent = &dpll5_m2_ck, | |
333943ba PW |
922 | .init = &omap2_init_clksel_parent, |
923 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | |
924 | .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, | |
925 | .clksel = omap_120m_fck_clksel, | |
3760d31f RT |
926 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | |
927 | PARENT_CONTROLS_CLOCK, | |
333943ba | 928 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
929 | }; |
930 | ||
931 | /* CM EXTERNAL CLOCK OUTPUTS */ | |
932 | ||
933 | static const struct clksel_rate clkout2_src_core_rates[] = { | |
934 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
935 | { .div = 0 } | |
936 | }; | |
937 | ||
938 | static const struct clksel_rate clkout2_src_sys_rates[] = { | |
939 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
940 | { .div = 0 } | |
941 | }; | |
942 | ||
943 | static const struct clksel_rate clkout2_src_96m_rates[] = { | |
944 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
945 | { .div = 0 } | |
946 | }; | |
947 | ||
948 | static const struct clksel_rate clkout2_src_54m_rates[] = { | |
949 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
950 | { .div = 0 } | |
951 | }; | |
952 | ||
953 | static const struct clksel clkout2_src_clksel[] = { | |
954 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, | |
955 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, | |
956 | { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, | |
957 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, | |
958 | { .parent = NULL } | |
959 | }; | |
960 | ||
961 | static struct clk clkout2_src_ck = { | |
962 | .name = "clkout2_src_ck", | |
963 | .init = &omap2_init_clksel_parent, | |
964 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, | |
965 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, | |
966 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | |
967 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, | |
968 | .clksel = clkout2_src_clksel, | |
969 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
970 | .recalc = &omap2_clksel_recalc, | |
971 | }; | |
972 | ||
973 | static const struct clksel_rate sys_clkout2_rates[] = { | |
974 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
975 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | |
976 | { .div = 4, .val = 2, .flags = RATE_IN_343X }, | |
977 | { .div = 8, .val = 3, .flags = RATE_IN_343X }, | |
978 | { .div = 16, .val = 4, .flags = RATE_IN_343X }, | |
979 | { .div = 0 }, | |
980 | }; | |
981 | ||
982 | static const struct clksel sys_clkout2_clksel[] = { | |
983 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, | |
984 | { .parent = NULL }, | |
985 | }; | |
986 | ||
987 | static struct clk sys_clkout2 = { | |
988 | .name = "sys_clkout2", | |
989 | .init = &omap2_init_clksel_parent, | |
990 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | |
991 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, | |
992 | .clksel = sys_clkout2_clksel, | |
993 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | |
994 | .recalc = &omap2_clksel_recalc, | |
995 | }; | |
996 | ||
997 | /* CM OUTPUT CLOCKS */ | |
998 | ||
999 | static struct clk corex2_fck = { | |
1000 | .name = "corex2_fck", | |
1001 | .parent = &dpll3_m2x2_ck, | |
1002 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1003 | PARENT_CONTROLS_CLOCK, | |
1004 | .recalc = &followparent_recalc, | |
1005 | }; | |
1006 | ||
1007 | /* DPLL power domain clock controls */ | |
1008 | ||
1009 | static const struct clksel div2_core_clksel[] = { | |
1010 | { .parent = &core_ck, .rates = div2_rates }, | |
1011 | { .parent = NULL } | |
1012 | }; | |
1013 | ||
3760d31f RT |
1014 | /* |
1015 | * REVISIT: Are these in DPLL power domain or CM power domain? docs | |
1016 | * may be inconsistent here? | |
1017 | */ | |
b045d080 PW |
1018 | static struct clk dpll1_fck = { |
1019 | .name = "dpll1_fck", | |
1020 | .parent = &core_ck, | |
1021 | .init = &omap2_init_clksel_parent, | |
1022 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
1023 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, | |
1024 | .clksel = div2_core_clksel, | |
1025 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1026 | PARENT_CONTROLS_CLOCK, | |
1027 | .recalc = &omap2_clksel_recalc, | |
1028 | }; | |
1029 | ||
3760d31f RT |
1030 | /* |
1031 | * MPU clksel: | |
1032 | * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck | |
1033 | * derives from the high-frequency bypass clock originating from DPLL3, | |
1034 | * called 'dpll1_fck' | |
1035 | */ | |
1036 | static const struct clksel mpu_clksel[] = { | |
333943ba | 1037 | { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, |
3760d31f RT |
1038 | { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, |
1039 | { .parent = NULL } | |
1040 | }; | |
1041 | ||
1042 | static struct clk mpu_ck = { | |
1043 | .name = "mpu_ck", | |
1044 | .parent = &dpll1_x2m2_ck, | |
1045 | .init = &omap2_init_clksel_parent, | |
1046 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | |
1047 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | |
1048 | .clksel = mpu_clksel, | |
1049 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1050 | PARENT_CONTROLS_CLOCK, | |
333943ba | 1051 | .clkdm_name = "mpu_clkdm", |
3760d31f RT |
1052 | .recalc = &omap2_clksel_recalc, |
1053 | }; | |
1054 | ||
1055 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ | |
1056 | static const struct clksel_rate arm_fck_rates[] = { | |
1057 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1058 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | |
1059 | { .div = 0 }, | |
1060 | }; | |
1061 | ||
1062 | static const struct clksel arm_fck_clksel[] = { | |
1063 | { .parent = &mpu_ck, .rates = arm_fck_rates }, | |
1064 | { .parent = NULL } | |
1065 | }; | |
1066 | ||
1067 | static struct clk arm_fck = { | |
1068 | .name = "arm_fck", | |
1069 | .parent = &mpu_ck, | |
1070 | .init = &omap2_init_clksel_parent, | |
1071 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | |
1072 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | |
1073 | .clksel = arm_fck_clksel, | |
1074 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1075 | PARENT_CONTROLS_CLOCK, | |
1076 | .recalc = &omap2_clksel_recalc, | |
1077 | }; | |
1078 | ||
333943ba PW |
1079 | /* XXX What about neon_clkdm ? */ |
1080 | ||
3760d31f RT |
1081 | /* |
1082 | * REVISIT: This clock is never specifically defined in the 3430 TRM, | |
1083 | * although it is referenced - so this is a guess | |
1084 | */ | |
1085 | static struct clk emu_mpu_alwon_ck = { | |
1086 | .name = "emu_mpu_alwon_ck", | |
1087 | .parent = &mpu_ck, | |
1088 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1089 | PARENT_CONTROLS_CLOCK, | |
1090 | .recalc = &followparent_recalc, | |
1091 | }; | |
1092 | ||
b045d080 PW |
1093 | static struct clk dpll2_fck = { |
1094 | .name = "dpll2_fck", | |
1095 | .parent = &core_ck, | |
1096 | .init = &omap2_init_clksel_parent, | |
1097 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
1098 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, | |
1099 | .clksel = div2_core_clksel, | |
1100 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1101 | PARENT_CONTROLS_CLOCK, | |
1102 | .recalc = &omap2_clksel_recalc, | |
1103 | }; | |
1104 | ||
3760d31f RT |
1105 | /* |
1106 | * IVA2 clksel: | |
1107 | * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck | |
1108 | * derives from the high-frequency bypass clock originating from DPLL3, | |
1109 | * called 'dpll2_fck' | |
1110 | */ | |
1111 | ||
1112 | static const struct clksel iva2_clksel[] = { | |
333943ba | 1113 | { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, |
3760d31f RT |
1114 | { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, |
1115 | { .parent = NULL } | |
1116 | }; | |
1117 | ||
1118 | static struct clk iva2_ck = { | |
1119 | .name = "iva2_ck", | |
1120 | .parent = &dpll2_m2_ck, | |
1121 | .init = &omap2_init_clksel_parent, | |
31c203d4 HD |
1122 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), |
1123 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | |
3760d31f RT |
1124 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, |
1125 | OMAP3430_CM_IDLEST_PLL), | |
1126 | .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, | |
1127 | .clksel = iva2_clksel, | |
31c203d4 | 1128 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
333943ba | 1129 | .clkdm_name = "iva2_clkdm", |
3760d31f RT |
1130 | .recalc = &omap2_clksel_recalc, |
1131 | }; | |
1132 | ||
b045d080 PW |
1133 | /* Common interface clocks */ |
1134 | ||
1135 | static struct clk l3_ick = { | |
1136 | .name = "l3_ick", | |
1137 | .parent = &core_ck, | |
1138 | .init = &omap2_init_clksel_parent, | |
1139 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1140 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, | |
1141 | .clksel = div2_core_clksel, | |
1142 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1143 | PARENT_CONTROLS_CLOCK, | |
333943ba | 1144 | .clkdm_name = "core_l3_clkdm", |
b045d080 PW |
1145 | .recalc = &omap2_clksel_recalc, |
1146 | }; | |
1147 | ||
1148 | static const struct clksel div2_l3_clksel[] = { | |
1149 | { .parent = &l3_ick, .rates = div2_rates }, | |
1150 | { .parent = NULL } | |
1151 | }; | |
1152 | ||
1153 | static struct clk l4_ick = { | |
1154 | .name = "l4_ick", | |
1155 | .parent = &l3_ick, | |
1156 | .init = &omap2_init_clksel_parent, | |
1157 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1158 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, | |
1159 | .clksel = div2_l3_clksel, | |
1160 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1161 | PARENT_CONTROLS_CLOCK, | |
333943ba | 1162 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1163 | .recalc = &omap2_clksel_recalc, |
1164 | ||
1165 | }; | |
1166 | ||
1167 | static const struct clksel div2_l4_clksel[] = { | |
1168 | { .parent = &l4_ick, .rates = div2_rates }, | |
1169 | { .parent = NULL } | |
1170 | }; | |
1171 | ||
1172 | static struct clk rm_ick = { | |
1173 | .name = "rm_ick", | |
1174 | .parent = &l4_ick, | |
1175 | .init = &omap2_init_clksel_parent, | |
1176 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
1177 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, | |
1178 | .clksel = div2_l4_clksel, | |
1179 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | |
1180 | .recalc = &omap2_clksel_recalc, | |
1181 | }; | |
1182 | ||
1183 | /* GFX power domain */ | |
1184 | ||
3760d31f | 1185 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ |
b045d080 PW |
1186 | |
1187 | static const struct clksel gfx_l3_clksel[] = { | |
1188 | { .parent = &l3_ick, .rates = gfx_l3_rates }, | |
1189 | { .parent = NULL } | |
1190 | }; | |
1191 | ||
1192 | static struct clk gfx_l3_fck = { | |
1193 | .name = "gfx_l3_fck", | |
1194 | .parent = &l3_ick, | |
1195 | .init = &omap2_init_clksel_parent, | |
1196 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | |
1197 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
1198 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
1199 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
1200 | .clksel = gfx_l3_clksel, | |
1201 | .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, | |
333943ba | 1202 | .clkdm_name = "gfx_3430es1_clkdm", |
b045d080 PW |
1203 | .recalc = &omap2_clksel_recalc, |
1204 | }; | |
1205 | ||
1206 | static struct clk gfx_l3_ick = { | |
1207 | .name = "gfx_l3_ick", | |
1208 | .parent = &l3_ick, | |
333943ba | 1209 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
1210 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
1211 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
1212 | .flags = CLOCK_IN_OMAP3430ES1, | |
333943ba | 1213 | .clkdm_name = "gfx_3430es1_clkdm", |
b045d080 PW |
1214 | .recalc = &followparent_recalc, |
1215 | }; | |
1216 | ||
1217 | static struct clk gfx_cg1_ck = { | |
1218 | .name = "gfx_cg1_ck", | |
1219 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | |
333943ba | 1220 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
1221 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1222 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | |
1223 | .flags = CLOCK_IN_OMAP3430ES1, | |
333943ba | 1224 | .clkdm_name = "gfx_3430es1_clkdm", |
b045d080 PW |
1225 | .recalc = &followparent_recalc, |
1226 | }; | |
1227 | ||
1228 | static struct clk gfx_cg2_ck = { | |
1229 | .name = "gfx_cg2_ck", | |
1230 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | |
333943ba | 1231 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
1232 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1233 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | |
1234 | .flags = CLOCK_IN_OMAP3430ES1, | |
333943ba | 1235 | .clkdm_name = "gfx_3430es1_clkdm", |
b045d080 PW |
1236 | .recalc = &followparent_recalc, |
1237 | }; | |
1238 | ||
1239 | /* SGX power domain - 3430ES2 only */ | |
1240 | ||
1241 | static const struct clksel_rate sgx_core_rates[] = { | |
1242 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1243 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, | |
1244 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, | |
1245 | { .div = 0 }, | |
1246 | }; | |
1247 | ||
1248 | static const struct clksel_rate sgx_96m_rates[] = { | |
1249 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1250 | { .div = 0 }, | |
1251 | }; | |
1252 | ||
1253 | static const struct clksel sgx_clksel[] = { | |
1254 | { .parent = &core_ck, .rates = sgx_core_rates }, | |
1255 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, | |
1256 | { .parent = NULL }, | |
1257 | }; | |
1258 | ||
1259 | static struct clk sgx_fck = { | |
1260 | .name = "sgx_fck", | |
1261 | .init = &omap2_init_clksel_parent, | |
1262 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), | |
1263 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | |
1264 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), | |
1265 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, | |
1266 | .clksel = sgx_clksel, | |
1267 | .flags = CLOCK_IN_OMAP3430ES2, | |
333943ba | 1268 | .clkdm_name = "sgx_clkdm", |
b045d080 PW |
1269 | .recalc = &omap2_clksel_recalc, |
1270 | }; | |
1271 | ||
1272 | static struct clk sgx_ick = { | |
1273 | .name = "sgx_ick", | |
1274 | .parent = &l3_ick, | |
333943ba | 1275 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
1276 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), |
1277 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | |
1278 | .flags = CLOCK_IN_OMAP3430ES2, | |
333943ba | 1279 | .clkdm_name = "sgx_clkdm", |
b045d080 PW |
1280 | .recalc = &followparent_recalc, |
1281 | }; | |
1282 | ||
1283 | /* CORE power domain */ | |
1284 | ||
1285 | static struct clk d2d_26m_fck = { | |
1286 | .name = "d2d_26m_fck", | |
1287 | .parent = &sys_ck, | |
333943ba | 1288 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
1289 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1290 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | |
1291 | .flags = CLOCK_IN_OMAP3430ES1, | |
333943ba | 1292 | .clkdm_name = "d2d_clkdm", |
b045d080 PW |
1293 | .recalc = &followparent_recalc, |
1294 | }; | |
1295 | ||
1296 | static const struct clksel omap343x_gpt_clksel[] = { | |
1297 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, | |
1298 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | |
1299 | { .parent = NULL} | |
1300 | }; | |
1301 | ||
1302 | static struct clk gpt10_fck = { | |
1303 | .name = "gpt10_fck", | |
1304 | .parent = &sys_ck, | |
1305 | .init = &omap2_init_clksel_parent, | |
1306 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1307 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | |
1308 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1309 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, | |
1310 | .clksel = omap343x_gpt_clksel, | |
1311 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1312 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1313 | .recalc = &omap2_clksel_recalc, |
1314 | }; | |
1315 | ||
1316 | static struct clk gpt11_fck = { | |
1317 | .name = "gpt11_fck", | |
1318 | .parent = &sys_ck, | |
1319 | .init = &omap2_init_clksel_parent, | |
1320 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1321 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | |
1322 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1323 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, | |
1324 | .clksel = omap343x_gpt_clksel, | |
1325 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1326 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1327 | .recalc = &omap2_clksel_recalc, |
1328 | }; | |
1329 | ||
1330 | static struct clk cpefuse_fck = { | |
1331 | .name = "cpefuse_fck", | |
1332 | .parent = &sys_ck, | |
1333 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
1334 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | |
1335 | .flags = CLOCK_IN_OMAP3430ES2, | |
1336 | .recalc = &followparent_recalc, | |
1337 | }; | |
1338 | ||
1339 | static struct clk ts_fck = { | |
1340 | .name = "ts_fck", | |
1341 | .parent = &omap_32k_fck, | |
1342 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
1343 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | |
1344 | .flags = CLOCK_IN_OMAP3430ES2, | |
1345 | .recalc = &followparent_recalc, | |
1346 | }; | |
1347 | ||
1348 | static struct clk usbtll_fck = { | |
1349 | .name = "usbtll_fck", | |
1350 | .parent = &omap_120m_fck, | |
1351 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
1352 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
1353 | .flags = CLOCK_IN_OMAP3430ES2, | |
1354 | .recalc = &followparent_recalc, | |
1355 | }; | |
1356 | ||
1357 | /* CORE 96M FCLK-derived clocks */ | |
1358 | ||
1359 | static struct clk core_96m_fck = { | |
1360 | .name = "core_96m_fck", | |
1361 | .parent = &omap_96m_fck, | |
1362 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1363 | PARENT_CONTROLS_CLOCK, | |
333943ba | 1364 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1365 | .recalc = &followparent_recalc, |
1366 | }; | |
1367 | ||
1368 | static struct clk mmchs3_fck = { | |
1369 | .name = "mmchs_fck", | |
1370 | .id = 3, | |
1371 | .parent = &core_96m_fck, | |
1372 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1373 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | |
1374 | .flags = CLOCK_IN_OMAP3430ES2, | |
333943ba | 1375 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1376 | .recalc = &followparent_recalc, |
1377 | }; | |
1378 | ||
1379 | static struct clk mmchs2_fck = { | |
1380 | .name = "mmchs_fck", | |
1381 | .id = 2, | |
1382 | .parent = &core_96m_fck, | |
1383 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1384 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | |
1385 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1386 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1387 | .recalc = &followparent_recalc, |
1388 | }; | |
1389 | ||
1390 | static struct clk mspro_fck = { | |
1391 | .name = "mspro_fck", | |
1392 | .parent = &core_96m_fck, | |
1393 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1394 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | |
1395 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1396 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1397 | .recalc = &followparent_recalc, |
1398 | }; | |
1399 | ||
1400 | static struct clk mmchs1_fck = { | |
1401 | .name = "mmchs_fck", | |
1402 | .id = 1, | |
1403 | .parent = &core_96m_fck, | |
1404 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1405 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | |
1406 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1407 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1408 | .recalc = &followparent_recalc, |
1409 | }; | |
1410 | ||
1411 | static struct clk i2c3_fck = { | |
1412 | .name = "i2c_fck", | |
1413 | .id = 3, | |
1414 | .parent = &core_96m_fck, | |
1415 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1416 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | |
1417 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1418 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1419 | .recalc = &followparent_recalc, |
1420 | }; | |
1421 | ||
1422 | static struct clk i2c2_fck = { | |
1423 | .name = "i2c_fck", | |
333943ba | 1424 | .id = 2, |
b045d080 PW |
1425 | .parent = &core_96m_fck, |
1426 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1427 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | |
1428 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1429 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1430 | .recalc = &followparent_recalc, |
1431 | }; | |
1432 | ||
1433 | static struct clk i2c1_fck = { | |
1434 | .name = "i2c_fck", | |
1435 | .id = 1, | |
1436 | .parent = &core_96m_fck, | |
1437 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1438 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | |
1439 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1440 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1441 | .recalc = &followparent_recalc, |
1442 | }; | |
1443 | ||
1444 | /* | |
1445 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; | |
1446 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. | |
1447 | */ | |
1448 | static const struct clksel_rate common_mcbsp_96m_rates[] = { | |
1449 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1450 | { .div = 0 } | |
1451 | }; | |
1452 | ||
1453 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { | |
1454 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1455 | { .div = 0 } | |
1456 | }; | |
1457 | ||
1458 | static const struct clksel mcbsp_15_clksel[] = { | |
1459 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, | |
1460 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | |
1461 | { .parent = NULL } | |
1462 | }; | |
1463 | ||
1464 | static struct clk mcbsp5_fck = { | |
78673bc8 EV |
1465 | .name = "mcbsp_fck", |
1466 | .id = 5, | |
b045d080 PW |
1467 | .init = &omap2_init_clksel_parent, |
1468 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1469 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | |
1470 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
1471 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | |
1472 | .clksel = mcbsp_15_clksel, | |
1473 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1474 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1475 | .recalc = &omap2_clksel_recalc, |
1476 | }; | |
1477 | ||
1478 | static struct clk mcbsp1_fck = { | |
78673bc8 EV |
1479 | .name = "mcbsp_fck", |
1480 | .id = 1, | |
b045d080 PW |
1481 | .init = &omap2_init_clksel_parent, |
1482 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1483 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1484 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
1485 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | |
1486 | .clksel = mcbsp_15_clksel, | |
1487 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1488 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1489 | .recalc = &omap2_clksel_recalc, |
1490 | }; | |
1491 | ||
1492 | /* CORE_48M_FCK-derived clocks */ | |
1493 | ||
1494 | static struct clk core_48m_fck = { | |
1495 | .name = "core_48m_fck", | |
1496 | .parent = &omap_48m_fck, | |
1497 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1498 | PARENT_CONTROLS_CLOCK, | |
333943ba | 1499 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1500 | .recalc = &followparent_recalc, |
1501 | }; | |
1502 | ||
1503 | static struct clk mcspi4_fck = { | |
1504 | .name = "mcspi_fck", | |
1505 | .id = 4, | |
1506 | .parent = &core_48m_fck, | |
1507 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1508 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
1509 | .flags = CLOCK_IN_OMAP343X, | |
1510 | .recalc = &followparent_recalc, | |
1511 | }; | |
1512 | ||
1513 | static struct clk mcspi3_fck = { | |
1514 | .name = "mcspi_fck", | |
1515 | .id = 3, | |
1516 | .parent = &core_48m_fck, | |
1517 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1518 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
1519 | .flags = CLOCK_IN_OMAP343X, | |
1520 | .recalc = &followparent_recalc, | |
1521 | }; | |
1522 | ||
1523 | static struct clk mcspi2_fck = { | |
1524 | .name = "mcspi_fck", | |
1525 | .id = 2, | |
1526 | .parent = &core_48m_fck, | |
1527 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1528 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
1529 | .flags = CLOCK_IN_OMAP343X, | |
1530 | .recalc = &followparent_recalc, | |
1531 | }; | |
1532 | ||
1533 | static struct clk mcspi1_fck = { | |
1534 | .name = "mcspi_fck", | |
1535 | .id = 1, | |
1536 | .parent = &core_48m_fck, | |
1537 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1538 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1539 | .flags = CLOCK_IN_OMAP343X, | |
1540 | .recalc = &followparent_recalc, | |
1541 | }; | |
1542 | ||
1543 | static struct clk uart2_fck = { | |
1544 | .name = "uart2_fck", | |
1545 | .parent = &core_48m_fck, | |
1546 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1547 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | |
1548 | .flags = CLOCK_IN_OMAP343X, | |
1549 | .recalc = &followparent_recalc, | |
1550 | }; | |
1551 | ||
1552 | static struct clk uart1_fck = { | |
1553 | .name = "uart1_fck", | |
1554 | .parent = &core_48m_fck, | |
1555 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1556 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | |
1557 | .flags = CLOCK_IN_OMAP343X, | |
1558 | .recalc = &followparent_recalc, | |
1559 | }; | |
1560 | ||
1561 | static struct clk fshostusb_fck = { | |
1562 | .name = "fshostusb_fck", | |
1563 | .parent = &core_48m_fck, | |
1564 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1565 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | |
1566 | .flags = CLOCK_IN_OMAP3430ES1, | |
1567 | .recalc = &followparent_recalc, | |
1568 | }; | |
1569 | ||
1570 | /* CORE_12M_FCK based clocks */ | |
1571 | ||
1572 | static struct clk core_12m_fck = { | |
1573 | .name = "core_12m_fck", | |
1574 | .parent = &omap_12m_fck, | |
1575 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1576 | PARENT_CONTROLS_CLOCK, | |
333943ba | 1577 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1578 | .recalc = &followparent_recalc, |
1579 | }; | |
1580 | ||
1581 | static struct clk hdq_fck = { | |
1582 | .name = "hdq_fck", | |
1583 | .parent = &core_12m_fck, | |
1584 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1585 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | |
1586 | .flags = CLOCK_IN_OMAP343X, | |
1587 | .recalc = &followparent_recalc, | |
1588 | }; | |
1589 | ||
1590 | /* DPLL3-derived clock */ | |
1591 | ||
1592 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { | |
1593 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1594 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
1595 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
1596 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
1597 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
1598 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
1599 | { .div = 0 } | |
1600 | }; | |
1601 | ||
1602 | static const struct clksel ssi_ssr_clksel[] = { | |
1603 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, | |
1604 | { .parent = NULL } | |
1605 | }; | |
1606 | ||
1607 | static struct clk ssi_ssr_fck = { | |
1608 | .name = "ssi_ssr_fck", | |
1609 | .init = &omap2_init_clksel_parent, | |
1610 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1611 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1612 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1613 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | |
1614 | .clksel = ssi_ssr_clksel, | |
1615 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
333943ba | 1616 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1617 | .recalc = &omap2_clksel_recalc, |
1618 | }; | |
1619 | ||
1620 | static struct clk ssi_sst_fck = { | |
1621 | .name = "ssi_sst_fck", | |
1622 | .parent = &ssi_ssr_fck, | |
1623 | .fixed_div = 2, | |
1624 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | |
1625 | .recalc = &omap2_fixed_divisor_recalc, | |
1626 | }; | |
1627 | ||
1628 | ||
1629 | ||
1630 | /* CORE_L3_ICK based clocks */ | |
1631 | ||
333943ba PW |
1632 | /* |
1633 | * XXX must add clk_enable/clk_disable for these if standard code won't | |
1634 | * handle it | |
1635 | */ | |
b045d080 PW |
1636 | static struct clk core_l3_ick = { |
1637 | .name = "core_l3_ick", | |
1638 | .parent = &l3_ick, | |
333943ba | 1639 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
1640 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1641 | PARENT_CONTROLS_CLOCK, | |
333943ba | 1642 | .clkdm_name = "core_l3_clkdm", |
b045d080 PW |
1643 | .recalc = &followparent_recalc, |
1644 | }; | |
1645 | ||
1646 | static struct clk hsotgusb_ick = { | |
1647 | .name = "hsotgusb_ick", | |
1648 | .parent = &core_l3_ick, | |
1649 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1650 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | |
1651 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1652 | .clkdm_name = "core_l3_clkdm", |
b045d080 PW |
1653 | .recalc = &followparent_recalc, |
1654 | }; | |
1655 | ||
1656 | static struct clk sdrc_ick = { | |
1657 | .name = "sdrc_ick", | |
1658 | .parent = &core_l3_ick, | |
1659 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1660 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, | |
1661 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | |
333943ba | 1662 | .clkdm_name = "core_l3_clkdm", |
b045d080 PW |
1663 | .recalc = &followparent_recalc, |
1664 | }; | |
1665 | ||
1666 | static struct clk gpmc_fck = { | |
1667 | .name = "gpmc_fck", | |
1668 | .parent = &core_l3_ick, | |
1669 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | | |
1670 | ENABLE_ON_INIT, | |
333943ba | 1671 | .clkdm_name = "core_l3_clkdm", |
b045d080 PW |
1672 | .recalc = &followparent_recalc, |
1673 | }; | |
1674 | ||
1675 | /* SECURITY_L3_ICK based clocks */ | |
1676 | ||
1677 | static struct clk security_l3_ick = { | |
1678 | .name = "security_l3_ick", | |
1679 | .parent = &l3_ick, | |
1680 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1681 | PARENT_CONTROLS_CLOCK, | |
1682 | .recalc = &followparent_recalc, | |
1683 | }; | |
1684 | ||
1685 | static struct clk pka_ick = { | |
1686 | .name = "pka_ick", | |
1687 | .parent = &security_l3_ick, | |
1688 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1689 | .enable_bit = OMAP3430_EN_PKA_SHIFT, | |
1690 | .flags = CLOCK_IN_OMAP343X, | |
1691 | .recalc = &followparent_recalc, | |
1692 | }; | |
1693 | ||
1694 | /* CORE_L4_ICK based clocks */ | |
1695 | ||
1696 | static struct clk core_l4_ick = { | |
1697 | .name = "core_l4_ick", | |
1698 | .parent = &l4_ick, | |
333943ba | 1699 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
1700 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1701 | PARENT_CONTROLS_CLOCK, | |
333943ba | 1702 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1703 | .recalc = &followparent_recalc, |
1704 | }; | |
1705 | ||
1706 | static struct clk usbtll_ick = { | |
1707 | .name = "usbtll_ick", | |
1708 | .parent = &core_l4_ick, | |
1709 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | |
1710 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
1711 | .flags = CLOCK_IN_OMAP3430ES2, | |
333943ba | 1712 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1713 | .recalc = &followparent_recalc, |
1714 | }; | |
1715 | ||
1716 | static struct clk mmchs3_ick = { | |
1717 | .name = "mmchs_ick", | |
1718 | .id = 3, | |
1719 | .parent = &core_l4_ick, | |
1720 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1721 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | |
1722 | .flags = CLOCK_IN_OMAP3430ES2, | |
333943ba | 1723 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1724 | .recalc = &followparent_recalc, |
1725 | }; | |
1726 | ||
1727 | /* Intersystem Communication Registers - chassis mode only */ | |
1728 | static struct clk icr_ick = { | |
1729 | .name = "icr_ick", | |
1730 | .parent = &core_l4_ick, | |
1731 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1732 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | |
1733 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1734 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1735 | .recalc = &followparent_recalc, |
1736 | }; | |
1737 | ||
1738 | static struct clk aes2_ick = { | |
1739 | .name = "aes2_ick", | |
1740 | .parent = &core_l4_ick, | |
1741 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1742 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | |
1743 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1744 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1745 | .recalc = &followparent_recalc, |
1746 | }; | |
1747 | ||
1748 | static struct clk sha12_ick = { | |
1749 | .name = "sha12_ick", | |
1750 | .parent = &core_l4_ick, | |
1751 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1752 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | |
1753 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1754 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1755 | .recalc = &followparent_recalc, |
1756 | }; | |
1757 | ||
1758 | static struct clk des2_ick = { | |
1759 | .name = "des2_ick", | |
1760 | .parent = &core_l4_ick, | |
1761 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1762 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | |
1763 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1764 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1765 | .recalc = &followparent_recalc, |
1766 | }; | |
1767 | ||
1768 | static struct clk mmchs2_ick = { | |
1769 | .name = "mmchs_ick", | |
1770 | .id = 2, | |
1771 | .parent = &core_l4_ick, | |
1772 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1773 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | |
1774 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1775 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1776 | .recalc = &followparent_recalc, |
1777 | }; | |
1778 | ||
1779 | static struct clk mmchs1_ick = { | |
1780 | .name = "mmchs_ick", | |
1781 | .id = 1, | |
1782 | .parent = &core_l4_ick, | |
1783 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1784 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | |
1785 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1786 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1787 | .recalc = &followparent_recalc, |
1788 | }; | |
1789 | ||
1790 | static struct clk mspro_ick = { | |
1791 | .name = "mspro_ick", | |
1792 | .parent = &core_l4_ick, | |
1793 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1794 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | |
1795 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1796 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1797 | .recalc = &followparent_recalc, |
1798 | }; | |
1799 | ||
1800 | static struct clk hdq_ick = { | |
1801 | .name = "hdq_ick", | |
1802 | .parent = &core_l4_ick, | |
1803 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1804 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | |
1805 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1806 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1807 | .recalc = &followparent_recalc, |
1808 | }; | |
1809 | ||
1810 | static struct clk mcspi4_ick = { | |
1811 | .name = "mcspi_ick", | |
1812 | .id = 4, | |
1813 | .parent = &core_l4_ick, | |
1814 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1815 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
1816 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1817 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1818 | .recalc = &followparent_recalc, |
1819 | }; | |
1820 | ||
1821 | static struct clk mcspi3_ick = { | |
1822 | .name = "mcspi_ick", | |
1823 | .id = 3, | |
1824 | .parent = &core_l4_ick, | |
1825 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1826 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
1827 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1828 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1829 | .recalc = &followparent_recalc, |
1830 | }; | |
1831 | ||
1832 | static struct clk mcspi2_ick = { | |
1833 | .name = "mcspi_ick", | |
1834 | .id = 2, | |
1835 | .parent = &core_l4_ick, | |
1836 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1837 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
1838 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1839 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1840 | .recalc = &followparent_recalc, |
1841 | }; | |
1842 | ||
1843 | static struct clk mcspi1_ick = { | |
1844 | .name = "mcspi_ick", | |
1845 | .id = 1, | |
1846 | .parent = &core_l4_ick, | |
1847 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1848 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1849 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1850 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1851 | .recalc = &followparent_recalc, |
1852 | }; | |
1853 | ||
1854 | static struct clk i2c3_ick = { | |
1855 | .name = "i2c_ick", | |
1856 | .id = 3, | |
1857 | .parent = &core_l4_ick, | |
1858 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1859 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | |
1860 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1861 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1862 | .recalc = &followparent_recalc, |
1863 | }; | |
1864 | ||
1865 | static struct clk i2c2_ick = { | |
1866 | .name = "i2c_ick", | |
1867 | .id = 2, | |
1868 | .parent = &core_l4_ick, | |
1869 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1870 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | |
1871 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1872 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1873 | .recalc = &followparent_recalc, |
1874 | }; | |
1875 | ||
1876 | static struct clk i2c1_ick = { | |
1877 | .name = "i2c_ick", | |
1878 | .id = 1, | |
1879 | .parent = &core_l4_ick, | |
1880 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1881 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | |
1882 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1883 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1884 | .recalc = &followparent_recalc, |
1885 | }; | |
1886 | ||
1887 | static struct clk uart2_ick = { | |
1888 | .name = "uart2_ick", | |
1889 | .parent = &core_l4_ick, | |
1890 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1891 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | |
1892 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1893 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1894 | .recalc = &followparent_recalc, |
1895 | }; | |
1896 | ||
1897 | static struct clk uart1_ick = { | |
1898 | .name = "uart1_ick", | |
1899 | .parent = &core_l4_ick, | |
1900 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1901 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | |
1902 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1903 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1904 | .recalc = &followparent_recalc, |
1905 | }; | |
1906 | ||
1907 | static struct clk gpt11_ick = { | |
1908 | .name = "gpt11_ick", | |
1909 | .parent = &core_l4_ick, | |
1910 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1911 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | |
1912 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1913 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1914 | .recalc = &followparent_recalc, |
1915 | }; | |
1916 | ||
1917 | static struct clk gpt10_ick = { | |
1918 | .name = "gpt10_ick", | |
1919 | .parent = &core_l4_ick, | |
1920 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1921 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | |
1922 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1923 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1924 | .recalc = &followparent_recalc, |
1925 | }; | |
1926 | ||
1927 | static struct clk mcbsp5_ick = { | |
78673bc8 EV |
1928 | .name = "mcbsp_ick", |
1929 | .id = 5, | |
b045d080 PW |
1930 | .parent = &core_l4_ick, |
1931 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1932 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | |
1933 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1934 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1935 | .recalc = &followparent_recalc, |
1936 | }; | |
1937 | ||
1938 | static struct clk mcbsp1_ick = { | |
78673bc8 EV |
1939 | .name = "mcbsp_ick", |
1940 | .id = 1, | |
b045d080 PW |
1941 | .parent = &core_l4_ick, |
1942 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1943 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1944 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1945 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1946 | .recalc = &followparent_recalc, |
1947 | }; | |
1948 | ||
1949 | static struct clk fac_ick = { | |
1950 | .name = "fac_ick", | |
1951 | .parent = &core_l4_ick, | |
1952 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1953 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | |
1954 | .flags = CLOCK_IN_OMAP3430ES1, | |
333943ba | 1955 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1956 | .recalc = &followparent_recalc, |
1957 | }; | |
1958 | ||
1959 | static struct clk mailboxes_ick = { | |
1960 | .name = "mailboxes_ick", | |
1961 | .parent = &core_l4_ick, | |
1962 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1963 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | |
1964 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1965 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1966 | .recalc = &followparent_recalc, |
1967 | }; | |
1968 | ||
1969 | static struct clk omapctrl_ick = { | |
1970 | .name = "omapctrl_ick", | |
1971 | .parent = &core_l4_ick, | |
1972 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1973 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | |
1974 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | |
1975 | .recalc = &followparent_recalc, | |
1976 | }; | |
1977 | ||
1978 | /* SSI_L4_ICK based clocks */ | |
1979 | ||
1980 | static struct clk ssi_l4_ick = { | |
1981 | .name = "ssi_l4_ick", | |
1982 | .parent = &l4_ick, | |
1971a390 JH |
1983 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1984 | PARENT_CONTROLS_CLOCK, | |
333943ba | 1985 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1986 | .recalc = &followparent_recalc, |
1987 | }; | |
1988 | ||
1989 | static struct clk ssi_ick = { | |
1990 | .name = "ssi_ick", | |
1991 | .parent = &ssi_l4_ick, | |
1992 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1993 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1994 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 1995 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1996 | .recalc = &followparent_recalc, |
1997 | }; | |
1998 | ||
1999 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, | |
2000 | * but l4_ick makes more sense to me */ | |
2001 | ||
2002 | static const struct clksel usb_l4_clksel[] = { | |
2003 | { .parent = &l4_ick, .rates = div2_rates }, | |
2004 | { .parent = NULL }, | |
2005 | }; | |
2006 | ||
2007 | static struct clk usb_l4_ick = { | |
2008 | .name = "usb_l4_ick", | |
2009 | .parent = &l4_ick, | |
2010 | .init = &omap2_init_clksel_parent, | |
2011 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
2012 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | |
2013 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
2014 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | |
2015 | .clksel = usb_l4_clksel, | |
2016 | .flags = CLOCK_IN_OMAP3430ES1, | |
2017 | .recalc = &omap2_clksel_recalc, | |
2018 | }; | |
2019 | ||
2020 | /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */ | |
2021 | ||
2022 | /* SECURITY_L4_ICK2 based clocks */ | |
2023 | ||
2024 | static struct clk security_l4_ick2 = { | |
2025 | .name = "security_l4_ick2", | |
2026 | .parent = &l4_ick, | |
2027 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
2028 | PARENT_CONTROLS_CLOCK, | |
2029 | .recalc = &followparent_recalc, | |
2030 | }; | |
2031 | ||
2032 | static struct clk aes1_ick = { | |
2033 | .name = "aes1_ick", | |
2034 | .parent = &security_l4_ick2, | |
2035 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2036 | .enable_bit = OMAP3430_EN_AES1_SHIFT, | |
2037 | .flags = CLOCK_IN_OMAP343X, | |
2038 | .recalc = &followparent_recalc, | |
2039 | }; | |
2040 | ||
2041 | static struct clk rng_ick = { | |
2042 | .name = "rng_ick", | |
2043 | .parent = &security_l4_ick2, | |
2044 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2045 | .enable_bit = OMAP3430_EN_RNG_SHIFT, | |
2046 | .flags = CLOCK_IN_OMAP343X, | |
2047 | .recalc = &followparent_recalc, | |
2048 | }; | |
2049 | ||
2050 | static struct clk sha11_ick = { | |
2051 | .name = "sha11_ick", | |
2052 | .parent = &security_l4_ick2, | |
2053 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2054 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, | |
2055 | .flags = CLOCK_IN_OMAP343X, | |
2056 | .recalc = &followparent_recalc, | |
2057 | }; | |
2058 | ||
2059 | static struct clk des1_ick = { | |
2060 | .name = "des1_ick", | |
2061 | .parent = &security_l4_ick2, | |
2062 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2063 | .enable_bit = OMAP3430_EN_DES1_SHIFT, | |
2064 | .flags = CLOCK_IN_OMAP343X, | |
2065 | .recalc = &followparent_recalc, | |
2066 | }; | |
2067 | ||
2068 | /* DSS */ | |
3760d31f | 2069 | static const struct clksel dss1_alwon_fck_clksel[] = { |
333943ba | 2070 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
3760d31f RT |
2071 | { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, |
2072 | { .parent = NULL } | |
2073 | }; | |
b045d080 PW |
2074 | |
2075 | static struct clk dss1_alwon_fck = { | |
2076 | .name = "dss1_alwon_fck", | |
2077 | .parent = &dpll4_m4x2_ck, | |
3760d31f | 2078 | .init = &omap2_init_clksel_parent, |
b045d080 PW |
2079 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2080 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | |
3760d31f | 2081 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
542313cc | 2082 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
3760d31f | 2083 | .clksel = dss1_alwon_fck_clksel, |
b045d080 | 2084 | .flags = CLOCK_IN_OMAP343X, |
333943ba | 2085 | .clkdm_name = "dss_clkdm", |
3760d31f | 2086 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
2087 | }; |
2088 | ||
2089 | static struct clk dss_tv_fck = { | |
2090 | .name = "dss_tv_fck", | |
2091 | .parent = &omap_54m_fck, | |
333943ba | 2092 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2093 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2094 | .enable_bit = OMAP3430_EN_TV_SHIFT, | |
2095 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2096 | .clkdm_name = "dss_clkdm", |
b045d080 PW |
2097 | .recalc = &followparent_recalc, |
2098 | }; | |
2099 | ||
2100 | static struct clk dss_96m_fck = { | |
2101 | .name = "dss_96m_fck", | |
2102 | .parent = &omap_96m_fck, | |
333943ba | 2103 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2104 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2105 | .enable_bit = OMAP3430_EN_TV_SHIFT, | |
2106 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2107 | .clkdm_name = "dss_clkdm", |
b045d080 PW |
2108 | .recalc = &followparent_recalc, |
2109 | }; | |
2110 | ||
2111 | static struct clk dss2_alwon_fck = { | |
2112 | .name = "dss2_alwon_fck", | |
2113 | .parent = &sys_ck, | |
333943ba | 2114 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2115 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2116 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | |
2117 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2118 | .clkdm_name = "dss_clkdm", |
b045d080 PW |
2119 | .recalc = &followparent_recalc, |
2120 | }; | |
2121 | ||
2122 | static struct clk dss_ick = { | |
2123 | /* Handles both L3 and L4 clocks */ | |
2124 | .name = "dss_ick", | |
2125 | .parent = &l4_ick, | |
333943ba | 2126 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2127 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
2128 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | |
2129 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2130 | .clkdm_name = "dss_clkdm", |
b045d080 PW |
2131 | .recalc = &followparent_recalc, |
2132 | }; | |
2133 | ||
2134 | /* CAM */ | |
2135 | ||
3760d31f | 2136 | static const struct clksel cam_mclk_clksel[] = { |
333943ba | 2137 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
3760d31f RT |
2138 | { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, |
2139 | { .parent = NULL } | |
2140 | }; | |
2141 | ||
b045d080 PW |
2142 | static struct clk cam_mclk = { |
2143 | .name = "cam_mclk", | |
2144 | .parent = &dpll4_m5x2_ck, | |
3760d31f RT |
2145 | .init = &omap2_init_clksel_parent, |
2146 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 2147 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
3760d31f | 2148 | .clksel = cam_mclk_clksel, |
b045d080 PW |
2149 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
2150 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
2151 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2152 | .clkdm_name = "cam_clkdm", |
3760d31f | 2153 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
2154 | }; |
2155 | ||
2156 | static struct clk cam_l3_ick = { | |
2157 | .name = "cam_l3_ick", | |
2158 | .parent = &l3_ick, | |
333943ba | 2159 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2160 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
2161 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
2162 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2163 | .clkdm_name = "cam_clkdm", |
b045d080 PW |
2164 | .recalc = &followparent_recalc, |
2165 | }; | |
2166 | ||
2167 | static struct clk cam_l4_ick = { | |
2168 | .name = "cam_l4_ick", | |
2169 | .parent = &l4_ick, | |
333943ba | 2170 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2171 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
2172 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
2173 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2174 | .clkdm_name = "cam_clkdm", |
b045d080 PW |
2175 | .recalc = &followparent_recalc, |
2176 | }; | |
2177 | ||
2178 | /* USBHOST - 3430ES2 only */ | |
2179 | ||
2180 | static struct clk usbhost_120m_fck = { | |
2181 | .name = "usbhost_120m_fck", | |
2182 | .parent = &omap_120m_fck, | |
333943ba | 2183 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2184 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
2185 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | |
2186 | .flags = CLOCK_IN_OMAP3430ES2, | |
333943ba | 2187 | .clkdm_name = "usbhost_clkdm", |
b045d080 PW |
2188 | .recalc = &followparent_recalc, |
2189 | }; | |
2190 | ||
2191 | static struct clk usbhost_48m_fck = { | |
2192 | .name = "usbhost_48m_fck", | |
2193 | .parent = &omap_48m_fck, | |
333943ba | 2194 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2195 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
2196 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | |
2197 | .flags = CLOCK_IN_OMAP3430ES2, | |
333943ba | 2198 | .clkdm_name = "usbhost_clkdm", |
b045d080 PW |
2199 | .recalc = &followparent_recalc, |
2200 | }; | |
2201 | ||
2202 | static struct clk usbhost_l3_ick = { | |
2203 | .name = "usbhost_l3_ick", | |
2204 | .parent = &l3_ick, | |
333943ba | 2205 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2206 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
2207 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | |
2208 | .flags = CLOCK_IN_OMAP3430ES2, | |
333943ba | 2209 | .clkdm_name = "usbhost_clkdm", |
b045d080 PW |
2210 | .recalc = &followparent_recalc, |
2211 | }; | |
2212 | ||
2213 | static struct clk usbhost_l4_ick = { | |
2214 | .name = "usbhost_l4_ick", | |
2215 | .parent = &l4_ick, | |
333943ba | 2216 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2217 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
2218 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | |
2219 | .flags = CLOCK_IN_OMAP3430ES2, | |
333943ba | 2220 | .clkdm_name = "usbhost_clkdm", |
b045d080 PW |
2221 | .recalc = &followparent_recalc, |
2222 | }; | |
2223 | ||
2224 | static struct clk usbhost_sar_fck = { | |
2225 | .name = "usbhost_sar_fck", | |
2226 | .parent = &osc_sys_ck, | |
333943ba | 2227 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2228 | .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), |
2229 | .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, | |
2230 | .flags = CLOCK_IN_OMAP3430ES2, | |
333943ba | 2231 | .clkdm_name = "usbhost_clkdm", |
b045d080 PW |
2232 | .recalc = &followparent_recalc, |
2233 | }; | |
2234 | ||
2235 | /* WKUP */ | |
2236 | ||
2237 | static const struct clksel_rate usim_96m_rates[] = { | |
2238 | { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2239 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2240 | { .div = 8, .val = 5, .flags = RATE_IN_343X }, | |
2241 | { .div = 10, .val = 6, .flags = RATE_IN_343X }, | |
2242 | { .div = 0 }, | |
2243 | }; | |
2244 | ||
2245 | static const struct clksel_rate usim_120m_rates[] = { | |
2246 | { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2247 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
2248 | { .div = 16, .val = 9, .flags = RATE_IN_343X }, | |
2249 | { .div = 20, .val = 10, .flags = RATE_IN_343X }, | |
2250 | { .div = 0 }, | |
2251 | }; | |
2252 | ||
2253 | static const struct clksel usim_clksel[] = { | |
2254 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, | |
2255 | { .parent = &omap_120m_fck, .rates = usim_120m_rates }, | |
2256 | { .parent = &sys_ck, .rates = div2_rates }, | |
2257 | { .parent = NULL }, | |
2258 | }; | |
2259 | ||
2260 | /* 3430ES2 only */ | |
2261 | static struct clk usim_fck = { | |
2262 | .name = "usim_fck", | |
2263 | .init = &omap2_init_clksel_parent, | |
2264 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2265 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | |
2266 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
2267 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, | |
2268 | .clksel = usim_clksel, | |
2269 | .flags = CLOCK_IN_OMAP3430ES2, | |
2270 | .recalc = &omap2_clksel_recalc, | |
2271 | }; | |
2272 | ||
333943ba | 2273 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ |
b045d080 PW |
2274 | static struct clk gpt1_fck = { |
2275 | .name = "gpt1_fck", | |
2276 | .init = &omap2_init_clksel_parent, | |
2277 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2278 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | |
2279 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
2280 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, | |
2281 | .clksel = omap343x_gpt_clksel, | |
2282 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2283 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2284 | .recalc = &omap2_clksel_recalc, |
2285 | }; | |
2286 | ||
2287 | static struct clk wkup_32k_fck = { | |
2288 | .name = "wkup_32k_fck", | |
333943ba | 2289 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2290 | .parent = &omap_32k_fck, |
2291 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
333943ba | 2292 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2293 | .recalc = &followparent_recalc, |
2294 | }; | |
2295 | ||
2296 | static struct clk gpio1_fck = { | |
2297 | .name = "gpio1_fck", | |
2298 | .parent = &wkup_32k_fck, | |
2299 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2300 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | |
2301 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2302 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2303 | .recalc = &followparent_recalc, |
2304 | }; | |
2305 | ||
2306 | static struct clk wdt2_fck = { | |
2307 | .name = "wdt2_fck", | |
2308 | .parent = &wkup_32k_fck, | |
2309 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2310 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | |
2311 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2312 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2313 | .recalc = &followparent_recalc, |
2314 | }; | |
2315 | ||
2316 | static struct clk wkup_l4_ick = { | |
2317 | .name = "wkup_l4_ick", | |
2318 | .parent = &sys_ck, | |
2319 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
333943ba | 2320 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2321 | .recalc = &followparent_recalc, |
2322 | }; | |
2323 | ||
2324 | /* 3430ES2 only */ | |
2325 | /* Never specifically named in the TRM, so we have to infer a likely name */ | |
2326 | static struct clk usim_ick = { | |
2327 | .name = "usim_ick", | |
2328 | .parent = &wkup_l4_ick, | |
2329 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2330 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | |
2331 | .flags = CLOCK_IN_OMAP3430ES2, | |
333943ba | 2332 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2333 | .recalc = &followparent_recalc, |
2334 | }; | |
2335 | ||
2336 | static struct clk wdt2_ick = { | |
2337 | .name = "wdt2_ick", | |
2338 | .parent = &wkup_l4_ick, | |
2339 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2340 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | |
2341 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2342 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2343 | .recalc = &followparent_recalc, |
2344 | }; | |
2345 | ||
2346 | static struct clk wdt1_ick = { | |
2347 | .name = "wdt1_ick", | |
2348 | .parent = &wkup_l4_ick, | |
2349 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2350 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | |
2351 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2352 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2353 | .recalc = &followparent_recalc, |
2354 | }; | |
2355 | ||
2356 | static struct clk gpio1_ick = { | |
2357 | .name = "gpio1_ick", | |
2358 | .parent = &wkup_l4_ick, | |
2359 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2360 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | |
2361 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2362 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2363 | .recalc = &followparent_recalc, |
2364 | }; | |
2365 | ||
2366 | static struct clk omap_32ksync_ick = { | |
2367 | .name = "omap_32ksync_ick", | |
2368 | .parent = &wkup_l4_ick, | |
2369 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2370 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | |
2371 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2372 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2373 | .recalc = &followparent_recalc, |
2374 | }; | |
2375 | ||
333943ba | 2376 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
b045d080 PW |
2377 | static struct clk gpt12_ick = { |
2378 | .name = "gpt12_ick", | |
2379 | .parent = &wkup_l4_ick, | |
2380 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2381 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | |
2382 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2383 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2384 | .recalc = &followparent_recalc, |
2385 | }; | |
2386 | ||
2387 | static struct clk gpt1_ick = { | |
2388 | .name = "gpt1_ick", | |
2389 | .parent = &wkup_l4_ick, | |
2390 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2391 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | |
2392 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2393 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2394 | .recalc = &followparent_recalc, |
2395 | }; | |
2396 | ||
2397 | ||
2398 | ||
2399 | /* PER clock domain */ | |
2400 | ||
2401 | static struct clk per_96m_fck = { | |
2402 | .name = "per_96m_fck", | |
2403 | .parent = &omap_96m_alwon_fck, | |
333943ba | 2404 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2405 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
2406 | PARENT_CONTROLS_CLOCK, | |
333943ba | 2407 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2408 | .recalc = &followparent_recalc, |
2409 | }; | |
2410 | ||
2411 | static struct clk per_48m_fck = { | |
2412 | .name = "per_48m_fck", | |
2413 | .parent = &omap_48m_fck, | |
333943ba | 2414 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2415 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
2416 | PARENT_CONTROLS_CLOCK, | |
333943ba | 2417 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2418 | .recalc = &followparent_recalc, |
2419 | }; | |
2420 | ||
2421 | static struct clk uart3_fck = { | |
2422 | .name = "uart3_fck", | |
2423 | .parent = &per_48m_fck, | |
2424 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2425 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | |
2426 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2427 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2428 | .recalc = &followparent_recalc, |
2429 | }; | |
2430 | ||
2431 | static struct clk gpt2_fck = { | |
2432 | .name = "gpt2_fck", | |
2433 | .init = &omap2_init_clksel_parent, | |
2434 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2435 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | |
2436 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2437 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, | |
2438 | .clksel = omap343x_gpt_clksel, | |
2439 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2440 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2441 | .recalc = &omap2_clksel_recalc, |
2442 | }; | |
2443 | ||
2444 | static struct clk gpt3_fck = { | |
2445 | .name = "gpt3_fck", | |
2446 | .init = &omap2_init_clksel_parent, | |
2447 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2448 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | |
2449 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2450 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, | |
2451 | .clksel = omap343x_gpt_clksel, | |
2452 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2453 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2454 | .recalc = &omap2_clksel_recalc, |
2455 | }; | |
2456 | ||
2457 | static struct clk gpt4_fck = { | |
2458 | .name = "gpt4_fck", | |
2459 | .init = &omap2_init_clksel_parent, | |
2460 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2461 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | |
2462 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2463 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, | |
2464 | .clksel = omap343x_gpt_clksel, | |
2465 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2466 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2467 | .recalc = &omap2_clksel_recalc, |
2468 | }; | |
2469 | ||
2470 | static struct clk gpt5_fck = { | |
2471 | .name = "gpt5_fck", | |
2472 | .init = &omap2_init_clksel_parent, | |
2473 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2474 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | |
2475 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2476 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, | |
2477 | .clksel = omap343x_gpt_clksel, | |
2478 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2479 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2480 | .recalc = &omap2_clksel_recalc, |
2481 | }; | |
2482 | ||
2483 | static struct clk gpt6_fck = { | |
2484 | .name = "gpt6_fck", | |
2485 | .init = &omap2_init_clksel_parent, | |
2486 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2487 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | |
2488 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2489 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, | |
2490 | .clksel = omap343x_gpt_clksel, | |
2491 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2492 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2493 | .recalc = &omap2_clksel_recalc, |
2494 | }; | |
2495 | ||
2496 | static struct clk gpt7_fck = { | |
2497 | .name = "gpt7_fck", | |
2498 | .init = &omap2_init_clksel_parent, | |
2499 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2500 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | |
2501 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2502 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, | |
2503 | .clksel = omap343x_gpt_clksel, | |
2504 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2505 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2506 | .recalc = &omap2_clksel_recalc, |
2507 | }; | |
2508 | ||
2509 | static struct clk gpt8_fck = { | |
2510 | .name = "gpt8_fck", | |
2511 | .init = &omap2_init_clksel_parent, | |
2512 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2513 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | |
2514 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2515 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, | |
2516 | .clksel = omap343x_gpt_clksel, | |
2517 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2518 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2519 | .recalc = &omap2_clksel_recalc, |
2520 | }; | |
2521 | ||
2522 | static struct clk gpt9_fck = { | |
2523 | .name = "gpt9_fck", | |
2524 | .init = &omap2_init_clksel_parent, | |
2525 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2526 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | |
2527 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2528 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, | |
2529 | .clksel = omap343x_gpt_clksel, | |
2530 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2531 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2532 | .recalc = &omap2_clksel_recalc, |
2533 | }; | |
2534 | ||
2535 | static struct clk per_32k_alwon_fck = { | |
2536 | .name = "per_32k_alwon_fck", | |
2537 | .parent = &omap_32k_fck, | |
333943ba | 2538 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2539 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, |
2540 | .recalc = &followparent_recalc, | |
2541 | }; | |
2542 | ||
2543 | static struct clk gpio6_fck = { | |
2544 | .name = "gpio6_fck", | |
2545 | .parent = &per_32k_alwon_fck, | |
2546 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2547 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
b045d080 | 2548 | .flags = CLOCK_IN_OMAP343X, |
333943ba | 2549 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2550 | .recalc = &followparent_recalc, |
2551 | }; | |
2552 | ||
2553 | static struct clk gpio5_fck = { | |
2554 | .name = "gpio5_fck", | |
2555 | .parent = &per_32k_alwon_fck, | |
2556 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2557 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
b045d080 | 2558 | .flags = CLOCK_IN_OMAP343X, |
333943ba | 2559 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2560 | .recalc = &followparent_recalc, |
2561 | }; | |
2562 | ||
2563 | static struct clk gpio4_fck = { | |
2564 | .name = "gpio4_fck", | |
2565 | .parent = &per_32k_alwon_fck, | |
2566 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2567 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
b045d080 | 2568 | .flags = CLOCK_IN_OMAP343X, |
333943ba | 2569 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2570 | .recalc = &followparent_recalc, |
2571 | }; | |
2572 | ||
2573 | static struct clk gpio3_fck = { | |
2574 | .name = "gpio3_fck", | |
2575 | .parent = &per_32k_alwon_fck, | |
2576 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2577 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
b045d080 | 2578 | .flags = CLOCK_IN_OMAP343X, |
333943ba | 2579 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2580 | .recalc = &followparent_recalc, |
2581 | }; | |
2582 | ||
2583 | static struct clk gpio2_fck = { | |
2584 | .name = "gpio2_fck", | |
2585 | .parent = &per_32k_alwon_fck, | |
2586 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2587 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
b045d080 | 2588 | .flags = CLOCK_IN_OMAP343X, |
333943ba | 2589 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2590 | .recalc = &followparent_recalc, |
2591 | }; | |
2592 | ||
2593 | static struct clk wdt3_fck = { | |
2594 | .name = "wdt3_fck", | |
2595 | .parent = &per_32k_alwon_fck, | |
2596 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2597 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | |
2598 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2599 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2600 | .recalc = &followparent_recalc, |
2601 | }; | |
2602 | ||
2603 | static struct clk per_l4_ick = { | |
2604 | .name = "per_l4_ick", | |
2605 | .parent = &l4_ick, | |
2606 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
2607 | PARENT_CONTROLS_CLOCK, | |
333943ba | 2608 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2609 | .recalc = &followparent_recalc, |
2610 | }; | |
2611 | ||
2612 | static struct clk gpio6_ick = { | |
2613 | .name = "gpio6_ick", | |
2614 | .parent = &per_l4_ick, | |
2615 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2616 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | |
2617 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2618 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2619 | .recalc = &followparent_recalc, |
2620 | }; | |
2621 | ||
2622 | static struct clk gpio5_ick = { | |
2623 | .name = "gpio5_ick", | |
2624 | .parent = &per_l4_ick, | |
2625 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2626 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | |
2627 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2628 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2629 | .recalc = &followparent_recalc, |
2630 | }; | |
2631 | ||
2632 | static struct clk gpio4_ick = { | |
2633 | .name = "gpio4_ick", | |
2634 | .parent = &per_l4_ick, | |
2635 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2636 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | |
2637 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2638 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2639 | .recalc = &followparent_recalc, |
2640 | }; | |
2641 | ||
2642 | static struct clk gpio3_ick = { | |
2643 | .name = "gpio3_ick", | |
2644 | .parent = &per_l4_ick, | |
2645 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2646 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | |
2647 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2648 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2649 | .recalc = &followparent_recalc, |
2650 | }; | |
2651 | ||
2652 | static struct clk gpio2_ick = { | |
2653 | .name = "gpio2_ick", | |
2654 | .parent = &per_l4_ick, | |
2655 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2656 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | |
2657 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2658 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2659 | .recalc = &followparent_recalc, |
2660 | }; | |
2661 | ||
2662 | static struct clk wdt3_ick = { | |
2663 | .name = "wdt3_ick", | |
2664 | .parent = &per_l4_ick, | |
2665 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2666 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | |
2667 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2668 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2669 | .recalc = &followparent_recalc, |
2670 | }; | |
2671 | ||
2672 | static struct clk uart3_ick = { | |
2673 | .name = "uart3_ick", | |
2674 | .parent = &per_l4_ick, | |
2675 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2676 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | |
2677 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2678 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2679 | .recalc = &followparent_recalc, |
2680 | }; | |
2681 | ||
2682 | static struct clk gpt9_ick = { | |
2683 | .name = "gpt9_ick", | |
2684 | .parent = &per_l4_ick, | |
2685 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2686 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | |
2687 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2688 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2689 | .recalc = &followparent_recalc, |
2690 | }; | |
2691 | ||
2692 | static struct clk gpt8_ick = { | |
2693 | .name = "gpt8_ick", | |
2694 | .parent = &per_l4_ick, | |
2695 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2696 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | |
2697 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2698 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2699 | .recalc = &followparent_recalc, |
2700 | }; | |
2701 | ||
2702 | static struct clk gpt7_ick = { | |
2703 | .name = "gpt7_ick", | |
2704 | .parent = &per_l4_ick, | |
2705 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2706 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | |
2707 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2708 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2709 | .recalc = &followparent_recalc, |
2710 | }; | |
2711 | ||
2712 | static struct clk gpt6_ick = { | |
2713 | .name = "gpt6_ick", | |
2714 | .parent = &per_l4_ick, | |
2715 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2716 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | |
2717 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2718 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2719 | .recalc = &followparent_recalc, |
2720 | }; | |
2721 | ||
2722 | static struct clk gpt5_ick = { | |
2723 | .name = "gpt5_ick", | |
2724 | .parent = &per_l4_ick, | |
2725 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2726 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | |
2727 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2728 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2729 | .recalc = &followparent_recalc, |
2730 | }; | |
2731 | ||
2732 | static struct clk gpt4_ick = { | |
2733 | .name = "gpt4_ick", | |
2734 | .parent = &per_l4_ick, | |
2735 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2736 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | |
2737 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2738 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2739 | .recalc = &followparent_recalc, |
2740 | }; | |
2741 | ||
2742 | static struct clk gpt3_ick = { | |
2743 | .name = "gpt3_ick", | |
2744 | .parent = &per_l4_ick, | |
2745 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2746 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | |
2747 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2748 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2749 | .recalc = &followparent_recalc, |
2750 | }; | |
2751 | ||
2752 | static struct clk gpt2_ick = { | |
2753 | .name = "gpt2_ick", | |
2754 | .parent = &per_l4_ick, | |
2755 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2756 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | |
2757 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2758 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2759 | .recalc = &followparent_recalc, |
2760 | }; | |
2761 | ||
2762 | static struct clk mcbsp2_ick = { | |
78673bc8 EV |
2763 | .name = "mcbsp_ick", |
2764 | .id = 2, | |
b045d080 PW |
2765 | .parent = &per_l4_ick, |
2766 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2767 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
2768 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2769 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2770 | .recalc = &followparent_recalc, |
2771 | }; | |
2772 | ||
2773 | static struct clk mcbsp3_ick = { | |
78673bc8 EV |
2774 | .name = "mcbsp_ick", |
2775 | .id = 3, | |
b045d080 PW |
2776 | .parent = &per_l4_ick, |
2777 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2778 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
2779 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2780 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2781 | .recalc = &followparent_recalc, |
2782 | }; | |
2783 | ||
2784 | static struct clk mcbsp4_ick = { | |
78673bc8 EV |
2785 | .name = "mcbsp_ick", |
2786 | .id = 4, | |
b045d080 PW |
2787 | .parent = &per_l4_ick, |
2788 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2789 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | |
2790 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2791 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2792 | .recalc = &followparent_recalc, |
2793 | }; | |
2794 | ||
2795 | static const struct clksel mcbsp_234_clksel[] = { | |
2796 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, | |
333943ba | 2797 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
b045d080 PW |
2798 | { .parent = NULL } |
2799 | }; | |
2800 | ||
2801 | static struct clk mcbsp2_fck = { | |
78673bc8 EV |
2802 | .name = "mcbsp_fck", |
2803 | .id = 2, | |
b045d080 PW |
2804 | .init = &omap2_init_clksel_parent, |
2805 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2806 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
2807 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
2808 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | |
2809 | .clksel = mcbsp_234_clksel, | |
2810 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2811 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2812 | .recalc = &omap2_clksel_recalc, |
2813 | }; | |
2814 | ||
2815 | static struct clk mcbsp3_fck = { | |
78673bc8 EV |
2816 | .name = "mcbsp_fck", |
2817 | .id = 3, | |
b045d080 PW |
2818 | .init = &omap2_init_clksel_parent, |
2819 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2820 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
2821 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
2822 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | |
2823 | .clksel = mcbsp_234_clksel, | |
2824 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2825 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2826 | .recalc = &omap2_clksel_recalc, |
2827 | }; | |
2828 | ||
2829 | static struct clk mcbsp4_fck = { | |
78673bc8 EV |
2830 | .name = "mcbsp_fck", |
2831 | .id = 4, | |
b045d080 PW |
2832 | .init = &omap2_init_clksel_parent, |
2833 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2834 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | |
2835 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
2836 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | |
2837 | .clksel = mcbsp_234_clksel, | |
2838 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 2839 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2840 | .recalc = &omap2_clksel_recalc, |
2841 | }; | |
2842 | ||
2843 | /* EMU clocks */ | |
2844 | ||
2845 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ | |
2846 | ||
2847 | static const struct clksel_rate emu_src_sys_rates[] = { | |
2848 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2849 | { .div = 0 }, | |
2850 | }; | |
2851 | ||
2852 | static const struct clksel_rate emu_src_core_rates[] = { | |
2853 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2854 | { .div = 0 }, | |
2855 | }; | |
2856 | ||
2857 | static const struct clksel_rate emu_src_per_rates[] = { | |
2858 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2859 | { .div = 0 }, | |
2860 | }; | |
2861 | ||
2862 | static const struct clksel_rate emu_src_mpu_rates[] = { | |
2863 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2864 | { .div = 0 }, | |
2865 | }; | |
2866 | ||
2867 | static const struct clksel emu_src_clksel[] = { | |
2868 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, | |
2869 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, | |
2870 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, | |
2871 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, | |
2872 | { .parent = NULL }, | |
2873 | }; | |
2874 | ||
2875 | /* | |
2876 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only | |
2877 | * to switch the source of some of the EMU clocks. | |
2878 | * XXX Are there CLKEN bits for these EMU clks? | |
2879 | */ | |
2880 | static struct clk emu_src_ck = { | |
2881 | .name = "emu_src_ck", | |
2882 | .init = &omap2_init_clksel_parent, | |
2883 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2884 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | |
2885 | .clksel = emu_src_clksel, | |
2886 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
333943ba | 2887 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2888 | .recalc = &omap2_clksel_recalc, |
2889 | }; | |
2890 | ||
2891 | static const struct clksel_rate pclk_emu_rates[] = { | |
2892 | { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2893 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
2894 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2895 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
2896 | { .div = 0 }, | |
2897 | }; | |
2898 | ||
2899 | static const struct clksel pclk_emu_clksel[] = { | |
2900 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, | |
2901 | { .parent = NULL }, | |
2902 | }; | |
2903 | ||
2904 | static struct clk pclk_fck = { | |
2905 | .name = "pclk_fck", | |
2906 | .init = &omap2_init_clksel_parent, | |
2907 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2908 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | |
2909 | .clksel = pclk_emu_clksel, | |
2910 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
333943ba | 2911 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2912 | .recalc = &omap2_clksel_recalc, |
2913 | }; | |
2914 | ||
2915 | static const struct clksel_rate pclkx2_emu_rates[] = { | |
2916 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2917 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
2918 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
2919 | { .div = 0 }, | |
2920 | }; | |
2921 | ||
2922 | static const struct clksel pclkx2_emu_clksel[] = { | |
2923 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, | |
2924 | { .parent = NULL }, | |
2925 | }; | |
2926 | ||
2927 | static struct clk pclkx2_fck = { | |
2928 | .name = "pclkx2_fck", | |
2929 | .init = &omap2_init_clksel_parent, | |
2930 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2931 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | |
2932 | .clksel = pclkx2_emu_clksel, | |
2933 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
333943ba | 2934 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2935 | .recalc = &omap2_clksel_recalc, |
2936 | }; | |
2937 | ||
2938 | static const struct clksel atclk_emu_clksel[] = { | |
2939 | { .parent = &emu_src_ck, .rates = div2_rates }, | |
2940 | { .parent = NULL }, | |
2941 | }; | |
2942 | ||
2943 | static struct clk atclk_fck = { | |
2944 | .name = "atclk_fck", | |
2945 | .init = &omap2_init_clksel_parent, | |
2946 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2947 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | |
2948 | .clksel = atclk_emu_clksel, | |
2949 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
333943ba | 2950 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2951 | .recalc = &omap2_clksel_recalc, |
2952 | }; | |
2953 | ||
2954 | static struct clk traceclk_src_fck = { | |
2955 | .name = "traceclk_src_fck", | |
2956 | .init = &omap2_init_clksel_parent, | |
2957 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2958 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | |
2959 | .clksel = emu_src_clksel, | |
2960 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
333943ba | 2961 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2962 | .recalc = &omap2_clksel_recalc, |
2963 | }; | |
2964 | ||
2965 | static const struct clksel_rate traceclk_rates[] = { | |
2966 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2967 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
2968 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2969 | { .div = 0 }, | |
2970 | }; | |
2971 | ||
2972 | static const struct clksel traceclk_clksel[] = { | |
2973 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, | |
2974 | { .parent = NULL }, | |
2975 | }; | |
2976 | ||
2977 | static struct clk traceclk_fck = { | |
2978 | .name = "traceclk_fck", | |
2979 | .init = &omap2_init_clksel_parent, | |
2980 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2981 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | |
2982 | .clksel = traceclk_clksel, | |
2983 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | |
333943ba | 2984 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2985 | .recalc = &omap2_clksel_recalc, |
2986 | }; | |
2987 | ||
2988 | /* SR clocks */ | |
2989 | ||
2990 | /* SmartReflex fclk (VDD1) */ | |
2991 | static struct clk sr1_fck = { | |
2992 | .name = "sr1_fck", | |
2993 | .parent = &sys_ck, | |
2994 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2995 | .enable_bit = OMAP3430_EN_SR1_SHIFT, | |
2996 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
2997 | .recalc = &followparent_recalc, | |
2998 | }; | |
2999 | ||
3000 | /* SmartReflex fclk (VDD2) */ | |
3001 | static struct clk sr2_fck = { | |
3002 | .name = "sr2_fck", | |
3003 | .parent = &sys_ck, | |
3004 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
3005 | .enable_bit = OMAP3430_EN_SR2_SHIFT, | |
3006 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
3007 | .recalc = &followparent_recalc, | |
3008 | }; | |
3009 | ||
3010 | static struct clk sr_l4_ick = { | |
3011 | .name = "sr_l4_ick", | |
3012 | .parent = &l4_ick, | |
3013 | .flags = CLOCK_IN_OMAP343X, | |
333943ba | 3014 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
3015 | .recalc = &followparent_recalc, |
3016 | }; | |
3017 | ||
3018 | /* SECURE_32K_FCK clocks */ | |
3019 | ||
333943ba | 3020 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
b045d080 PW |
3021 | static struct clk gpt12_fck = { |
3022 | .name = "gpt12_fck", | |
3023 | .parent = &secure_32k_fck, | |
3024 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | |
3025 | .recalc = &followparent_recalc, | |
3026 | }; | |
3027 | ||
3028 | static struct clk wdt1_fck = { | |
3029 | .name = "wdt1_fck", | |
3030 | .parent = &secure_32k_fck, | |
3031 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | |
3032 | .recalc = &followparent_recalc, | |
3033 | }; | |
3034 | ||
b045d080 PW |
3035 | static struct clk *onchip_34xx_clks[] __initdata = { |
3036 | &omap_32k_fck, | |
3037 | &virt_12m_ck, | |
3038 | &virt_13m_ck, | |
3039 | &virt_16_8m_ck, | |
3040 | &virt_19_2m_ck, | |
3041 | &virt_26m_ck, | |
3042 | &virt_38_4m_ck, | |
3043 | &osc_sys_ck, | |
3044 | &sys_ck, | |
3045 | &sys_altclk, | |
3046 | &mcbsp_clks, | |
3047 | &sys_clkout1, | |
3048 | &dpll1_ck, | |
3760d31f RT |
3049 | &dpll1_x2_ck, |
3050 | &dpll1_x2m2_ck, | |
b045d080 | 3051 | &dpll2_ck, |
3760d31f | 3052 | &dpll2_m2_ck, |
b045d080 PW |
3053 | &dpll3_ck, |
3054 | &core_ck, | |
3055 | &dpll3_x2_ck, | |
3056 | &dpll3_m2_ck, | |
3057 | &dpll3_m2x2_ck, | |
3760d31f | 3058 | &dpll3_m3_ck, |
b045d080 PW |
3059 | &dpll3_m3x2_ck, |
3060 | &emu_core_alwon_ck, | |
3061 | &dpll4_ck, | |
3062 | &dpll4_x2_ck, | |
3063 | &omap_96m_alwon_fck, | |
3064 | &omap_96m_fck, | |
3065 | &cm_96m_fck, | |
3760d31f | 3066 | &virt_omap_54m_fck, |
b045d080 PW |
3067 | &omap_54m_fck, |
3068 | &omap_48m_fck, | |
3069 | &omap_12m_fck, | |
3760d31f | 3070 | &dpll4_m2_ck, |
b045d080 | 3071 | &dpll4_m2x2_ck, |
3760d31f | 3072 | &dpll4_m3_ck, |
b045d080 | 3073 | &dpll4_m3x2_ck, |
3760d31f | 3074 | &dpll4_m4_ck, |
b045d080 | 3075 | &dpll4_m4x2_ck, |
3760d31f | 3076 | &dpll4_m5_ck, |
b045d080 | 3077 | &dpll4_m5x2_ck, |
3760d31f | 3078 | &dpll4_m6_ck, |
b045d080 PW |
3079 | &dpll4_m6x2_ck, |
3080 | &emu_per_alwon_ck, | |
3081 | &dpll5_ck, | |
3082 | &dpll5_m2_ck, | |
3083 | &omap_120m_fck, | |
3084 | &clkout2_src_ck, | |
3085 | &sys_clkout2, | |
3086 | &corex2_fck, | |
3087 | &dpll1_fck, | |
3760d31f RT |
3088 | &mpu_ck, |
3089 | &arm_fck, | |
3090 | &emu_mpu_alwon_ck, | |
b045d080 | 3091 | &dpll2_fck, |
3760d31f | 3092 | &iva2_ck, |
b045d080 PW |
3093 | &l3_ick, |
3094 | &l4_ick, | |
3095 | &rm_ick, | |
3096 | &gfx_l3_fck, | |
3097 | &gfx_l3_ick, | |
3098 | &gfx_cg1_ck, | |
3099 | &gfx_cg2_ck, | |
3100 | &sgx_fck, | |
3101 | &sgx_ick, | |
3102 | &d2d_26m_fck, | |
3103 | &gpt10_fck, | |
3104 | &gpt11_fck, | |
3105 | &cpefuse_fck, | |
3106 | &ts_fck, | |
3107 | &usbtll_fck, | |
3108 | &core_96m_fck, | |
3109 | &mmchs3_fck, | |
3110 | &mmchs2_fck, | |
3111 | &mspro_fck, | |
3112 | &mmchs1_fck, | |
3113 | &i2c3_fck, | |
3114 | &i2c2_fck, | |
3115 | &i2c1_fck, | |
3116 | &mcbsp5_fck, | |
3117 | &mcbsp1_fck, | |
3118 | &core_48m_fck, | |
3119 | &mcspi4_fck, | |
3120 | &mcspi3_fck, | |
3121 | &mcspi2_fck, | |
3122 | &mcspi1_fck, | |
3123 | &uart2_fck, | |
3124 | &uart1_fck, | |
3125 | &fshostusb_fck, | |
3126 | &core_12m_fck, | |
3127 | &hdq_fck, | |
3128 | &ssi_ssr_fck, | |
3129 | &ssi_sst_fck, | |
3130 | &core_l3_ick, | |
3131 | &hsotgusb_ick, | |
3132 | &sdrc_ick, | |
3133 | &gpmc_fck, | |
3134 | &security_l3_ick, | |
3135 | &pka_ick, | |
3136 | &core_l4_ick, | |
3137 | &usbtll_ick, | |
3138 | &mmchs3_ick, | |
3139 | &icr_ick, | |
3140 | &aes2_ick, | |
3141 | &sha12_ick, | |
3142 | &des2_ick, | |
3143 | &mmchs2_ick, | |
3144 | &mmchs1_ick, | |
3145 | &mspro_ick, | |
3146 | &hdq_ick, | |
3147 | &mcspi4_ick, | |
3148 | &mcspi3_ick, | |
3149 | &mcspi2_ick, | |
3150 | &mcspi1_ick, | |
3151 | &i2c3_ick, | |
3152 | &i2c2_ick, | |
3153 | &i2c1_ick, | |
3154 | &uart2_ick, | |
3155 | &uart1_ick, | |
3156 | &gpt11_ick, | |
3157 | &gpt10_ick, | |
3158 | &mcbsp5_ick, | |
3159 | &mcbsp1_ick, | |
3160 | &fac_ick, | |
3161 | &mailboxes_ick, | |
3162 | &omapctrl_ick, | |
3163 | &ssi_l4_ick, | |
3164 | &ssi_ick, | |
3165 | &usb_l4_ick, | |
3166 | &security_l4_ick2, | |
3167 | &aes1_ick, | |
3168 | &rng_ick, | |
3169 | &sha11_ick, | |
3170 | &des1_ick, | |
3171 | &dss1_alwon_fck, | |
3172 | &dss_tv_fck, | |
3173 | &dss_96m_fck, | |
3174 | &dss2_alwon_fck, | |
3175 | &dss_ick, | |
3176 | &cam_mclk, | |
3177 | &cam_l3_ick, | |
3178 | &cam_l4_ick, | |
3179 | &usbhost_120m_fck, | |
3180 | &usbhost_48m_fck, | |
3181 | &usbhost_l3_ick, | |
3182 | &usbhost_l4_ick, | |
3183 | &usbhost_sar_fck, | |
3184 | &usim_fck, | |
3185 | &gpt1_fck, | |
3186 | &wkup_32k_fck, | |
3187 | &gpio1_fck, | |
3188 | &wdt2_fck, | |
3189 | &wkup_l4_ick, | |
3190 | &usim_ick, | |
3191 | &wdt2_ick, | |
3192 | &wdt1_ick, | |
3193 | &gpio1_ick, | |
3194 | &omap_32ksync_ick, | |
3195 | &gpt12_ick, | |
3196 | &gpt1_ick, | |
3197 | &per_96m_fck, | |
3198 | &per_48m_fck, | |
3199 | &uart3_fck, | |
3200 | &gpt2_fck, | |
3201 | &gpt3_fck, | |
3202 | &gpt4_fck, | |
3203 | &gpt5_fck, | |
3204 | &gpt6_fck, | |
3205 | &gpt7_fck, | |
3206 | &gpt8_fck, | |
3207 | &gpt9_fck, | |
3208 | &per_32k_alwon_fck, | |
3209 | &gpio6_fck, | |
3210 | &gpio5_fck, | |
3211 | &gpio4_fck, | |
3212 | &gpio3_fck, | |
3213 | &gpio2_fck, | |
3214 | &wdt3_fck, | |
3215 | &per_l4_ick, | |
3216 | &gpio6_ick, | |
3217 | &gpio5_ick, | |
3218 | &gpio4_ick, | |
3219 | &gpio3_ick, | |
3220 | &gpio2_ick, | |
3221 | &wdt3_ick, | |
3222 | &uart3_ick, | |
3223 | &gpt9_ick, | |
3224 | &gpt8_ick, | |
3225 | &gpt7_ick, | |
3226 | &gpt6_ick, | |
3227 | &gpt5_ick, | |
3228 | &gpt4_ick, | |
3229 | &gpt3_ick, | |
3230 | &gpt2_ick, | |
3231 | &mcbsp2_ick, | |
3232 | &mcbsp3_ick, | |
3233 | &mcbsp4_ick, | |
3234 | &mcbsp2_fck, | |
3235 | &mcbsp3_fck, | |
3236 | &mcbsp4_fck, | |
3237 | &emu_src_ck, | |
3238 | &pclk_fck, | |
3239 | &pclkx2_fck, | |
3240 | &atclk_fck, | |
3241 | &traceclk_src_fck, | |
3242 | &traceclk_fck, | |
3243 | &sr1_fck, | |
3244 | &sr2_fck, | |
3245 | &sr_l4_ick, | |
3246 | &secure_32k_fck, | |
3247 | &gpt12_fck, | |
3248 | &wdt1_fck, | |
3249 | }; | |
3250 | ||
3251 | #endif |