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ARM: OMAP: Add OMAP chip type structure; clean up mach-omap2/id.c
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / clock34xx.h
CommitLineData
b045d080
PW		 1/*
2 * OMAP3 clock framework
3 *
3760d31f
RT		 4 * Virtual clocks are introduced as a convenient tools.
5 * They are sources for other clocks and not supposed
6 * to be requested from drivers directly.
7 *
b045d080
PW		 8 * Copyright (C) 2007-2008 Texas Instruments, Inc.
9 * Copyright (C) 2007-2008 Nokia Corporation
10 *
11 * Written by Paul Walmsley
12 */
13
14#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
15#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
16
17#include <asm/arch/control.h>
18
19#include "clock.h"
20#include "cm.h"
21#include "cm-regbits-34xx.h"
22#include "prm.h"
23#include "prm-regbits-34xx.h"
24
25static void omap3_dpll_recalc(struct clk *clk);
26static void omap3_clkoutx2_recalc(struct clk *clk);
27
28/*
29 * DPLL1 supplies clock to the MPU.
30 * DPLL2 supplies clock to the IVA2.
31 * DPLL3 supplies CORE domain clocks.
32 * DPLL4 supplies peripheral clocks.
33 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
34 */
35
36/* PRM CLOCKS */
37
38/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
39static struct clk omap_32k_fck = {
40 .name = "omap_32k_fck",
41 .rate = 32768,
42 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
43 ALWAYS_ENABLED,
44 .recalc = &propagate_rate,
45};
46
47static struct clk secure_32k_fck = {
48 .name = "secure_32k_fck",
49 .rate = 32768,
50 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
51 ALWAYS_ENABLED,
52 .recalc = &propagate_rate,
53};
54
55/* Virtual source clocks for osc_sys_ck */
56static struct clk virt_12m_ck = {
57 .name = "virt_12m_ck",
58 .rate = 12000000,
59 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
60 ALWAYS_ENABLED,
61 .recalc = &propagate_rate,
62};
63
64static struct clk virt_13m_ck = {
65 .name = "virt_13m_ck",
66 .rate = 13000000,
67 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
68 ALWAYS_ENABLED,
69 .recalc = &propagate_rate,
70};
71
72static struct clk virt_16_8m_ck = {
73 .name = "virt_16_8m_ck",
74 .rate = 16800000,
75 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
76 ALWAYS_ENABLED,
77 .recalc = &propagate_rate,
78};
79
80static struct clk virt_19_2m_ck = {
81 .name = "virt_19_2m_ck",
82 .rate = 19200000,
83 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
84 ALWAYS_ENABLED,
85 .recalc = &propagate_rate,
86};
87
88static struct clk virt_26m_ck = {
89 .name = "virt_26m_ck",
90 .rate = 26000000,
91 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
92 ALWAYS_ENABLED,
93 .recalc = &propagate_rate,
94};
95
96static struct clk virt_38_4m_ck = {
97 .name = "virt_38_4m_ck",
98 .rate = 38400000,
99 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
100 ALWAYS_ENABLED,
101 .recalc = &propagate_rate,
102};
103
104static const struct clksel_rate osc_sys_12m_rates[] = {
105 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
106 { .div = 0 }
107};
108
109static const struct clksel_rate osc_sys_13m_rates[] = {
110 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
111 { .div = 0 }
112};
113
114static const struct clksel_rate osc_sys_16_8m_rates[] = {
115 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
116 { .div = 0 }
117};
118
119static const struct clksel_rate osc_sys_19_2m_rates[] = {
120 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
121 { .div = 0 }
122};
123
124static const struct clksel_rate osc_sys_26m_rates[] = {
125 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
126 { .div = 0 }
127};
128
129static const struct clksel_rate osc_sys_38_4m_rates[] = {
130 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
131 { .div = 0 }
132};
133
134static const struct clksel osc_sys_clksel[] = {
135 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
136 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
137 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
138 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
139 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
140 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
141 { .parent = NULL },
142};
143
144/* Oscillator clock */
145/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
146static struct clk osc_sys_ck = {
147 .name = "osc_sys_ck",
148 .init = &omap2_init_clksel_parent,
149 .clksel_reg = OMAP3430_PRM_CLKSEL,
150 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
151 .clksel = osc_sys_clksel,
152 /* REVISIT: deal with autoextclkmode? */
153 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
154 ALWAYS_ENABLED,
155 .recalc = &omap2_clksel_recalc,
156};
157
158static const struct clksel_rate div2_rates[] = {
159 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
160 { .div = 2, .val = 2, .flags = RATE_IN_343X },
161 { .div = 0 }
162};
163
164static const struct clksel sys_clksel[] = {
165 { .parent = &osc_sys_ck, .rates = div2_rates },
166 { .parent = NULL }
167};
168
169/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
170/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
171static struct clk sys_ck = {
172 .name = "sys_ck",
173 .parent = &osc_sys_ck,
174 .init = &omap2_init_clksel_parent,
175 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
176 .clksel_mask = OMAP_SYSCLKDIV_MASK,
177 .clksel = sys_clksel,
178 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
179 .recalc = &omap2_clksel_recalc,
180};
181
182static struct clk sys_altclk = {
183 .name = "sys_altclk",
184 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
185 .recalc = &propagate_rate,
186};
187
188/* Optional external clock input for some McBSPs */
189static struct clk mcbsp_clks = {
190 .name = "mcbsp_clks",
191 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
192 .recalc = &propagate_rate,
193};
194
195/* PRM EXTERNAL CLOCK OUTPUT */
196
197static struct clk sys_clkout1 = {
198 .name = "sys_clkout1",
199 .parent = &osc_sys_ck,
200 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
201 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
202 .flags = CLOCK_IN_OMAP343X,
203 .recalc = &followparent_recalc,
204};
205
206/* DPLLS */
207
208/* CM CLOCKS */
209
3760d31f
RT		 210static const struct clksel_rate dpll_bypass_rates[] = {
211 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
212 { .div = 0 }
213};
214
215static const struct clksel_rate dpll_locked_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
217 { .div = 0 }
218};
219
220static const struct clksel_rate div16_dpll_rates[] = {
221 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
222 { .div = 2, .val = 2, .flags = RATE_IN_343X },
223 { .div = 3, .val = 3, .flags = RATE_IN_343X },
224 { .div = 4, .val = 4, .flags = RATE_IN_343X },
225 { .div = 5, .val = 5, .flags = RATE_IN_343X },
226 { .div = 6, .val = 6, .flags = RATE_IN_343X },
227 { .div = 7, .val = 7, .flags = RATE_IN_343X },
228 { .div = 8, .val = 8, .flags = RATE_IN_343X },
229 { .div = 9, .val = 9, .flags = RATE_IN_343X },
230 { .div = 10, .val = 10, .flags = RATE_IN_343X },
231 { .div = 11, .val = 11, .flags = RATE_IN_343X },
232 { .div = 12, .val = 12, .flags = RATE_IN_343X },
233 { .div = 13, .val = 13, .flags = RATE_IN_343X },
234 { .div = 14, .val = 14, .flags = RATE_IN_343X },
235 { .div = 15, .val = 15, .flags = RATE_IN_343X },
236 { .div = 16, .val = 16, .flags = RATE_IN_343X },
237 { .div = 0 }
238};
239
b045d080
PW		 240/* DPLL1 */
241/* MPU clock source */
242/* Type: DPLL */
243static const struct dpll_data dpll1_dd = {
244 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
245 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
246 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
b045d080
PW		 247 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
248 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
249 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
250 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
251 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
252};
253
254static struct clk dpll1_ck = {
255 .name = "dpll1_ck",
256 .parent = &sys_ck,
257 .dpll_data = &dpll1_dd,
258 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
259 .recalc = &omap3_dpll_recalc,
260};
261
262/*
3760d31f
RT		 263 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
264 * DPLL isn't bypassed.
b045d080 265 */
3760d31f
RT		 266static struct clk dpll1_x2_ck = {
267 .name = "dpll1_x2_ck",
b045d080
PW		 268 .parent = &dpll1_ck,
269 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
270 PARENT_CONTROLS_CLOCK,
3760d31f
RT		 271 .recalc = &omap3_clkoutx2_recalc,
272};
273
274/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
275static const struct clksel div16_dpll1_x2m2_clksel[] = {
276 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
277 { .parent = NULL }
278};
279
280/*
281 * Does not exist in the TRM - needed to separate the M2 divider from
282 * bypass selection in mpu_ck
283 */
284static struct clk dpll1_x2m2_ck = {
285 .name = "dpll1_x2m2_ck",
286 .parent = &dpll1_x2_ck,
287 .init = &omap2_init_clksel_parent,
288 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
289 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
290 .clksel = div16_dpll1_x2m2_clksel,
291 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
292 PARENT_CONTROLS_CLOCK,
293 .recalc = &omap2_clksel_recalc,
b045d080
PW		 294};
295
296/* DPLL2 */
297/* IVA2 clock source */
298/* Type: DPLL */
299
300static const struct dpll_data dpll2_dd = {
301 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
302 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
303 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
b045d080
PW		 304 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
305 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
306 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
307 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
308 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
309};
310
311static struct clk dpll2_ck = {
312 .name = "dpll2_ck",
313 .parent = &sys_ck,
314 .dpll_data = &dpll2_dd,
315 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
316 .recalc = &omap3_dpll_recalc,
317};
318
3760d31f
RT		 319static const struct clksel div16_dpll2_m2x2_clksel[] = {
320 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
321 { .parent = NULL }
322};
323
324/*
325 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
326 * or CLKOUTX2. CLKOUT seems most plausible.
327 */
328static struct clk dpll2_m2_ck = {
329 .name = "dpll2_m2_ck",
330 .parent = &dpll2_ck,
331 .init = &omap2_init_clksel_parent,
332 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
333 OMAP3430_CM_CLKSEL2_PLL),
334 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
335 .clksel = div16_dpll2_m2x2_clksel,
336 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
337 PARENT_CONTROLS_CLOCK,
338 .recalc = &omap2_clksel_recalc,
339};
340
b045d080
PW		 341/* DPLL3 */
342/* Source clock for all interfaces and for some device fclks */
343/* Type: DPLL */
344static const struct dpll_data dpll3_dd = {
345 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
346 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
347 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
b045d080
PW		 348 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
349 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
350 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
351 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
352 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
353};
354
355static struct clk dpll3_ck = {
356 .name = "dpll3_ck",
357 .parent = &sys_ck,
358 .dpll_data = &dpll3_dd,
359 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
360 .recalc = &omap3_dpll_recalc,
361};
362
3760d31f
RT		 363/*
364 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
365 * DPLL isn't bypassed
366 */
367static struct clk dpll3_x2_ck = {
368 .name = "dpll3_x2_ck",
369 .parent = &dpll3_ck,
370 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
371 PARENT_CONTROLS_CLOCK,
372 .recalc = &omap3_clkoutx2_recalc,
b045d080
PW		 373};
374
375static const struct clksel_rate div31_dpll3_rates[] = {
376 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
377 { .div = 2, .val = 2, .flags = RATE_IN_343X },
378 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
379 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
380 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
381 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
382 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
383 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
384 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
385 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
386 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
387 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
388 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
389 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
390 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
391 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
392 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
393 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
394 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
395 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
396 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
397 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
398 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
399 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
400 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
401 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
402 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
403 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
404 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
405 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
406 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
407 { .div = 0 },
408};
409
410static const struct clksel div31_dpll3m2_clksel[] = {
411 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
412 { .parent = NULL }
413};
414
415/*
3760d31f
RT		 416 * DPLL3 output M2
417 * REVISIT: This DPLL output divider must be changed in SRAM, so until
418 * that code is ready, this should remain a 'read-only' clksel clock.
b045d080
PW		 419 */
420static struct clk dpll3_m2_ck = {
421 .name = "dpll3_m2_ck",
422 .parent = &dpll3_ck,
423 .init = &omap2_init_clksel_parent,
424 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
425 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
426 .clksel = div31_dpll3m2_clksel,
427 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
428 PARENT_CONTROLS_CLOCK,
429 .recalc = &omap2_clksel_recalc,
430};
431
3760d31f
RT		 432static const struct clksel core_ck_clksel[] = {
433 { .parent = &sys_ck, .rates = dpll_bypass_rates },
434 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
435 { .parent = NULL }
436};
437
b045d080
PW		 438static struct clk core_ck = {
439 .name = "core_ck",
3760d31f
RT		 440 .init = &omap2_init_clksel_parent,
441 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
442 .clksel_mask = OMAP3430_ST_CORE_CLK,
443 .clksel = core_ck_clksel,
b045d080
PW		 444 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
445 PARENT_CONTROLS_CLOCK,
3760d31f 446 .recalc = &omap2_clksel_recalc,
b045d080
PW		 447};
448
3760d31f
RT		 449static const struct clksel dpll3_m2x2_ck_clksel[] = {
450 { .parent = &sys_ck, .rates = dpll_bypass_rates },
451 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
452 { .parent = NULL }
b045d080
PW		 453};
454
455static struct clk dpll3_m2x2_ck = {
456 .name = "dpll3_m2x2_ck",
3760d31f
RT		 457 .init = &omap2_init_clksel_parent,
458 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
459 .clksel_mask = OMAP3430_ST_CORE_CLK,
460 .clksel = dpll3_m2x2_ck_clksel,
b045d080
PW		 461 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
462 PARENT_CONTROLS_CLOCK,
3760d31f
RT		 463 .recalc = &omap2_clksel_recalc,
464};
465
466/* The PWRDN bit is apparently only available on 3430ES2 and above */
467static const struct clksel div16_dpll3_clksel[] = {
468 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
469 { .parent = NULL }
470};
471
472/* This virtual clock is the source for dpll3_m3x2_ck */
473static struct clk dpll3_m3_ck = {
474 .name = "dpll3_m3_ck",
475 .parent = &dpll3_ck,
476 .init = &omap2_init_clksel_parent,
477 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
478 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
479 .clksel = div16_dpll3_clksel,
480 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
481 PARENT_CONTROLS_CLOCK,
482 .recalc = &omap2_clksel_recalc,
b045d080
PW		 483};
484
485/* The PWRDN bit is apparently only available on 3430ES2 and above */
486static struct clk dpll3_m3x2_ck = {
487 .name = "dpll3_m3x2_ck",
3760d31f 488 .parent = &dpll3_m3_ck,
b045d080
PW		 489 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
490 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
491 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
3760d31f 492 .recalc = &omap3_clkoutx2_recalc,
b045d080
PW		 493};
494
3760d31f
RT		 495static const struct clksel emu_core_alwon_ck_clksel[] = {
496 { .parent = &sys_ck, .rates = dpll_bypass_rates },
497 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
b045d080
PW		 498 { .parent = NULL }
499};
500
501static struct clk emu_core_alwon_ck = {
502 .name = "emu_core_alwon_ck",
3760d31f 503 .parent = &dpll3_m3x2_ck,
b045d080 504 .init = &omap2_init_clksel_parent,
3760d31f
RT		 505 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
506 .clksel_mask = OMAP3430_ST_CORE_CLK,
507 .clksel = emu_core_alwon_ck_clksel,
508 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
509 PARENT_CONTROLS_CLOCK,
510 .recalc = &omap2_clksel_recalc,
b045d080
PW		 511};
512
513/* DPLL4 */
514/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
515/* Type: DPLL */
516static const struct dpll_data dpll4_dd = {
517 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
518 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
519 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
520 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
521 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
522 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
523 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
524 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
525};
526
527static struct clk dpll4_ck = {
528 .name = "dpll4_ck",
529 .parent = &sys_ck,
530 .dpll_data = &dpll4_dd,
531 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
532 .recalc = &omap3_dpll_recalc,
533};
534
535/*
536 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
3760d31f
RT		 537 * DPLL isn't bypassed --
538 * XXX does this serve any downstream clocks?
b045d080
PW		 539 */
540static struct clk dpll4_x2_ck = {
541 .name = "dpll4_x2_ck",
542 .parent = &dpll4_ck,
543 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
544 PARENT_CONTROLS_CLOCK,
545 .recalc = &omap3_clkoutx2_recalc,
546};
547
548static const struct clksel div16_dpll4_clksel[] = {
3760d31f 549 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
b045d080
PW		 550 { .parent = NULL }
551};
552
3760d31f
RT		 553/* This virtual clock is the source for dpll4_m2x2_ck */
554static struct clk dpll4_m2_ck = {
555 .name = "dpll4_m2_ck",
556 .parent = &dpll4_ck,
557 .init = &omap2_init_clksel_parent,
558 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
559 .clksel_mask = OMAP3430_DIV_96M_MASK,
560 .clksel = div16_dpll4_clksel,
561 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
562 PARENT_CONTROLS_CLOCK,
563 .recalc = &omap2_clksel_recalc,
564};
565
b045d080
PW		 566/* The PWRDN bit is apparently only available on 3430ES2 and above */
567static struct clk dpll4_m2x2_ck = {
568 .name = "dpll4_m2x2_ck",
3760d31f 569 .parent = &dpll4_m2_ck,
b045d080
PW		 570 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
571 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
b045d080 572 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
3760d31f
RT		 573 .recalc = &omap3_clkoutx2_recalc,
574};
575
576static const struct clksel omap_96m_alwon_fck_clksel[] = {
577 { .parent = &sys_ck, .rates = dpll_bypass_rates },
578 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
579 { .parent = NULL }
b045d080
PW		 580};
581
582static struct clk omap_96m_alwon_fck = {
583 .name = "omap_96m_alwon_fck",
584 .parent = &dpll4_m2x2_ck,
3760d31f
RT		 585 .init = &omap2_init_clksel_parent,
586 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
587 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
588 .clksel = omap_96m_alwon_fck_clksel,
b045d080
PW		 589 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
590 PARENT_CONTROLS_CLOCK,
3760d31f 591 .recalc = &omap2_clksel_recalc,
b045d080
PW		 592};
593
594static struct clk omap_96m_fck = {
595 .name = "omap_96m_fck",
596 .parent = &omap_96m_alwon_fck,
597 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
598 PARENT_CONTROLS_CLOCK,
599 .recalc = &followparent_recalc,
600};
601
3760d31f
RT		 602static const struct clksel cm_96m_fck_clksel[] = {
603 { .parent = &sys_ck, .rates = dpll_bypass_rates },
604 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
605 { .parent = NULL }
606};
607
b045d080
PW		 608static struct clk cm_96m_fck = {
609 .name = "cm_96m_fck",
610 .parent = &dpll4_m2x2_ck,
3760d31f
RT		 611 .init = &omap2_init_clksel_parent,
612 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
613 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
614 .clksel = cm_96m_fck_clksel,
b045d080
PW		 615 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
616 PARENT_CONTROLS_CLOCK,
3760d31f
RT		 617 .recalc = &omap2_clksel_recalc,
618};
619
620/* This virtual clock is the source for dpll4_m3x2_ck */
621static struct clk dpll4_m3_ck = {
622 .name = "dpll4_m3_ck",
623 .parent = &dpll4_ck,
624 .init = &omap2_init_clksel_parent,
625 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
626 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
627 .clksel = div16_dpll4_clksel,
628 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
629 PARENT_CONTROLS_CLOCK,
630 .recalc = &omap2_clksel_recalc,
b045d080
PW		 631};
632
633/* The PWRDN bit is apparently only available on 3430ES2 and above */
634static struct clk dpll4_m3x2_ck = {
635 .name = "dpll4_m3x2_ck",
3760d31f 636 .parent = &dpll4_m3_ck,
b045d080
PW		 637 .init = &omap2_init_clksel_parent,
638 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
639 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
b045d080 640 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
3760d31f
RT		 641 .recalc = &omap3_clkoutx2_recalc,
642};
643
644static const struct clksel virt_omap_54m_fck_clksel[] = {
645 { .parent = &sys_ck, .rates = dpll_bypass_rates },
646 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
647 { .parent = NULL }
648};
649
650static struct clk virt_omap_54m_fck = {
651 .name = "virt_omap_54m_fck",
652 .parent = &dpll4_m3x2_ck,
653 .init = &omap2_init_clksel_parent,
654 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
655 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
656 .clksel = virt_omap_54m_fck_clksel,
657 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
658 PARENT_CONTROLS_CLOCK,
b045d080
PW		 659 .recalc = &omap2_clksel_recalc,
660};
661
662static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
663 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
664 { .div = 0 }
665};
666
667static const struct clksel_rate omap_54m_alt_rates[] = {
668 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
669 { .div = 0 }
670};
671
672static const struct clksel omap_54m_clksel[] = {
3760d31f 673 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
b045d080
PW		 674 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
675 { .parent = NULL }
676};
677
678static struct clk omap_54m_fck = {
679 .name = "omap_54m_fck",
680 .init = &omap2_init_clksel_parent,
681 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
682 .clksel_mask = OMAP3430_SOURCE_54M,
683 .clksel = omap_54m_clksel,
684 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
685 PARENT_CONTROLS_CLOCK,
686 .recalc = &omap2_clksel_recalc,
687};
688
689static const struct clksel_rate omap_48m_96md2_rates[] = {
690 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
691 { .div = 0 }
692};
693
694static const struct clksel_rate omap_48m_alt_rates[] = {
695 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
696 { .div = 0 }
697};
698
699static const struct clksel omap_48m_clksel[] = {
700 { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
701 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
702 { .parent = NULL }
703};
704
705static struct clk omap_48m_fck = {
706 .name = "omap_48m_fck",
707 .init = &omap2_init_clksel_parent,
708 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
709 .clksel_mask = OMAP3430_SOURCE_48M,
710 .clksel = omap_48m_clksel,
711 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
712 PARENT_CONTROLS_CLOCK,
713 .recalc = &omap2_clksel_recalc,
714};
715
716static struct clk omap_12m_fck = {
717 .name = "omap_12m_fck",
718 .parent = &omap_48m_fck,
719 .fixed_div = 4,
720 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
721 PARENT_CONTROLS_CLOCK,
722 .recalc = &omap2_fixed_divisor_recalc,
723};
724
3760d31f
RT		 725/* This virstual clock is the source for dpll4_m4x2_ck */
726static struct clk dpll4_m4_ck = {
727 .name = "dpll4_m4_ck",
728 .parent = &dpll4_ck,
729 .init = &omap2_init_clksel_parent,
730 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
731 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
732 .clksel = div16_dpll4_clksel,
733 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
734 PARENT_CONTROLS_CLOCK,
735 .recalc = &omap2_clksel_recalc,
736};
737
b045d080
PW		 738/* The PWRDN bit is apparently only available on 3430ES2 and above */
739static struct clk dpll4_m4x2_ck = {
740 .name = "dpll4_m4x2_ck",
3760d31f 741 .parent = &dpll4_m4_ck,
b045d080
PW		 742 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
743 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
b045d080 744 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
3760d31f
RT		 745 .recalc = &omap3_clkoutx2_recalc,
746};
747
748/* This virtual clock is the source for dpll4_m5x2_ck */
749static struct clk dpll4_m5_ck = {
750 .name = "dpll4_m5_ck",
751 .parent = &dpll4_ck,
752 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
754 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
755 .clksel = div16_dpll4_clksel,
756 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
757 PARENT_CONTROLS_CLOCK,
b045d080
PW		 758 .recalc = &omap2_clksel_recalc,
759};
760
761/* The PWRDN bit is apparently only available on 3430ES2 and above */
762static struct clk dpll4_m5x2_ck = {
763 .name = "dpll4_m5x2_ck",
3760d31f 764 .parent = &dpll4_m5_ck,
b045d080
PW		 765 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
766 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
b045d080 767 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
3760d31f
RT		 768 .recalc = &omap3_clkoutx2_recalc,
769};
770
771/* This virtual clock is the source for dpll4_m6x2_ck */
772static struct clk dpll4_m6_ck = {
773 .name = "dpll4_m6_ck",
774 .parent = &dpll4_ck,
775 .init = &omap2_init_clksel_parent,
776 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
777 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
778 .clksel = div16_dpll4_clksel,
779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
780 PARENT_CONTROLS_CLOCK,
b045d080
PW		 781 .recalc = &omap2_clksel_recalc,
782};
783
784/* The PWRDN bit is apparently only available on 3430ES2 and above */
785static struct clk dpll4_m6x2_ck = {
786 .name = "dpll4_m6x2_ck",
3760d31f 787 .parent = &dpll4_m6_ck,
b045d080
PW		 788 .init = &omap2_init_clksel_parent,
789 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
790 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
b045d080 791 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
3760d31f 792 .recalc = &omap3_clkoutx2_recalc,
b045d080
PW		 793};
794
795static struct clk emu_per_alwon_ck = {
796 .name = "emu_per_alwon_ck",
797 .parent = &dpll4_m6x2_ck,
798 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
799 PARENT_CONTROLS_CLOCK,
800 .recalc = &followparent_recalc,
801};
802
803/* DPLL5 */
804/* Supplies 120MHz clock, USIM source clock */
805/* Type: DPLL */
806/* 3430ES2 only */
807static const struct dpll_data dpll5_dd = {
808 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
809 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
810 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
811 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
812 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
813 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
814 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
815 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
816};
817
818static struct clk dpll5_ck = {
819 .name = "dpll5_ck",
820 .parent = &sys_ck,
821 .dpll_data = &dpll5_dd,
822 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
823 ALWAYS_ENABLED,
824 .recalc = &omap3_dpll_recalc,
825};
826
3760d31f 827static const struct clksel div16_dpll5_clksel[] = {
b045d080
PW		 828 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
829 { .parent = NULL }
830};
831
832static struct clk dpll5_m2_ck = {
833 .name = "dpll5_m2_ck",
834 .parent = &dpll5_ck,
835 .init = &omap2_init_clksel_parent,
836 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
837 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
3760d31f 838 .clksel = div16_dpll5_clksel,
d756f54e
HJ		 839 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
840 PARENT_CONTROLS_CLOCK,
b045d080
PW		 841 .recalc = &omap2_clksel_recalc,
842};
843
3760d31f
RT		 844static const struct clksel omap_120m_fck_clksel[] = {
845 { .parent = &sys_ck, .rates = dpll_bypass_rates },
846 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
847 { .parent = NULL }
848};
849
b045d080
PW		 850static struct clk omap_120m_fck = {
851 .name = "omap_120m_fck",
852 .parent = &dpll5_m2_ck,
3760d31f
RT		 853 .init = &omap2_init_clksel_parent,
854 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
855 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
856 .clksel = omap_120m_fck_clksel,
857 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
858 PARENT_CONTROLS_CLOCK,
859 .recalc = &omap2_clksel_recalc,
b045d080
PW		 860};
861
862/* CM EXTERNAL CLOCK OUTPUTS */
863
864static const struct clksel_rate clkout2_src_core_rates[] = {
865 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
866 { .div = 0 }
867};
868
869static const struct clksel_rate clkout2_src_sys_rates[] = {
870 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
871 { .div = 0 }
872};
873
874static const struct clksel_rate clkout2_src_96m_rates[] = {
875 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
876 { .div = 0 }
877};
878
879static const struct clksel_rate clkout2_src_54m_rates[] = {
880 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
881 { .div = 0 }
882};
883
884static const struct clksel clkout2_src_clksel[] = {
885 { .parent = &core_ck, .rates = clkout2_src_core_rates },
886 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
887 { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates },
888 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
889 { .parent = NULL }
890};
891
892static struct clk clkout2_src_ck = {
893 .name = "clkout2_src_ck",
894 .init = &omap2_init_clksel_parent,
895 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
896 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
897 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
898 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
899 .clksel = clkout2_src_clksel,
900 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
901 .recalc = &omap2_clksel_recalc,
902};
903
904static const struct clksel_rate sys_clkout2_rates[] = {
905 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
906 { .div = 2, .val = 1, .flags = RATE_IN_343X },
907 { .div = 4, .val = 2, .flags = RATE_IN_343X },
908 { .div = 8, .val = 3, .flags = RATE_IN_343X },
909 { .div = 16, .val = 4, .flags = RATE_IN_343X },
910 { .div = 0 },
911};
912
913static const struct clksel sys_clkout2_clksel[] = {
914 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
915 { .parent = NULL },
916};
917
918static struct clk sys_clkout2 = {
919 .name = "sys_clkout2",
920 .init = &omap2_init_clksel_parent,
921 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
922 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
923 .clksel = sys_clkout2_clksel,
924 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
925 .recalc = &omap2_clksel_recalc,
926};
927
928/* CM OUTPUT CLOCKS */
929
930static struct clk corex2_fck = {
931 .name = "corex2_fck",
932 .parent = &dpll3_m2x2_ck,
933 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
934 PARENT_CONTROLS_CLOCK,
935 .recalc = &followparent_recalc,
936};
937
938/* DPLL power domain clock controls */
939
940static const struct clksel div2_core_clksel[] = {
941 { .parent = &core_ck, .rates = div2_rates },
942 { .parent = NULL }
943};
944
3760d31f
RT		 945/*
946 * REVISIT: Are these in DPLL power domain or CM power domain? docs
947 * may be inconsistent here?
948 */
b045d080
PW		 949static struct clk dpll1_fck = {
950 .name = "dpll1_fck",
951 .parent = &core_ck,
952 .init = &omap2_init_clksel_parent,
953 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
954 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
955 .clksel = div2_core_clksel,
956 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
957 PARENT_CONTROLS_CLOCK,
958 .recalc = &omap2_clksel_recalc,
959};
960
3760d31f
RT		 961/*
962 * MPU clksel:
963 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
964 * derives from the high-frequency bypass clock originating from DPLL3,
965 * called 'dpll1_fck'
966 */
967static const struct clksel mpu_clksel[] = {
968 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
969 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
970 { .parent = NULL }
971};
972
973static struct clk mpu_ck = {
974 .name = "mpu_ck",
975 .parent = &dpll1_x2m2_ck,
976 .init = &omap2_init_clksel_parent,
977 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
978 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
979 .clksel = mpu_clksel,
980 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
981 PARENT_CONTROLS_CLOCK,
982 .recalc = &omap2_clksel_recalc,
983};
984
985/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
986static const struct clksel_rate arm_fck_rates[] = {
987 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
988 { .div = 2, .val = 1, .flags = RATE_IN_343X },
989 { .div = 0 },
990};
991
992static const struct clksel arm_fck_clksel[] = {
993 { .parent = &mpu_ck, .rates = arm_fck_rates },
994 { .parent = NULL }
995};
996
997static struct clk arm_fck = {
998 .name = "arm_fck",
999 .parent = &mpu_ck,
1000 .init = &omap2_init_clksel_parent,
1001 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1002 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1003 .clksel = arm_fck_clksel,
1004 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1005 PARENT_CONTROLS_CLOCK,
1006 .recalc = &omap2_clksel_recalc,
1007};
1008
1009/*
1010 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1011 * although it is referenced - so this is a guess
1012 */
1013static struct clk emu_mpu_alwon_ck = {
1014 .name = "emu_mpu_alwon_ck",
1015 .parent = &mpu_ck,
1016 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1017 PARENT_CONTROLS_CLOCK,
1018 .recalc = &followparent_recalc,
1019};
1020
b045d080
PW		 1021static struct clk dpll2_fck = {
1022 .name = "dpll2_fck",
1023 .parent = &core_ck,
1024 .init = &omap2_init_clksel_parent,
1025 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1026 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1027 .clksel = div2_core_clksel,
1028 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1029 PARENT_CONTROLS_CLOCK,
1030 .recalc = &omap2_clksel_recalc,
1031};
1032
3760d31f
RT		 1033/*
1034 * IVA2 clksel:
1035 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1036 * derives from the high-frequency bypass clock originating from DPLL3,
1037 * called 'dpll2_fck'
1038 */
1039
1040static const struct clksel iva2_clksel[] = {
1041 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1042 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1043 { .parent = NULL }
1044};
1045
1046static struct clk iva2_ck = {
1047 .name = "iva2_ck",
1048 .parent = &dpll2_m2_ck,
1049 .init = &omap2_init_clksel_parent,
31c203d4
HD		 1050 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1051 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
3760d31f
RT		 1052 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1053 OMAP3430_CM_IDLEST_PLL),
1054 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1055 .clksel = iva2_clksel,
31c203d4 1056 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3760d31f
RT		 1057 .recalc = &omap2_clksel_recalc,
1058};
1059
b045d080
PW		 1060/* Common interface clocks */
1061
1062static struct clk l3_ick = {
1063 .name = "l3_ick",
1064 .parent = &core_ck,
1065 .init = &omap2_init_clksel_parent,
1066 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1067 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1068 .clksel = div2_core_clksel,
1069 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1070 PARENT_CONTROLS_CLOCK,
1071 .recalc = &omap2_clksel_recalc,
1072};
1073
1074static const struct clksel div2_l3_clksel[] = {
1075 { .parent = &l3_ick, .rates = div2_rates },
1076 { .parent = NULL }
1077};
1078
1079static struct clk l4_ick = {
1080 .name = "l4_ick",
1081 .parent = &l3_ick,
1082 .init = &omap2_init_clksel_parent,
1083 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1084 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1085 .clksel = div2_l3_clksel,
1086 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1087 PARENT_CONTROLS_CLOCK,
1088 .recalc = &omap2_clksel_recalc,
1089
1090};
1091
1092static const struct clksel div2_l4_clksel[] = {
1093 { .parent = &l4_ick, .rates = div2_rates },
1094 { .parent = NULL }
1095};
1096
1097static struct clk rm_ick = {
1098 .name = "rm_ick",
1099 .parent = &l4_ick,
1100 .init = &omap2_init_clksel_parent,
1101 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1102 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1103 .clksel = div2_l4_clksel,
1104 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1105 .recalc = &omap2_clksel_recalc,
1106};
1107
1108/* GFX power domain */
1109
3760d31f 1110/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
b045d080
PW		 1111
1112static const struct clksel gfx_l3_clksel[] = {
1113 { .parent = &l3_ick, .rates = gfx_l3_rates },
1114 { .parent = NULL }
1115};
1116
1117static struct clk gfx_l3_fck = {
1118 .name = "gfx_l3_fck",
1119 .parent = &l3_ick,
1120 .init = &omap2_init_clksel_parent,
1121 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1122 .enable_bit = OMAP_EN_GFX_SHIFT,
1123 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1124 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1125 .clksel = gfx_l3_clksel,
1126 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1127 .recalc = &omap2_clksel_recalc,
1128};
1129
1130static struct clk gfx_l3_ick = {
1131 .name = "gfx_l3_ick",
1132 .parent = &l3_ick,
1133 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1134 .enable_bit = OMAP_EN_GFX_SHIFT,
1135 .flags = CLOCK_IN_OMAP3430ES1,
1136 .recalc = &followparent_recalc,
1137};
1138
1139static struct clk gfx_cg1_ck = {
1140 .name = "gfx_cg1_ck",
1141 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1142 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1143 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1144 .flags = CLOCK_IN_OMAP3430ES1,
1145 .recalc = &followparent_recalc,
1146};
1147
1148static struct clk gfx_cg2_ck = {
1149 .name = "gfx_cg2_ck",
1150 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1151 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1152 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1153 .flags = CLOCK_IN_OMAP3430ES1,
1154 .recalc = &followparent_recalc,
1155};
1156
1157/* SGX power domain - 3430ES2 only */
1158
1159static const struct clksel_rate sgx_core_rates[] = {
1160 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1161 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1162 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1163 { .div = 0 },
1164};
1165
1166static const struct clksel_rate sgx_96m_rates[] = {
1167 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1168 { .div = 0 },
1169};
1170
1171static const struct clksel sgx_clksel[] = {
1172 { .parent = &core_ck, .rates = sgx_core_rates },
1173 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1174 { .parent = NULL },
1175};
1176
1177static struct clk sgx_fck = {
1178 .name = "sgx_fck",
1179 .init = &omap2_init_clksel_parent,
1180 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1181 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1182 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1183 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1184 .clksel = sgx_clksel,
1185 .flags = CLOCK_IN_OMAP3430ES2,
1186 .recalc = &omap2_clksel_recalc,
1187};
1188
1189static struct clk sgx_ick = {
1190 .name = "sgx_ick",
1191 .parent = &l3_ick,
1192 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1193 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1194 .flags = CLOCK_IN_OMAP3430ES2,
1195 .recalc = &followparent_recalc,
1196};
1197
1198/* CORE power domain */
1199
1200static struct clk d2d_26m_fck = {
1201 .name = "d2d_26m_fck",
1202 .parent = &sys_ck,
1203 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1204 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1205 .flags = CLOCK_IN_OMAP3430ES1,
1206 .recalc = &followparent_recalc,
1207};
1208
1209static const struct clksel omap343x_gpt_clksel[] = {
1210 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1211 { .parent = &sys_ck, .rates = gpt_sys_rates },
1212 { .parent = NULL}
1213};
1214
1215static struct clk gpt10_fck = {
1216 .name = "gpt10_fck",
1217 .parent = &sys_ck,
1218 .init = &omap2_init_clksel_parent,
1219 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1220 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1221 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1222 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1223 .clksel = omap343x_gpt_clksel,
1224 .flags = CLOCK_IN_OMAP343X,
1225 .recalc = &omap2_clksel_recalc,
1226};
1227
1228static struct clk gpt11_fck = {
1229 .name = "gpt11_fck",
1230 .parent = &sys_ck,
1231 .init = &omap2_init_clksel_parent,
1232 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1233 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1234 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1235 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1236 .clksel = omap343x_gpt_clksel,
1237 .flags = CLOCK_IN_OMAP343X,
1238 .recalc = &omap2_clksel_recalc,
1239};
1240
1241static struct clk cpefuse_fck = {
1242 .name = "cpefuse_fck",
1243 .parent = &sys_ck,
1244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1245 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1246 .flags = CLOCK_IN_OMAP3430ES2,
1247 .recalc = &followparent_recalc,
1248};
1249
1250static struct clk ts_fck = {
1251 .name = "ts_fck",
1252 .parent = &omap_32k_fck,
1253 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1254 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1255 .flags = CLOCK_IN_OMAP3430ES2,
1256 .recalc = &followparent_recalc,
1257};
1258
1259static struct clk usbtll_fck = {
1260 .name = "usbtll_fck",
1261 .parent = &omap_120m_fck,
1262 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1263 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1264 .flags = CLOCK_IN_OMAP3430ES2,
1265 .recalc = &followparent_recalc,
1266};
1267
1268/* CORE 96M FCLK-derived clocks */
1269
1270static struct clk core_96m_fck = {
1271 .name = "core_96m_fck",
1272 .parent = &omap_96m_fck,
1273 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1274 PARENT_CONTROLS_CLOCK,
1275 .recalc = &followparent_recalc,
1276};
1277
1278static struct clk mmchs3_fck = {
1279 .name = "mmchs_fck",
1280 .id = 3,
1281 .parent = &core_96m_fck,
1282 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1283 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1284 .flags = CLOCK_IN_OMAP3430ES2,
1285 .recalc = &followparent_recalc,
1286};
1287
1288static struct clk mmchs2_fck = {
1289 .name = "mmchs_fck",
1290 .id = 2,
1291 .parent = &core_96m_fck,
1292 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1293 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1294 .flags = CLOCK_IN_OMAP343X,
1295 .recalc = &followparent_recalc,
1296};
1297
1298static struct clk mspro_fck = {
1299 .name = "mspro_fck",
1300 .parent = &core_96m_fck,
1301 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1302 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1303 .flags = CLOCK_IN_OMAP343X,
1304 .recalc = &followparent_recalc,
1305};
1306
1307static struct clk mmchs1_fck = {
1308 .name = "mmchs_fck",
1309 .id = 1,
1310 .parent = &core_96m_fck,
1311 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1312 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1313 .flags = CLOCK_IN_OMAP343X,
1314 .recalc = &followparent_recalc,
1315};
1316
1317static struct clk i2c3_fck = {
1318 .name = "i2c_fck",
1319 .id = 3,
1320 .parent = &core_96m_fck,
1321 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1322 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1323 .flags = CLOCK_IN_OMAP343X,
1324 .recalc = &followparent_recalc,
1325};
1326
1327static struct clk i2c2_fck = {
1328 .name = "i2c_fck",
1329 .id = 2,
1330 .parent = &core_96m_fck,
1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1332 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1333 .flags = CLOCK_IN_OMAP343X,
1334 .recalc = &followparent_recalc,
1335};
1336
1337static struct clk i2c1_fck = {
1338 .name = "i2c_fck",
1339 .id = 1,
1340 .parent = &core_96m_fck,
1341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1342 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1343 .flags = CLOCK_IN_OMAP343X,
1344 .recalc = &followparent_recalc,
1345};
1346
1347/*
1348 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1349 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1350 */
1351static const struct clksel_rate common_mcbsp_96m_rates[] = {
1352 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1353 { .div = 0 }
1354};
1355
1356static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1357 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1358 { .div = 0 }
1359};
1360
1361static const struct clksel mcbsp_15_clksel[] = {
1362 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1363 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1364 { .parent = NULL }
1365};
1366
1367static struct clk mcbsp5_fck = {
78673bc8
EV		 1368 .name = "mcbsp_fck",
1369 .id = 5,
b045d080
PW		 1370 .init = &omap2_init_clksel_parent,
1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1372 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1373 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1374 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1375 .clksel = mcbsp_15_clksel,
1376 .flags = CLOCK_IN_OMAP343X,
1377 .recalc = &omap2_clksel_recalc,
1378};
1379
1380static struct clk mcbsp1_fck = {
78673bc8
EV		 1381 .name = "mcbsp_fck",
1382 .id = 1,
b045d080
PW		 1383 .init = &omap2_init_clksel_parent,
1384 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1385 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1386 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1387 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1388 .clksel = mcbsp_15_clksel,
1389 .flags = CLOCK_IN_OMAP343X,
1390 .recalc = &omap2_clksel_recalc,
1391};
1392
1393/* CORE_48M_FCK-derived clocks */
1394
1395static struct clk core_48m_fck = {
1396 .name = "core_48m_fck",
1397 .parent = &omap_48m_fck,
1398 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1399 PARENT_CONTROLS_CLOCK,
1400 .recalc = &followparent_recalc,
1401};
1402
1403static struct clk mcspi4_fck = {
1404 .name = "mcspi_fck",
1405 .id = 4,
1406 .parent = &core_48m_fck,
1407 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1408 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1409 .flags = CLOCK_IN_OMAP343X,
1410 .recalc = &followparent_recalc,
1411};
1412
1413static struct clk mcspi3_fck = {
1414 .name = "mcspi_fck",
1415 .id = 3,
1416 .parent = &core_48m_fck,
1417 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1418 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1419 .flags = CLOCK_IN_OMAP343X,
1420 .recalc = &followparent_recalc,
1421};
1422
1423static struct clk mcspi2_fck = {
1424 .name = "mcspi_fck",
1425 .id = 2,
1426 .parent = &core_48m_fck,
1427 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1428 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1429 .flags = CLOCK_IN_OMAP343X,
1430 .recalc = &followparent_recalc,
1431};
1432
1433static struct clk mcspi1_fck = {
1434 .name = "mcspi_fck",
1435 .id = 1,
1436 .parent = &core_48m_fck,
1437 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1438 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1439 .flags = CLOCK_IN_OMAP343X,
1440 .recalc = &followparent_recalc,
1441};
1442
1443static struct clk uart2_fck = {
1444 .name = "uart2_fck",
1445 .parent = &core_48m_fck,
1446 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1447 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1448 .flags = CLOCK_IN_OMAP343X,
1449 .recalc = &followparent_recalc,
1450};
1451
1452static struct clk uart1_fck = {
1453 .name = "uart1_fck",
1454 .parent = &core_48m_fck,
1455 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1456 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1457 .flags = CLOCK_IN_OMAP343X,
1458 .recalc = &followparent_recalc,
1459};
1460
1461static struct clk fshostusb_fck = {
1462 .name = "fshostusb_fck",
1463 .parent = &core_48m_fck,
1464 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1465 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1466 .flags = CLOCK_IN_OMAP3430ES1,
1467 .recalc = &followparent_recalc,
1468};
1469
1470/* CORE_12M_FCK based clocks */
1471
1472static struct clk core_12m_fck = {
1473 .name = "core_12m_fck",
1474 .parent = &omap_12m_fck,
1475 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1476 PARENT_CONTROLS_CLOCK,
1477 .recalc = &followparent_recalc,
1478};
1479
1480static struct clk hdq_fck = {
1481 .name = "hdq_fck",
1482 .parent = &core_12m_fck,
1483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1484 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1485 .flags = CLOCK_IN_OMAP343X,
1486 .recalc = &followparent_recalc,
1487};
1488
1489/* DPLL3-derived clock */
1490
1491static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1492 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1493 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1494 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1495 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1496 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1497 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1498 { .div = 0 }
1499};
1500
1501static const struct clksel ssi_ssr_clksel[] = {
1502 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1503 { .parent = NULL }
1504};
1505
1506static struct clk ssi_ssr_fck = {
1507 .name = "ssi_ssr_fck",
1508 .init = &omap2_init_clksel_parent,
1509 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1510 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1511 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1512 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1513 .clksel = ssi_ssr_clksel,
1514 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1515 .recalc = &omap2_clksel_recalc,
1516};
1517
1518static struct clk ssi_sst_fck = {
1519 .name = "ssi_sst_fck",
1520 .parent = &ssi_ssr_fck,
1521 .fixed_div = 2,
1522 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1523 .recalc = &omap2_fixed_divisor_recalc,
1524};
1525
1526
1527
1528/* CORE_L3_ICK based clocks */
1529
1530static struct clk core_l3_ick = {
1531 .name = "core_l3_ick",
1532 .parent = &l3_ick,
1533 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1534 PARENT_CONTROLS_CLOCK,
1535 .recalc = &followparent_recalc,
1536};
1537
1538static struct clk hsotgusb_ick = {
1539 .name = "hsotgusb_ick",
1540 .parent = &core_l3_ick,
1541 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1542 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1543 .flags = CLOCK_IN_OMAP343X,
1544 .recalc = &followparent_recalc,
1545};
1546
1547static struct clk sdrc_ick = {
1548 .name = "sdrc_ick",
1549 .parent = &core_l3_ick,
1550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1551 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1552 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1553 .recalc = &followparent_recalc,
1554};
1555
1556static struct clk gpmc_fck = {
1557 .name = "gpmc_fck",
1558 .parent = &core_l3_ick,
1559 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1560 ENABLE_ON_INIT,
1561 .recalc = &followparent_recalc,
1562};
1563
1564/* SECURITY_L3_ICK based clocks */
1565
1566static struct clk security_l3_ick = {
1567 .name = "security_l3_ick",
1568 .parent = &l3_ick,
1569 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1570 PARENT_CONTROLS_CLOCK,
1571 .recalc = &followparent_recalc,
1572};
1573
1574static struct clk pka_ick = {
1575 .name = "pka_ick",
1576 .parent = &security_l3_ick,
1577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1578 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1579 .flags = CLOCK_IN_OMAP343X,
1580 .recalc = &followparent_recalc,
1581};
1582
1583/* CORE_L4_ICK based clocks */
1584
1585static struct clk core_l4_ick = {
1586 .name = "core_l4_ick",
1587 .parent = &l4_ick,
1588 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1589 PARENT_CONTROLS_CLOCK,
1590 .recalc = &followparent_recalc,
1591};
1592
1593static struct clk usbtll_ick = {
1594 .name = "usbtll_ick",
1595 .parent = &core_l4_ick,
1596 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1597 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1598 .flags = CLOCK_IN_OMAP3430ES2,
1599 .recalc = &followparent_recalc,
1600};
1601
1602static struct clk mmchs3_ick = {
1603 .name = "mmchs_ick",
1604 .id = 3,
1605 .parent = &core_l4_ick,
1606 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1607 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1608 .flags = CLOCK_IN_OMAP3430ES2,
1609 .recalc = &followparent_recalc,
1610};
1611
1612/* Intersystem Communication Registers - chassis mode only */
1613static struct clk icr_ick = {
1614 .name = "icr_ick",
1615 .parent = &core_l4_ick,
1616 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1617 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1618 .flags = CLOCK_IN_OMAP343X,
1619 .recalc = &followparent_recalc,
1620};
1621
1622static struct clk aes2_ick = {
1623 .name = "aes2_ick",
1624 .parent = &core_l4_ick,
1625 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1626 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1627 .flags = CLOCK_IN_OMAP343X,
1628 .recalc = &followparent_recalc,
1629};
1630
1631static struct clk sha12_ick = {
1632 .name = "sha12_ick",
1633 .parent = &core_l4_ick,
1634 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1635 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1636 .flags = CLOCK_IN_OMAP343X,
1637 .recalc = &followparent_recalc,
1638};
1639
1640static struct clk des2_ick = {
1641 .name = "des2_ick",
1642 .parent = &core_l4_ick,
1643 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1644 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1645 .flags = CLOCK_IN_OMAP343X,
1646 .recalc = &followparent_recalc,
1647};
1648
1649static struct clk mmchs2_ick = {
1650 .name = "mmchs_ick",
1651 .id = 2,
1652 .parent = &core_l4_ick,
1653 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1654 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1655 .flags = CLOCK_IN_OMAP343X,
1656 .recalc = &followparent_recalc,
1657};
1658
1659static struct clk mmchs1_ick = {
1660 .name = "mmchs_ick",
1661 .id = 1,
1662 .parent = &core_l4_ick,
1663 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1664 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1665 .flags = CLOCK_IN_OMAP343X,
1666 .recalc = &followparent_recalc,
1667};
1668
1669static struct clk mspro_ick = {
1670 .name = "mspro_ick",
1671 .parent = &core_l4_ick,
1672 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1673 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1674 .flags = CLOCK_IN_OMAP343X,
1675 .recalc = &followparent_recalc,
1676};
1677
1678static struct clk hdq_ick = {
1679 .name = "hdq_ick",
1680 .parent = &core_l4_ick,
1681 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1682 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1683 .flags = CLOCK_IN_OMAP343X,
1684 .recalc = &followparent_recalc,
1685};
1686
1687static struct clk mcspi4_ick = {
1688 .name = "mcspi_ick",
1689 .id = 4,
1690 .parent = &core_l4_ick,
1691 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1692 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1693 .flags = CLOCK_IN_OMAP343X,
1694 .recalc = &followparent_recalc,
1695};
1696
1697static struct clk mcspi3_ick = {
1698 .name = "mcspi_ick",
1699 .id = 3,
1700 .parent = &core_l4_ick,
1701 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1702 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1703 .flags = CLOCK_IN_OMAP343X,
1704 .recalc = &followparent_recalc,
1705};
1706
1707static struct clk mcspi2_ick = {
1708 .name = "mcspi_ick",
1709 .id = 2,
1710 .parent = &core_l4_ick,
1711 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1712 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1713 .flags = CLOCK_IN_OMAP343X,
1714 .recalc = &followparent_recalc,
1715};
1716
1717static struct clk mcspi1_ick = {
1718 .name = "mcspi_ick",
1719 .id = 1,
1720 .parent = &core_l4_ick,
1721 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1722 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1723 .flags = CLOCK_IN_OMAP343X,
1724 .recalc = &followparent_recalc,
1725};
1726
1727static struct clk i2c3_ick = {
1728 .name = "i2c_ick",
1729 .id = 3,
1730 .parent = &core_l4_ick,
1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1732 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1733 .flags = CLOCK_IN_OMAP343X,
1734 .recalc = &followparent_recalc,
1735};
1736
1737static struct clk i2c2_ick = {
1738 .name = "i2c_ick",
1739 .id = 2,
1740 .parent = &core_l4_ick,
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1743 .flags = CLOCK_IN_OMAP343X,
1744 .recalc = &followparent_recalc,
1745};
1746
1747static struct clk i2c1_ick = {
1748 .name = "i2c_ick",
1749 .id = 1,
1750 .parent = &core_l4_ick,
1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1752 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1753 .flags = CLOCK_IN_OMAP343X,
1754 .recalc = &followparent_recalc,
1755};
1756
1757static struct clk uart2_ick = {
1758 .name = "uart2_ick",
1759 .parent = &core_l4_ick,
1760 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1761 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1762 .flags = CLOCK_IN_OMAP343X,
1763 .recalc = &followparent_recalc,
1764};
1765
1766static struct clk uart1_ick = {
1767 .name = "uart1_ick",
1768 .parent = &core_l4_ick,
1769 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1770 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1771 .flags = CLOCK_IN_OMAP343X,
1772 .recalc = &followparent_recalc,
1773};
1774
1775static struct clk gpt11_ick = {
1776 .name = "gpt11_ick",
1777 .parent = &core_l4_ick,
1778 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1779 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1780 .flags = CLOCK_IN_OMAP343X,
1781 .recalc = &followparent_recalc,
1782};
1783
1784static struct clk gpt10_ick = {
1785 .name = "gpt10_ick",
1786 .parent = &core_l4_ick,
1787 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1789 .flags = CLOCK_IN_OMAP343X,
1790 .recalc = &followparent_recalc,
1791};
1792
1793static struct clk mcbsp5_ick = {
78673bc8
EV		 1794 .name = "mcbsp_ick",
1795 .id = 5,
b045d080
PW		 1796 .parent = &core_l4_ick,
1797 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1798 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1799 .flags = CLOCK_IN_OMAP343X,
1800 .recalc = &followparent_recalc,
1801};
1802
1803static struct clk mcbsp1_ick = {
78673bc8
EV		 1804 .name = "mcbsp_ick",
1805 .id = 1,
b045d080
PW		 1806 .parent = &core_l4_ick,
1807 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1808 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1809 .flags = CLOCK_IN_OMAP343X,
1810 .recalc = &followparent_recalc,
1811};
1812
1813static struct clk fac_ick = {
1814 .name = "fac_ick",
1815 .parent = &core_l4_ick,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1817 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1818 .flags = CLOCK_IN_OMAP3430ES1,
1819 .recalc = &followparent_recalc,
1820};
1821
1822static struct clk mailboxes_ick = {
1823 .name = "mailboxes_ick",
1824 .parent = &core_l4_ick,
1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1826 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1827 .flags = CLOCK_IN_OMAP343X,
1828 .recalc = &followparent_recalc,
1829};
1830
1831static struct clk omapctrl_ick = {
1832 .name = "omapctrl_ick",
1833 .parent = &core_l4_ick,
1834 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1835 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1836 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1837 .recalc = &followparent_recalc,
1838};
1839
1840/* SSI_L4_ICK based clocks */
1841
1842static struct clk ssi_l4_ick = {
1843 .name = "ssi_l4_ick",
1844 .parent = &l4_ick,
1971a390
JH		 1845 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1846 PARENT_CONTROLS_CLOCK,
b045d080
PW		 1847 .recalc = &followparent_recalc,
1848};
1849
1850static struct clk ssi_ick = {
1851 .name = "ssi_ick",
1852 .parent = &ssi_l4_ick,
1853 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1854 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1855 .flags = CLOCK_IN_OMAP343X,
1856 .recalc = &followparent_recalc,
1857};
1858
1859/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1860 * but l4_ick makes more sense to me */
1861
1862static const struct clksel usb_l4_clksel[] = {
1863 { .parent = &l4_ick, .rates = div2_rates },
1864 { .parent = NULL },
1865};
1866
1867static struct clk usb_l4_ick = {
1868 .name = "usb_l4_ick",
1869 .parent = &l4_ick,
1870 .init = &omap2_init_clksel_parent,
1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1872 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1873 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1874 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1875 .clksel = usb_l4_clksel,
1876 .flags = CLOCK_IN_OMAP3430ES1,
1877 .recalc = &omap2_clksel_recalc,
1878};
1879
1880/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1881
1882/* SECURITY_L4_ICK2 based clocks */
1883
1884static struct clk security_l4_ick2 = {
1885 .name = "security_l4_ick2",
1886 .parent = &l4_ick,
1887 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1888 PARENT_CONTROLS_CLOCK,
1889 .recalc = &followparent_recalc,
1890};
1891
1892static struct clk aes1_ick = {
1893 .name = "aes1_ick",
1894 .parent = &security_l4_ick2,
1895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1896 .enable_bit = OMAP3430_EN_AES1_SHIFT,
1897 .flags = CLOCK_IN_OMAP343X,
1898 .recalc = &followparent_recalc,
1899};
1900
1901static struct clk rng_ick = {
1902 .name = "rng_ick",
1903 .parent = &security_l4_ick2,
1904 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1905 .enable_bit = OMAP3430_EN_RNG_SHIFT,
1906 .flags = CLOCK_IN_OMAP343X,
1907 .recalc = &followparent_recalc,
1908};
1909
1910static struct clk sha11_ick = {
1911 .name = "sha11_ick",
1912 .parent = &security_l4_ick2,
1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1914 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
1915 .flags = CLOCK_IN_OMAP343X,
1916 .recalc = &followparent_recalc,
1917};
1918
1919static struct clk des1_ick = {
1920 .name = "des1_ick",
1921 .parent = &security_l4_ick2,
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1923 .enable_bit = OMAP3430_EN_DES1_SHIFT,
1924 .flags = CLOCK_IN_OMAP343X,
1925 .recalc = &followparent_recalc,
1926};
1927
1928/* DSS */
3760d31f
RT		 1929static const struct clksel dss1_alwon_fck_clksel[] = {
1930 { .parent = &sys_ck, .rates = dpll_bypass_rates },
1931 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
1932 { .parent = NULL }
1933};
b045d080
PW		 1934
1935static struct clk dss1_alwon_fck = {
1936 .name = "dss1_alwon_fck",
1937 .parent = &dpll4_m4x2_ck,
3760d31f 1938 .init = &omap2_init_clksel_parent,
b045d080
PW		 1939 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1940 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
3760d31f
RT		 1941 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1942 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
1943 .clksel = dss1_alwon_fck_clksel,
b045d080 1944 .flags = CLOCK_IN_OMAP343X,
3760d31f 1945 .recalc = &omap2_clksel_recalc,
b045d080
PW		 1946};
1947
1948static struct clk dss_tv_fck = {
1949 .name = "dss_tv_fck",
1950 .parent = &omap_54m_fck,
1951 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1952 .enable_bit = OMAP3430_EN_TV_SHIFT,
1953 .flags = CLOCK_IN_OMAP343X,
1954 .recalc = &followparent_recalc,
1955};
1956
1957static struct clk dss_96m_fck = {
1958 .name = "dss_96m_fck",
1959 .parent = &omap_96m_fck,
1960 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1961 .enable_bit = OMAP3430_EN_TV_SHIFT,
1962 .flags = CLOCK_IN_OMAP343X,
1963 .recalc = &followparent_recalc,
1964};
1965
1966static struct clk dss2_alwon_fck = {
1967 .name = "dss2_alwon_fck",
1968 .parent = &sys_ck,
1969 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1970 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
1971 .flags = CLOCK_IN_OMAP343X,
1972 .recalc = &followparent_recalc,
1973};
1974
1975static struct clk dss_ick = {
1976 /* Handles both L3 and L4 clocks */
1977 .name = "dss_ick",
1978 .parent = &l4_ick,
1979 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1980 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1981 .flags = CLOCK_IN_OMAP343X,
1982 .recalc = &followparent_recalc,
1983};
1984
1985/* CAM */
1986
3760d31f
RT		 1987static const struct clksel cam_mclk_clksel[] = {
1988 { .parent = &sys_ck, .rates = dpll_bypass_rates },
1989 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
1990 { .parent = NULL }
1991};
1992
b045d080
PW		 1993static struct clk cam_mclk = {
1994 .name = "cam_mclk",
1995 .parent = &dpll4_m5x2_ck,
3760d31f
RT		 1996 .init = &omap2_init_clksel_parent,
1997 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1998 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
1999 .clksel = cam_mclk_clksel,
b045d080
PW		 2000 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2001 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2002 .flags = CLOCK_IN_OMAP343X,
3760d31f 2003 .recalc = &omap2_clksel_recalc,
b045d080
PW		 2004};
2005
2006static struct clk cam_l3_ick = {
2007 .name = "cam_l3_ick",
2008 .parent = &l3_ick,
2009 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2010 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2011 .flags = CLOCK_IN_OMAP343X,
2012 .recalc = &followparent_recalc,
2013};
2014
2015static struct clk cam_l4_ick = {
2016 .name = "cam_l4_ick",
2017 .parent = &l4_ick,
2018 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2019 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2020 .flags = CLOCK_IN_OMAP343X,
2021 .recalc = &followparent_recalc,
2022};
2023
2024/* USBHOST - 3430ES2 only */
2025
2026static struct clk usbhost_120m_fck = {
2027 .name = "usbhost_120m_fck",
2028 .parent = &omap_120m_fck,
2029 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2030 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2031 .flags = CLOCK_IN_OMAP3430ES2,
2032 .recalc = &followparent_recalc,
2033};
2034
2035static struct clk usbhost_48m_fck = {
2036 .name = "usbhost_48m_fck",
2037 .parent = &omap_48m_fck,
2038 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2039 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2040 .flags = CLOCK_IN_OMAP3430ES2,
2041 .recalc = &followparent_recalc,
2042};
2043
2044static struct clk usbhost_l3_ick = {
2045 .name = "usbhost_l3_ick",
2046 .parent = &l3_ick,
2047 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2048 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2049 .flags = CLOCK_IN_OMAP3430ES2,
2050 .recalc = &followparent_recalc,
2051};
2052
2053static struct clk usbhost_l4_ick = {
2054 .name = "usbhost_l4_ick",
2055 .parent = &l4_ick,
2056 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2057 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2058 .flags = CLOCK_IN_OMAP3430ES2,
2059 .recalc = &followparent_recalc,
2060};
2061
2062static struct clk usbhost_sar_fck = {
2063 .name = "usbhost_sar_fck",
2064 .parent = &osc_sys_ck,
2065 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2066 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2067 .flags = CLOCK_IN_OMAP3430ES2,
2068 .recalc = &followparent_recalc,
2069};
2070
2071/* WKUP */
2072
2073static const struct clksel_rate usim_96m_rates[] = {
2074 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2075 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2076 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2077 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2078 { .div = 0 },
2079};
2080
2081static const struct clksel_rate usim_120m_rates[] = {
2082 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2083 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2084 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2085 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2086 { .div = 0 },
2087};
2088
2089static const struct clksel usim_clksel[] = {
2090 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2091 { .parent = &omap_120m_fck, .rates = usim_120m_rates },
2092 { .parent = &sys_ck, .rates = div2_rates },
2093 { .parent = NULL },
2094};
2095
2096/* 3430ES2 only */
2097static struct clk usim_fck = {
2098 .name = "usim_fck",
2099 .init = &omap2_init_clksel_parent,
2100 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2101 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2102 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2103 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2104 .clksel = usim_clksel,
2105 .flags = CLOCK_IN_OMAP3430ES2,
2106 .recalc = &omap2_clksel_recalc,
2107};
2108
2109static struct clk gpt1_fck = {
2110 .name = "gpt1_fck",
2111 .init = &omap2_init_clksel_parent,
2112 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2113 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2114 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2115 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2116 .clksel = omap343x_gpt_clksel,
2117 .flags = CLOCK_IN_OMAP343X,
2118 .recalc = &omap2_clksel_recalc,
2119};
2120
2121static struct clk wkup_32k_fck = {
2122 .name = "wkup_32k_fck",
2123 .parent = &omap_32k_fck,
2124 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2125 .recalc = &followparent_recalc,
2126};
2127
2128static struct clk gpio1_fck = {
2129 .name = "gpio1_fck",
2130 .parent = &wkup_32k_fck,
2131 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2132 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2133 .flags = CLOCK_IN_OMAP343X,
2134 .recalc = &followparent_recalc,
2135};
2136
2137static struct clk wdt2_fck = {
2138 .name = "wdt2_fck",
2139 .parent = &wkup_32k_fck,
2140 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2141 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2142 .flags = CLOCK_IN_OMAP343X,
2143 .recalc = &followparent_recalc,
2144};
2145
2146static struct clk wkup_l4_ick = {
2147 .name = "wkup_l4_ick",
2148 .parent = &sys_ck,
2149 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2150 .recalc = &followparent_recalc,
2151};
2152
2153/* 3430ES2 only */
2154/* Never specifically named in the TRM, so we have to infer a likely name */
2155static struct clk usim_ick = {
2156 .name = "usim_ick",
2157 .parent = &wkup_l4_ick,
2158 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2159 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2160 .flags = CLOCK_IN_OMAP3430ES2,
2161 .recalc = &followparent_recalc,
2162};
2163
2164static struct clk wdt2_ick = {
2165 .name = "wdt2_ick",
2166 .parent = &wkup_l4_ick,
2167 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2168 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2169 .flags = CLOCK_IN_OMAP343X,
2170 .recalc = &followparent_recalc,
2171};
2172
2173static struct clk wdt1_ick = {
2174 .name = "wdt1_ick",
2175 .parent = &wkup_l4_ick,
2176 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2177 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2178 .flags = CLOCK_IN_OMAP343X,
2179 .recalc = &followparent_recalc,
2180};
2181
2182static struct clk gpio1_ick = {
2183 .name = "gpio1_ick",
2184 .parent = &wkup_l4_ick,
2185 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2186 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2187 .flags = CLOCK_IN_OMAP343X,
2188 .recalc = &followparent_recalc,
2189};
2190
2191static struct clk omap_32ksync_ick = {
2192 .name = "omap_32ksync_ick",
2193 .parent = &wkup_l4_ick,
2194 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2195 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2196 .flags = CLOCK_IN_OMAP343X,
2197 .recalc = &followparent_recalc,
2198};
2199
2200static struct clk gpt12_ick = {
2201 .name = "gpt12_ick",
2202 .parent = &wkup_l4_ick,
2203 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2204 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2205 .flags = CLOCK_IN_OMAP343X,
2206 .recalc = &followparent_recalc,
2207};
2208
2209static struct clk gpt1_ick = {
2210 .name = "gpt1_ick",
2211 .parent = &wkup_l4_ick,
2212 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2213 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2214 .flags = CLOCK_IN_OMAP343X,
2215 .recalc = &followparent_recalc,
2216};
2217
2218
2219
2220/* PER clock domain */
2221
2222static struct clk per_96m_fck = {
2223 .name = "per_96m_fck",
2224 .parent = &omap_96m_alwon_fck,
2225 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2226 PARENT_CONTROLS_CLOCK,
2227 .recalc = &followparent_recalc,
2228};
2229
2230static struct clk per_48m_fck = {
2231 .name = "per_48m_fck",
2232 .parent = &omap_48m_fck,
2233 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2234 PARENT_CONTROLS_CLOCK,
2235 .recalc = &followparent_recalc,
2236};
2237
2238static struct clk uart3_fck = {
2239 .name = "uart3_fck",
2240 .parent = &per_48m_fck,
2241 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2242 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2243 .flags = CLOCK_IN_OMAP343X,
2244 .recalc = &followparent_recalc,
2245};
2246
2247static struct clk gpt2_fck = {
2248 .name = "gpt2_fck",
2249 .init = &omap2_init_clksel_parent,
2250 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2251 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2252 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2253 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2254 .clksel = omap343x_gpt_clksel,
2255 .flags = CLOCK_IN_OMAP343X,
2256 .recalc = &omap2_clksel_recalc,
2257};
2258
2259static struct clk gpt3_fck = {
2260 .name = "gpt3_fck",
2261 .init = &omap2_init_clksel_parent,
2262 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2263 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2264 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2265 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2266 .clksel = omap343x_gpt_clksel,
2267 .flags = CLOCK_IN_OMAP343X,
2268 .recalc = &omap2_clksel_recalc,
2269};
2270
2271static struct clk gpt4_fck = {
2272 .name = "gpt4_fck",
2273 .init = &omap2_init_clksel_parent,
2274 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2275 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2276 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2277 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2278 .clksel = omap343x_gpt_clksel,
2279 .flags = CLOCK_IN_OMAP343X,
2280 .recalc = &omap2_clksel_recalc,
2281};
2282
2283static struct clk gpt5_fck = {
2284 .name = "gpt5_fck",
2285 .init = &omap2_init_clksel_parent,
2286 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2287 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2288 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2289 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2290 .clksel = omap343x_gpt_clksel,
2291 .flags = CLOCK_IN_OMAP343X,
2292 .recalc = &omap2_clksel_recalc,
2293};
2294
2295static struct clk gpt6_fck = {
2296 .name = "gpt6_fck",
2297 .init = &omap2_init_clksel_parent,
2298 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2299 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2300 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2301 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2302 .clksel = omap343x_gpt_clksel,
2303 .flags = CLOCK_IN_OMAP343X,
2304 .recalc = &omap2_clksel_recalc,
2305};
2306
2307static struct clk gpt7_fck = {
2308 .name = "gpt7_fck",
2309 .init = &omap2_init_clksel_parent,
2310 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2311 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2312 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2313 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2314 .clksel = omap343x_gpt_clksel,
2315 .flags = CLOCK_IN_OMAP343X,
2316 .recalc = &omap2_clksel_recalc,
2317};
2318
2319static struct clk gpt8_fck = {
2320 .name = "gpt8_fck",
2321 .init = &omap2_init_clksel_parent,
2322 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2323 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2324 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2325 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2326 .clksel = omap343x_gpt_clksel,
2327 .flags = CLOCK_IN_OMAP343X,
2328 .recalc = &omap2_clksel_recalc,
2329};
2330
2331static struct clk gpt9_fck = {
2332 .name = "gpt9_fck",
2333 .init = &omap2_init_clksel_parent,
2334 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2335 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2336 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2337 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2338 .clksel = omap343x_gpt_clksel,
2339 .flags = CLOCK_IN_OMAP343X,
2340 .recalc = &omap2_clksel_recalc,
2341};
2342
2343static struct clk per_32k_alwon_fck = {
2344 .name = "per_32k_alwon_fck",
2345 .parent = &omap_32k_fck,
2346 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2347 .recalc = &followparent_recalc,
2348};
2349
2350static struct clk gpio6_fck = {
2351 .name = "gpio6_fck",
2352 .parent = &per_32k_alwon_fck,
2353 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
c3aa044a 2354 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
b045d080
PW		 2355 .flags = CLOCK_IN_OMAP343X,
2356 .recalc = &followparent_recalc,
2357};
2358
2359static struct clk gpio5_fck = {
2360 .name = "gpio5_fck",
2361 .parent = &per_32k_alwon_fck,
2362 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
c3aa044a 2363 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
b045d080
PW		 2364 .flags = CLOCK_IN_OMAP343X,
2365 .recalc = &followparent_recalc,
2366};
2367
2368static struct clk gpio4_fck = {
2369 .name = "gpio4_fck",
2370 .parent = &per_32k_alwon_fck,
2371 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
c3aa044a 2372 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
b045d080
PW		 2373 .flags = CLOCK_IN_OMAP343X,
2374 .recalc = &followparent_recalc,
2375};
2376
2377static struct clk gpio3_fck = {
2378 .name = "gpio3_fck",
2379 .parent = &per_32k_alwon_fck,
2380 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
c3aa044a 2381 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
b045d080
PW		 2382 .flags = CLOCK_IN_OMAP343X,
2383 .recalc = &followparent_recalc,
2384};
2385
2386static struct clk gpio2_fck = {
2387 .name = "gpio2_fck",
2388 .parent = &per_32k_alwon_fck,
2389 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
c3aa044a 2390 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
b045d080
PW		 2391 .flags = CLOCK_IN_OMAP343X,
2392 .recalc = &followparent_recalc,
2393};
2394
2395static struct clk wdt3_fck = {
2396 .name = "wdt3_fck",
2397 .parent = &per_32k_alwon_fck,
2398 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2399 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2400 .flags = CLOCK_IN_OMAP343X,
2401 .recalc = &followparent_recalc,
2402};
2403
2404static struct clk per_l4_ick = {
2405 .name = "per_l4_ick",
2406 .parent = &l4_ick,
2407 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2408 PARENT_CONTROLS_CLOCK,
2409 .recalc = &followparent_recalc,
2410};
2411
2412static struct clk gpio6_ick = {
2413 .name = "gpio6_ick",
2414 .parent = &per_l4_ick,
2415 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2416 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2417 .flags = CLOCK_IN_OMAP343X,
2418 .recalc = &followparent_recalc,
2419};
2420
2421static struct clk gpio5_ick = {
2422 .name = "gpio5_ick",
2423 .parent = &per_l4_ick,
2424 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2425 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2426 .flags = CLOCK_IN_OMAP343X,
2427 .recalc = &followparent_recalc,
2428};
2429
2430static struct clk gpio4_ick = {
2431 .name = "gpio4_ick",
2432 .parent = &per_l4_ick,
2433 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2434 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2435 .flags = CLOCK_IN_OMAP343X,
2436 .recalc = &followparent_recalc,
2437};
2438
2439static struct clk gpio3_ick = {
2440 .name = "gpio3_ick",
2441 .parent = &per_l4_ick,
2442 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2443 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2444 .flags = CLOCK_IN_OMAP343X,
2445 .recalc = &followparent_recalc,
2446};
2447
2448static struct clk gpio2_ick = {
2449 .name = "gpio2_ick",
2450 .parent = &per_l4_ick,
2451 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2452 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2453 .flags = CLOCK_IN_OMAP343X,
2454 .recalc = &followparent_recalc,
2455};
2456
2457static struct clk wdt3_ick = {
2458 .name = "wdt3_ick",
2459 .parent = &per_l4_ick,
2460 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2461 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2462 .flags = CLOCK_IN_OMAP343X,
2463 .recalc = &followparent_recalc,
2464};
2465
2466static struct clk uart3_ick = {
2467 .name = "uart3_ick",
2468 .parent = &per_l4_ick,
2469 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2470 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2471 .flags = CLOCK_IN_OMAP343X,
2472 .recalc = &followparent_recalc,
2473};
2474
2475static struct clk gpt9_ick = {
2476 .name = "gpt9_ick",
2477 .parent = &per_l4_ick,
2478 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2479 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2480 .flags = CLOCK_IN_OMAP343X,
2481 .recalc = &followparent_recalc,
2482};
2483
2484static struct clk gpt8_ick = {
2485 .name = "gpt8_ick",
2486 .parent = &per_l4_ick,
2487 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2488 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2489 .flags = CLOCK_IN_OMAP343X,
2490 .recalc = &followparent_recalc,
2491};
2492
2493static struct clk gpt7_ick = {
2494 .name = "gpt7_ick",
2495 .parent = &per_l4_ick,
2496 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2497 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2498 .flags = CLOCK_IN_OMAP343X,
2499 .recalc = &followparent_recalc,
2500};
2501
2502static struct clk gpt6_ick = {
2503 .name = "gpt6_ick",
2504 .parent = &per_l4_ick,
2505 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2506 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2507 .flags = CLOCK_IN_OMAP343X,
2508 .recalc = &followparent_recalc,
2509};
2510
2511static struct clk gpt5_ick = {
2512 .name = "gpt5_ick",
2513 .parent = &per_l4_ick,
2514 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2515 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2516 .flags = CLOCK_IN_OMAP343X,
2517 .recalc = &followparent_recalc,
2518};
2519
2520static struct clk gpt4_ick = {
2521 .name = "gpt4_ick",
2522 .parent = &per_l4_ick,
2523 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2524 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2525 .flags = CLOCK_IN_OMAP343X,
2526 .recalc = &followparent_recalc,
2527};
2528
2529static struct clk gpt3_ick = {
2530 .name = "gpt3_ick",
2531 .parent = &per_l4_ick,
2532 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2533 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2534 .flags = CLOCK_IN_OMAP343X,
2535 .recalc = &followparent_recalc,
2536};
2537
2538static struct clk gpt2_ick = {
2539 .name = "gpt2_ick",
2540 .parent = &per_l4_ick,
2541 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2542 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2543 .flags = CLOCK_IN_OMAP343X,
2544 .recalc = &followparent_recalc,
2545};
2546
2547static struct clk mcbsp2_ick = {
78673bc8
EV		 2548 .name = "mcbsp_ick",
2549 .id = 2,
b045d080
PW		 2550 .parent = &per_l4_ick,
2551 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2552 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2553 .flags = CLOCK_IN_OMAP343X,
2554 .recalc = &followparent_recalc,
2555};
2556
2557static struct clk mcbsp3_ick = {
78673bc8
EV		 2558 .name = "mcbsp_ick",
2559 .id = 3,
b045d080
PW		 2560 .parent = &per_l4_ick,
2561 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2562 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2563 .flags = CLOCK_IN_OMAP343X,
2564 .recalc = &followparent_recalc,
2565};
2566
2567static struct clk mcbsp4_ick = {
78673bc8
EV		 2568 .name = "mcbsp_ick",
2569 .id = 4,
b045d080
PW		 2570 .parent = &per_l4_ick,
2571 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2572 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2573 .flags = CLOCK_IN_OMAP343X,
2574 .recalc = &followparent_recalc,
2575};
2576
2577static const struct clksel mcbsp_234_clksel[] = {
2578 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2579 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2580 { .parent = NULL }
2581};
2582
2583static struct clk mcbsp2_fck = {
78673bc8
EV		 2584 .name = "mcbsp_fck",
2585 .id = 2,
b045d080
PW		 2586 .init = &omap2_init_clksel_parent,
2587 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2588 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2589 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2590 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2591 .clksel = mcbsp_234_clksel,
2592 .flags = CLOCK_IN_OMAP343X,
2593 .recalc = &omap2_clksel_recalc,
2594};
2595
2596static struct clk mcbsp3_fck = {
78673bc8
EV		 2597 .name = "mcbsp_fck",
2598 .id = 3,
b045d080
PW		 2599 .init = &omap2_init_clksel_parent,
2600 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2601 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2602 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2603 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2604 .clksel = mcbsp_234_clksel,
2605 .flags = CLOCK_IN_OMAP343X,
2606 .recalc = &omap2_clksel_recalc,
2607};
2608
2609static struct clk mcbsp4_fck = {
78673bc8
EV		 2610 .name = "mcbsp_fck",
2611 .id = 4,
b045d080
PW		 2612 .init = &omap2_init_clksel_parent,
2613 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2614 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2615 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2616 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2617 .clksel = mcbsp_234_clksel,
2618 .flags = CLOCK_IN_OMAP343X,
2619 .recalc = &omap2_clksel_recalc,
2620};
2621
2622/* EMU clocks */
2623
2624/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2625
2626static const struct clksel_rate emu_src_sys_rates[] = {
2627 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2628 { .div = 0 },
2629};
2630
2631static const struct clksel_rate emu_src_core_rates[] = {
2632 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2633 { .div = 0 },
2634};
2635
2636static const struct clksel_rate emu_src_per_rates[] = {
2637 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2638 { .div = 0 },
2639};
2640
2641static const struct clksel_rate emu_src_mpu_rates[] = {
2642 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2643 { .div = 0 },
2644};
2645
2646static const struct clksel emu_src_clksel[] = {
2647 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2648 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2649 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2650 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2651 { .parent = NULL },
2652};
2653
2654/*
2655 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2656 * to switch the source of some of the EMU clocks.
2657 * XXX Are there CLKEN bits for these EMU clks?
2658 */
2659static struct clk emu_src_ck = {
2660 .name = "emu_src_ck",
2661 .init = &omap2_init_clksel_parent,
2662 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2663 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2664 .clksel = emu_src_clksel,
2665 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2666 .recalc = &omap2_clksel_recalc,
2667};
2668
2669static const struct clksel_rate pclk_emu_rates[] = {
2670 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2671 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2672 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2673 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2674 { .div = 0 },
2675};
2676
2677static const struct clksel pclk_emu_clksel[] = {
2678 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2679 { .parent = NULL },
2680};
2681
2682static struct clk pclk_fck = {
2683 .name = "pclk_fck",
2684 .init = &omap2_init_clksel_parent,
2685 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2686 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2687 .clksel = pclk_emu_clksel,
2688 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2689 .recalc = &omap2_clksel_recalc,
2690};
2691
2692static const struct clksel_rate pclkx2_emu_rates[] = {
2693 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2694 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2695 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2696 { .div = 0 },
2697};
2698
2699static const struct clksel pclkx2_emu_clksel[] = {
2700 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2701 { .parent = NULL },
2702};
2703
2704static struct clk pclkx2_fck = {
2705 .name = "pclkx2_fck",
2706 .init = &omap2_init_clksel_parent,
2707 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2708 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2709 .clksel = pclkx2_emu_clksel,
2710 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2711 .recalc = &omap2_clksel_recalc,
2712};
2713
2714static const struct clksel atclk_emu_clksel[] = {
2715 { .parent = &emu_src_ck, .rates = div2_rates },
2716 { .parent = NULL },
2717};
2718
2719static struct clk atclk_fck = {
2720 .name = "atclk_fck",
2721 .init = &omap2_init_clksel_parent,
2722 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2723 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2724 .clksel = atclk_emu_clksel,
2725 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2726 .recalc = &omap2_clksel_recalc,
2727};
2728
2729static struct clk traceclk_src_fck = {
2730 .name = "traceclk_src_fck",
2731 .init = &omap2_init_clksel_parent,
2732 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2733 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2734 .clksel = emu_src_clksel,
2735 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2736 .recalc = &omap2_clksel_recalc,
2737};
2738
2739static const struct clksel_rate traceclk_rates[] = {
2740 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2741 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2742 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2743 { .div = 0 },
2744};
2745
2746static const struct clksel traceclk_clksel[] = {
2747 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2748 { .parent = NULL },
2749};
2750
2751static struct clk traceclk_fck = {
2752 .name = "traceclk_fck",
2753 .init = &omap2_init_clksel_parent,
2754 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2755 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2756 .clksel = traceclk_clksel,
2757 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2758 .recalc = &omap2_clksel_recalc,
2759};
2760
2761/* SR clocks */
2762
2763/* SmartReflex fclk (VDD1) */
2764static struct clk sr1_fck = {
2765 .name = "sr1_fck",
2766 .parent = &sys_ck,
2767 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2768 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2769 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2770 .recalc = &followparent_recalc,
2771};
2772
2773/* SmartReflex fclk (VDD2) */
2774static struct clk sr2_fck = {
2775 .name = "sr2_fck",
2776 .parent = &sys_ck,
2777 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2778 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2780 .recalc = &followparent_recalc,
2781};
2782
2783static struct clk sr_l4_ick = {
2784 .name = "sr_l4_ick",
2785 .parent = &l4_ick,
2786 .flags = CLOCK_IN_OMAP343X,
2787 .recalc = &followparent_recalc,
2788};
2789
2790/* SECURE_32K_FCK clocks */
2791
2792static struct clk gpt12_fck = {
2793 .name = "gpt12_fck",
2794 .parent = &secure_32k_fck,
2795 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2796 .recalc = &followparent_recalc,
2797};
2798
2799static struct clk wdt1_fck = {
2800 .name = "wdt1_fck",
2801 .parent = &secure_32k_fck,
2802 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2803 .recalc = &followparent_recalc,
2804};
2805
b045d080
PW		 2806static struct clk *onchip_34xx_clks[] __initdata = {
2807 &omap_32k_fck,
2808 &virt_12m_ck,
2809 &virt_13m_ck,
2810 &virt_16_8m_ck,
2811 &virt_19_2m_ck,
2812 &virt_26m_ck,
2813 &virt_38_4m_ck,
2814 &osc_sys_ck,
2815 &sys_ck,
2816 &sys_altclk,
2817 &mcbsp_clks,
2818 &sys_clkout1,
2819 &dpll1_ck,
3760d31f
RT		 2820 &dpll1_x2_ck,
2821 &dpll1_x2m2_ck,
b045d080 2822 &dpll2_ck,
3760d31f 2823 &dpll2_m2_ck,
b045d080
PW		 2824 &dpll3_ck,
2825 &core_ck,
2826 &dpll3_x2_ck,
2827 &dpll3_m2_ck,
2828 &dpll3_m2x2_ck,
3760d31f 2829 &dpll3_m3_ck,
b045d080
PW		 2830 &dpll3_m3x2_ck,
2831 &emu_core_alwon_ck,
2832 &dpll4_ck,
2833 &dpll4_x2_ck,
2834 &omap_96m_alwon_fck,
2835 &omap_96m_fck,
2836 &cm_96m_fck,
3760d31f 2837 &virt_omap_54m_fck,
b045d080
PW		 2838 &omap_54m_fck,
2839 &omap_48m_fck,
2840 &omap_12m_fck,
3760d31f 2841 &dpll4_m2_ck,
b045d080 2842 &dpll4_m2x2_ck,
3760d31f 2843 &dpll4_m3_ck,
b045d080 2844 &dpll4_m3x2_ck,
3760d31f 2845 &dpll4_m4_ck,
b045d080 2846 &dpll4_m4x2_ck,
3760d31f 2847 &dpll4_m5_ck,
b045d080 2848 &dpll4_m5x2_ck,
3760d31f 2849 &dpll4_m6_ck,
b045d080
PW		 2850 &dpll4_m6x2_ck,
2851 &emu_per_alwon_ck,
2852 &dpll5_ck,
2853 &dpll5_m2_ck,
2854 &omap_120m_fck,
2855 &clkout2_src_ck,
2856 &sys_clkout2,
2857 &corex2_fck,
2858 &dpll1_fck,
3760d31f
RT		 2859 &mpu_ck,
2860 &arm_fck,
2861 &emu_mpu_alwon_ck,
b045d080 2862 &dpll2_fck,
3760d31f 2863 &iva2_ck,
b045d080
PW		 2864 &l3_ick,
2865 &l4_ick,
2866 &rm_ick,
2867 &gfx_l3_fck,
2868 &gfx_l3_ick,
2869 &gfx_cg1_ck,
2870 &gfx_cg2_ck,
2871 &sgx_fck,
2872 &sgx_ick,
2873 &d2d_26m_fck,
2874 &gpt10_fck,
2875 &gpt11_fck,
2876 &cpefuse_fck,
2877 &ts_fck,
2878 &usbtll_fck,
2879 &core_96m_fck,
2880 &mmchs3_fck,
2881 &mmchs2_fck,
2882 &mspro_fck,
2883 &mmchs1_fck,
2884 &i2c3_fck,
2885 &i2c2_fck,
2886 &i2c1_fck,
2887 &mcbsp5_fck,
2888 &mcbsp1_fck,
2889 &core_48m_fck,
2890 &mcspi4_fck,
2891 &mcspi3_fck,
2892 &mcspi2_fck,
2893 &mcspi1_fck,
2894 &uart2_fck,
2895 &uart1_fck,
2896 &fshostusb_fck,
2897 &core_12m_fck,
2898 &hdq_fck,
2899 &ssi_ssr_fck,
2900 &ssi_sst_fck,
2901 &core_l3_ick,
2902 &hsotgusb_ick,
2903 &sdrc_ick,
2904 &gpmc_fck,
2905 &security_l3_ick,
2906 &pka_ick,
2907 &core_l4_ick,
2908 &usbtll_ick,
2909 &mmchs3_ick,
2910 &icr_ick,
2911 &aes2_ick,
2912 &sha12_ick,
2913 &des2_ick,
2914 &mmchs2_ick,
2915 &mmchs1_ick,
2916 &mspro_ick,
2917 &hdq_ick,
2918 &mcspi4_ick,
2919 &mcspi3_ick,
2920 &mcspi2_ick,
2921 &mcspi1_ick,
2922 &i2c3_ick,
2923 &i2c2_ick,
2924 &i2c1_ick,
2925 &uart2_ick,
2926 &uart1_ick,
2927 &gpt11_ick,
2928 &gpt10_ick,
2929 &mcbsp5_ick,
2930 &mcbsp1_ick,
2931 &fac_ick,
2932 &mailboxes_ick,
2933 &omapctrl_ick,
2934 &ssi_l4_ick,
2935 &ssi_ick,
2936 &usb_l4_ick,
2937 &security_l4_ick2,
2938 &aes1_ick,
2939 &rng_ick,
2940 &sha11_ick,
2941 &des1_ick,
2942 &dss1_alwon_fck,
2943 &dss_tv_fck,
2944 &dss_96m_fck,
2945 &dss2_alwon_fck,
2946 &dss_ick,
2947 &cam_mclk,
2948 &cam_l3_ick,
2949 &cam_l4_ick,
2950 &usbhost_120m_fck,
2951 &usbhost_48m_fck,
2952 &usbhost_l3_ick,
2953 &usbhost_l4_ick,
2954 &usbhost_sar_fck,
2955 &usim_fck,
2956 &gpt1_fck,
2957 &wkup_32k_fck,
2958 &gpio1_fck,
2959 &wdt2_fck,
2960 &wkup_l4_ick,
2961 &usim_ick,
2962 &wdt2_ick,
2963 &wdt1_ick,
2964 &gpio1_ick,
2965 &omap_32ksync_ick,
2966 &gpt12_ick,
2967 &gpt1_ick,
2968 &per_96m_fck,
2969 &per_48m_fck,
2970 &uart3_fck,
2971 &gpt2_fck,
2972 &gpt3_fck,
2973 &gpt4_fck,
2974 &gpt5_fck,
2975 &gpt6_fck,
2976 &gpt7_fck,
2977 &gpt8_fck,
2978 &gpt9_fck,
2979 &per_32k_alwon_fck,
2980 &gpio6_fck,
2981 &gpio5_fck,
2982 &gpio4_fck,
2983 &gpio3_fck,
2984 &gpio2_fck,
2985 &wdt3_fck,
2986 &per_l4_ick,
2987 &gpio6_ick,
2988 &gpio5_ick,
2989 &gpio4_ick,
2990 &gpio3_ick,
2991 &gpio2_ick,
2992 &wdt3_ick,
2993 &uart3_ick,
2994 &gpt9_ick,
2995 &gpt8_ick,
2996 &gpt7_ick,
2997 &gpt6_ick,
2998 &gpt5_ick,
2999 &gpt4_ick,
3000 &gpt3_ick,
3001 &gpt2_ick,
3002 &mcbsp2_ick,
3003 &mcbsp3_ick,
3004 &mcbsp4_ick,
3005 &mcbsp2_fck,
3006 &mcbsp3_fck,
3007 &mcbsp4_fck,
3008 &emu_src_ck,
3009 &pclk_fck,
3010 &pclkx2_fck,
3011 &atclk_fck,
3012 &traceclk_src_fck,
3013 &traceclk_fck,
3014 &sr1_fck,
3015 &sr2_fck,
3016 &sr_l4_ick,
3017 &secure_32k_fck,
3018 &gpt12_fck,
3019 &wdt1_fck,
3020};
3021
3022#endif
kernel source for telekom puls (alcatel/mediatek)