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b045d080 PW |
1 | /* |
2 | * OMAP3 clock framework | |
3 | * | |
4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
5 | * Copyright (C) 2007-2008 Nokia Corporation | |
6 | * | |
7 | * Written by Paul Walmsley | |
8 | */ | |
9 | ||
10 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | |
11 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | |
12 | ||
13 | #include <asm/arch/control.h> | |
14 | ||
15 | #include "clock.h" | |
16 | #include "cm.h" | |
17 | #include "cm-regbits-34xx.h" | |
18 | #include "prm.h" | |
19 | #include "prm-regbits-34xx.h" | |
20 | ||
21 | static void omap3_dpll_recalc(struct clk *clk); | |
22 | static void omap3_clkoutx2_recalc(struct clk *clk); | |
23 | ||
24 | /* | |
25 | * DPLL1 supplies clock to the MPU. | |
26 | * DPLL2 supplies clock to the IVA2. | |
27 | * DPLL3 supplies CORE domain clocks. | |
28 | * DPLL4 supplies peripheral clocks. | |
29 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). | |
30 | */ | |
31 | ||
32 | /* PRM CLOCKS */ | |
33 | ||
34 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ | |
35 | static struct clk omap_32k_fck = { | |
36 | .name = "omap_32k_fck", | |
37 | .rate = 32768, | |
38 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
39 | ALWAYS_ENABLED, | |
40 | .recalc = &propagate_rate, | |
41 | }; | |
42 | ||
43 | static struct clk secure_32k_fck = { | |
44 | .name = "secure_32k_fck", | |
45 | .rate = 32768, | |
46 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
47 | ALWAYS_ENABLED, | |
48 | .recalc = &propagate_rate, | |
49 | }; | |
50 | ||
51 | /* Virtual source clocks for osc_sys_ck */ | |
52 | static struct clk virt_12m_ck = { | |
53 | .name = "virt_12m_ck", | |
54 | .rate = 12000000, | |
55 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
56 | ALWAYS_ENABLED, | |
57 | .recalc = &propagate_rate, | |
58 | }; | |
59 | ||
60 | static struct clk virt_13m_ck = { | |
61 | .name = "virt_13m_ck", | |
62 | .rate = 13000000, | |
63 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
64 | ALWAYS_ENABLED, | |
65 | .recalc = &propagate_rate, | |
66 | }; | |
67 | ||
68 | static struct clk virt_16_8m_ck = { | |
69 | .name = "virt_16_8m_ck", | |
70 | .rate = 16800000, | |
71 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | | |
72 | ALWAYS_ENABLED, | |
73 | .recalc = &propagate_rate, | |
74 | }; | |
75 | ||
76 | static struct clk virt_19_2m_ck = { | |
77 | .name = "virt_19_2m_ck", | |
78 | .rate = 19200000, | |
79 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
80 | ALWAYS_ENABLED, | |
81 | .recalc = &propagate_rate, | |
82 | }; | |
83 | ||
84 | static struct clk virt_26m_ck = { | |
85 | .name = "virt_26m_ck", | |
86 | .rate = 26000000, | |
87 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
88 | ALWAYS_ENABLED, | |
89 | .recalc = &propagate_rate, | |
90 | }; | |
91 | ||
92 | static struct clk virt_38_4m_ck = { | |
93 | .name = "virt_38_4m_ck", | |
94 | .rate = 38400000, | |
95 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
96 | ALWAYS_ENABLED, | |
97 | .recalc = &propagate_rate, | |
98 | }; | |
99 | ||
100 | static const struct clksel_rate osc_sys_12m_rates[] = { | |
101 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
102 | { .div = 0 } | |
103 | }; | |
104 | ||
105 | static const struct clksel_rate osc_sys_13m_rates[] = { | |
106 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
107 | { .div = 0 } | |
108 | }; | |
109 | ||
110 | static const struct clksel_rate osc_sys_16_8m_rates[] = { | |
111 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, | |
112 | { .div = 0 } | |
113 | }; | |
114 | ||
115 | static const struct clksel_rate osc_sys_19_2m_rates[] = { | |
116 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
117 | { .div = 0 } | |
118 | }; | |
119 | ||
120 | static const struct clksel_rate osc_sys_26m_rates[] = { | |
121 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
122 | { .div = 0 } | |
123 | }; | |
124 | ||
125 | static const struct clksel_rate osc_sys_38_4m_rates[] = { | |
126 | { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
127 | { .div = 0 } | |
128 | }; | |
129 | ||
130 | static const struct clksel osc_sys_clksel[] = { | |
131 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, | |
132 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, | |
133 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, | |
134 | { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, | |
135 | { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, | |
136 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, | |
137 | { .parent = NULL }, | |
138 | }; | |
139 | ||
140 | /* Oscillator clock */ | |
141 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ | |
142 | static struct clk osc_sys_ck = { | |
143 | .name = "osc_sys_ck", | |
144 | .init = &omap2_init_clksel_parent, | |
145 | .clksel_reg = OMAP3430_PRM_CLKSEL, | |
146 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | |
147 | .clksel = osc_sys_clksel, | |
148 | /* REVISIT: deal with autoextclkmode? */ | |
149 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
150 | ALWAYS_ENABLED, | |
151 | .recalc = &omap2_clksel_recalc, | |
152 | }; | |
153 | ||
154 | static const struct clksel_rate div2_rates[] = { | |
155 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
156 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
157 | { .div = 0 } | |
158 | }; | |
159 | ||
160 | static const struct clksel sys_clksel[] = { | |
161 | { .parent = &osc_sys_ck, .rates = div2_rates }, | |
162 | { .parent = NULL } | |
163 | }; | |
164 | ||
165 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ | |
166 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ | |
167 | static struct clk sys_ck = { | |
168 | .name = "sys_ck", | |
169 | .parent = &osc_sys_ck, | |
170 | .init = &omap2_init_clksel_parent, | |
171 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, | |
172 | .clksel_mask = OMAP_SYSCLKDIV_MASK, | |
173 | .clksel = sys_clksel, | |
174 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
175 | .recalc = &omap2_clksel_recalc, | |
176 | }; | |
177 | ||
178 | static struct clk sys_altclk = { | |
179 | .name = "sys_altclk", | |
180 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
181 | .recalc = &propagate_rate, | |
182 | }; | |
183 | ||
184 | /* Optional external clock input for some McBSPs */ | |
185 | static struct clk mcbsp_clks = { | |
186 | .name = "mcbsp_clks", | |
187 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
188 | .recalc = &propagate_rate, | |
189 | }; | |
190 | ||
191 | /* PRM EXTERNAL CLOCK OUTPUT */ | |
192 | ||
193 | static struct clk sys_clkout1 = { | |
194 | .name = "sys_clkout1", | |
195 | .parent = &osc_sys_ck, | |
196 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, | |
197 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, | |
198 | .flags = CLOCK_IN_OMAP343X, | |
199 | .recalc = &followparent_recalc, | |
200 | }; | |
201 | ||
202 | /* DPLLS */ | |
203 | ||
204 | /* CM CLOCKS */ | |
205 | ||
206 | /* DPLL1 */ | |
207 | /* MPU clock source */ | |
208 | /* Type: DPLL */ | |
209 | static const struct dpll_data dpll1_dd = { | |
210 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
211 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, | |
212 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, | |
213 | .div2_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), | |
214 | .div2_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, | |
215 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), | |
216 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, | |
217 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, | |
218 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, | |
219 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, | |
220 | }; | |
221 | ||
222 | static struct clk dpll1_ck = { | |
223 | .name = "dpll1_ck", | |
224 | .parent = &sys_ck, | |
225 | .dpll_data = &dpll1_dd, | |
226 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
227 | .recalc = &omap3_dpll_recalc, | |
228 | }; | |
229 | ||
230 | /* | |
231 | * REVISIT: This clock is never specifically defined in the 3430 TRM, | |
232 | * although it is referenced - so this is a guess | |
233 | */ | |
234 | static struct clk emu_mpu_alwon_ck = { | |
235 | .name = "emu_mpu_alwon_ck", | |
236 | .parent = &dpll1_ck, | |
237 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
238 | PARENT_CONTROLS_CLOCK, | |
239 | .recalc = &followparent_recalc, | |
240 | }; | |
241 | ||
242 | /* DPLL2 */ | |
243 | /* IVA2 clock source */ | |
244 | /* Type: DPLL */ | |
245 | ||
246 | static const struct dpll_data dpll2_dd = { | |
247 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
248 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, | |
249 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, | |
250 | .div2_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL), | |
251 | .div2_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, | |
252 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), | |
253 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, | |
254 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, | |
255 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, | |
256 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, | |
257 | }; | |
258 | ||
259 | static struct clk dpll2_ck = { | |
260 | .name = "dpll2_ck", | |
261 | .parent = &sys_ck, | |
262 | .dpll_data = &dpll2_dd, | |
263 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
264 | .recalc = &omap3_dpll_recalc, | |
265 | }; | |
266 | ||
267 | /* DPLL3 */ | |
268 | /* Source clock for all interfaces and for some device fclks */ | |
269 | /* Type: DPLL */ | |
270 | static const struct dpll_data dpll3_dd = { | |
271 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
272 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, | |
273 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, | |
274 | .div2_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
275 | .div2_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, | |
276 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
277 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, | |
278 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, | |
279 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, | |
280 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, | |
281 | }; | |
282 | ||
283 | static struct clk dpll3_ck = { | |
284 | .name = "dpll3_ck", | |
285 | .parent = &sys_ck, | |
286 | .dpll_data = &dpll3_dd, | |
287 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
288 | .recalc = &omap3_dpll_recalc, | |
289 | }; | |
290 | ||
291 | static const struct clksel_rate div16_dpll_rates[] = { | |
292 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
293 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
294 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
295 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
296 | { .div = 5, .val = 5, .flags = RATE_IN_343X }, | |
297 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
298 | { .div = 7, .val = 7, .flags = RATE_IN_343X }, | |
299 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
300 | { .div = 9, .val = 9, .flags = RATE_IN_343X }, | |
301 | { .div = 10, .val = 10, .flags = RATE_IN_343X }, | |
302 | { .div = 11, .val = 11, .flags = RATE_IN_343X }, | |
303 | { .div = 12, .val = 12, .flags = RATE_IN_343X }, | |
304 | { .div = 13, .val = 13, .flags = RATE_IN_343X }, | |
305 | { .div = 14, .val = 14, .flags = RATE_IN_343X }, | |
306 | { .div = 15, .val = 15, .flags = RATE_IN_343X }, | |
307 | { .div = 16, .val = 16, .flags = RATE_IN_343X }, | |
308 | { .div = 0 } | |
309 | }; | |
310 | ||
311 | static const struct clksel_rate div31_dpll3_rates[] = { | |
312 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
313 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
314 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, | |
315 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, | |
316 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, | |
317 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, | |
318 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, | |
319 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, | |
320 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, | |
321 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, | |
322 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, | |
323 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, | |
324 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, | |
325 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, | |
326 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, | |
327 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, | |
328 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, | |
329 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, | |
330 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, | |
331 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, | |
332 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, | |
333 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, | |
334 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, | |
335 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, | |
336 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, | |
337 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, | |
338 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, | |
339 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, | |
340 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, | |
341 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, | |
342 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, | |
343 | { .div = 0 }, | |
344 | }; | |
345 | ||
346 | static const struct clksel div31_dpll3m2_clksel[] = { | |
347 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, | |
348 | { .parent = NULL } | |
349 | }; | |
350 | ||
351 | /* | |
352 | * REVISIT: Not sure what to do about clksel & these M2 divider clocks. | |
353 | * Shouldn't they be changed in SRAM? | |
354 | * This should probably remain a 'read-only' clksel clock. | |
355 | */ | |
356 | static struct clk dpll3_m2_ck = { | |
357 | .name = "dpll3_m2_ck", | |
358 | .parent = &dpll3_ck, | |
359 | .init = &omap2_init_clksel_parent, | |
360 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
361 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, | |
362 | .clksel = div31_dpll3m2_clksel, | |
363 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
364 | PARENT_CONTROLS_CLOCK, | |
365 | .recalc = &omap2_clksel_recalc, | |
366 | }; | |
367 | ||
368 | static struct clk core_ck = { | |
369 | .name = "core_ck", | |
370 | .parent = &dpll3_m2_ck, | |
371 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
372 | PARENT_CONTROLS_CLOCK, | |
373 | .recalc = &followparent_recalc, | |
374 | }; | |
375 | ||
376 | /* | |
377 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | |
378 | * DPLL isn't bypassed | |
379 | */ | |
380 | static struct clk dpll3_x2_ck = { | |
381 | .name = "dpll3_x2_ck", | |
382 | .parent = &core_ck, | |
383 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
384 | PARENT_CONTROLS_CLOCK, | |
385 | .recalc = &omap3_clkoutx2_recalc, | |
386 | }; | |
387 | ||
388 | static struct clk dpll3_m2x2_ck = { | |
389 | .name = "dpll3_m2x2_ck", | |
390 | .parent = &dpll3_x2_ck, | |
391 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
392 | PARENT_CONTROLS_CLOCK, | |
393 | .recalc = &followparent_recalc, | |
394 | }; | |
395 | ||
396 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
397 | static struct clk dpll3_m3x2_ck = { | |
398 | .name = "dpll3_m3x2_ck", | |
399 | .parent = &dpll3_x2_ck, | |
400 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
401 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, | |
402 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | |
403 | .recalc = &followparent_recalc, | |
404 | }; | |
405 | ||
406 | static const struct clksel div16_dpll3_clksel[] = { | |
407 | { .parent = &dpll3_x2_ck, .rates = div16_dpll_rates }, | |
408 | { .parent = NULL } | |
409 | }; | |
410 | ||
411 | static struct clk emu_core_alwon_ck = { | |
412 | .name = "emu_core_alwon_ck", | |
413 | .parent = &dpll3_x2_ck, | |
414 | .init = &omap2_init_clksel_parent, | |
415 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
416 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, | |
417 | .clksel = div16_dpll3_clksel, | |
418 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
419 | .recalc = &followparent_recalc, | |
420 | }; | |
421 | ||
422 | /* DPLL4 */ | |
423 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ | |
424 | /* Type: DPLL */ | |
425 | static const struct dpll_data dpll4_dd = { | |
426 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | |
427 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | |
428 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | |
429 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
430 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | |
431 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, | |
432 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, | |
433 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, | |
434 | }; | |
435 | ||
436 | static struct clk dpll4_ck = { | |
437 | .name = "dpll4_ck", | |
438 | .parent = &sys_ck, | |
439 | .dpll_data = &dpll4_dd, | |
440 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
441 | .recalc = &omap3_dpll_recalc, | |
442 | }; | |
443 | ||
444 | /* | |
445 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | |
446 | * DPLL isn't bypassed | |
447 | */ | |
448 | static struct clk dpll4_x2_ck = { | |
449 | .name = "dpll4_x2_ck", | |
450 | .parent = &dpll4_ck, | |
451 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
452 | PARENT_CONTROLS_CLOCK, | |
453 | .recalc = &omap3_clkoutx2_recalc, | |
454 | }; | |
455 | ||
456 | static const struct clksel div16_dpll4_clksel[] = { | |
457 | { .parent = &dpll4_x2_ck, .rates = div16_dpll_rates }, | |
458 | { .parent = NULL } | |
459 | }; | |
460 | ||
461 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
462 | static struct clk dpll4_m2x2_ck = { | |
463 | .name = "dpll4_m2x2_ck", | |
464 | .parent = &dpll4_x2_ck, | |
465 | .init = &omap2_init_clksel_parent, | |
466 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
467 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, | |
468 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | |
469 | .clksel_mask = OMAP3430_DIV_96M_MASK, | |
470 | .clksel = div16_dpll4_clksel, | |
471 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | |
472 | .recalc = &omap2_clksel_recalc, | |
473 | }; | |
474 | ||
475 | static struct clk omap_96m_alwon_fck = { | |
476 | .name = "omap_96m_alwon_fck", | |
477 | .parent = &dpll4_m2x2_ck, | |
478 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
479 | PARENT_CONTROLS_CLOCK, | |
480 | .recalc = &followparent_recalc, | |
481 | }; | |
482 | ||
483 | static struct clk omap_96m_fck = { | |
484 | .name = "omap_96m_fck", | |
485 | .parent = &omap_96m_alwon_fck, | |
486 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
487 | PARENT_CONTROLS_CLOCK, | |
488 | .recalc = &followparent_recalc, | |
489 | }; | |
490 | ||
491 | static struct clk cm_96m_fck = { | |
492 | .name = "cm_96m_fck", | |
493 | .parent = &dpll4_m2x2_ck, | |
494 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
495 | PARENT_CONTROLS_CLOCK, | |
496 | .recalc = &followparent_recalc, | |
497 | }; | |
498 | ||
499 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
500 | static struct clk dpll4_m3x2_ck = { | |
501 | .name = "dpll4_m3x2_ck", | |
502 | .parent = &dpll4_x2_ck, | |
503 | .init = &omap2_init_clksel_parent, | |
504 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
505 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, | |
506 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | |
507 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, | |
508 | .clksel = div16_dpll4_clksel, | |
509 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | |
510 | .recalc = &omap2_clksel_recalc, | |
511 | }; | |
512 | ||
513 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { | |
514 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
515 | { .div = 0 } | |
516 | }; | |
517 | ||
518 | static const struct clksel_rate omap_54m_alt_rates[] = { | |
519 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
520 | { .div = 0 } | |
521 | }; | |
522 | ||
523 | static const struct clksel omap_54m_clksel[] = { | |
524 | { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, | |
525 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, | |
526 | { .parent = NULL } | |
527 | }; | |
528 | ||
529 | static struct clk omap_54m_fck = { | |
530 | .name = "omap_54m_fck", | |
531 | .init = &omap2_init_clksel_parent, | |
532 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
533 | .clksel_mask = OMAP3430_SOURCE_54M, | |
534 | .clksel = omap_54m_clksel, | |
535 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
536 | PARENT_CONTROLS_CLOCK, | |
537 | .recalc = &omap2_clksel_recalc, | |
538 | }; | |
539 | ||
540 | static const struct clksel_rate omap_48m_96md2_rates[] = { | |
541 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
542 | { .div = 0 } | |
543 | }; | |
544 | ||
545 | static const struct clksel_rate omap_48m_alt_rates[] = { | |
546 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
547 | { .div = 0 } | |
548 | }; | |
549 | ||
550 | static const struct clksel omap_48m_clksel[] = { | |
551 | { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, | |
552 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, | |
553 | { .parent = NULL } | |
554 | }; | |
555 | ||
556 | static struct clk omap_48m_fck = { | |
557 | .name = "omap_48m_fck", | |
558 | .init = &omap2_init_clksel_parent, | |
559 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
560 | .clksel_mask = OMAP3430_SOURCE_48M, | |
561 | .clksel = omap_48m_clksel, | |
562 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
563 | PARENT_CONTROLS_CLOCK, | |
564 | .recalc = &omap2_clksel_recalc, | |
565 | }; | |
566 | ||
567 | static struct clk omap_12m_fck = { | |
568 | .name = "omap_12m_fck", | |
569 | .parent = &omap_48m_fck, | |
570 | .fixed_div = 4, | |
571 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
572 | PARENT_CONTROLS_CLOCK, | |
573 | .recalc = &omap2_fixed_divisor_recalc, | |
574 | }; | |
575 | ||
576 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
577 | static struct clk dpll4_m4x2_ck = { | |
578 | .name = "dpll4_m4x2_ck", | |
579 | .parent = &dpll4_x2_ck, | |
580 | .init = &omap2_init_clksel_parent, | |
581 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
582 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | |
583 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | |
584 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, | |
585 | .clksel = div16_dpll4_clksel, | |
586 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | |
587 | .recalc = &omap2_clksel_recalc, | |
588 | }; | |
589 | ||
590 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
591 | static struct clk dpll4_m5x2_ck = { | |
592 | .name = "dpll4_m5x2_ck", | |
593 | .parent = &dpll4_x2_ck, | |
594 | .init = &omap2_init_clksel_parent, | |
595 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
596 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | |
597 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | |
598 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, | |
599 | .clksel = div16_dpll4_clksel, | |
600 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | |
601 | .recalc = &omap2_clksel_recalc, | |
602 | }; | |
603 | ||
604 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
605 | static struct clk dpll4_m6x2_ck = { | |
606 | .name = "dpll4_m6x2_ck", | |
607 | .parent = &dpll4_x2_ck, | |
608 | .init = &omap2_init_clksel_parent, | |
609 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
610 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, | |
611 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
612 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, | |
613 | .clksel = div16_dpll4_clksel, | |
614 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | |
615 | .recalc = &omap2_clksel_recalc, | |
616 | }; | |
617 | ||
618 | static struct clk emu_per_alwon_ck = { | |
619 | .name = "emu_per_alwon_ck", | |
620 | .parent = &dpll4_m6x2_ck, | |
621 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
622 | PARENT_CONTROLS_CLOCK, | |
623 | .recalc = &followparent_recalc, | |
624 | }; | |
625 | ||
626 | /* DPLL5 */ | |
627 | /* Supplies 120MHz clock, USIM source clock */ | |
628 | /* Type: DPLL */ | |
629 | /* 3430ES2 only */ | |
630 | static const struct dpll_data dpll5_dd = { | |
631 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), | |
632 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, | |
633 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, | |
634 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), | |
635 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, | |
636 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, | |
637 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, | |
638 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, | |
639 | }; | |
640 | ||
641 | static struct clk dpll5_ck = { | |
642 | .name = "dpll5_ck", | |
643 | .parent = &sys_ck, | |
644 | .dpll_data = &dpll5_dd, | |
645 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | | |
646 | ALWAYS_ENABLED, | |
647 | .recalc = &omap3_dpll_recalc, | |
648 | }; | |
649 | ||
650 | static const struct clksel div16_dpll5m2_clksel[] = { | |
651 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, | |
652 | { .parent = NULL } | |
653 | }; | |
654 | ||
655 | static struct clk dpll5_m2_ck = { | |
656 | .name = "dpll5_m2_ck", | |
657 | .parent = &dpll5_ck, | |
658 | .init = &omap2_init_clksel_parent, | |
659 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), | |
660 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, | |
661 | .clksel = div16_dpll5m2_clksel, | |
662 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, | |
663 | .recalc = &omap2_clksel_recalc, | |
664 | }; | |
665 | ||
666 | static struct clk omap_120m_fck = { | |
667 | .name = "omap_120m_fck", | |
668 | .parent = &dpll5_m2_ck, | |
669 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, | |
670 | .recalc = &followparent_recalc, | |
671 | }; | |
672 | ||
673 | /* CM EXTERNAL CLOCK OUTPUTS */ | |
674 | ||
675 | static const struct clksel_rate clkout2_src_core_rates[] = { | |
676 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
677 | { .div = 0 } | |
678 | }; | |
679 | ||
680 | static const struct clksel_rate clkout2_src_sys_rates[] = { | |
681 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
682 | { .div = 0 } | |
683 | }; | |
684 | ||
685 | static const struct clksel_rate clkout2_src_96m_rates[] = { | |
686 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
687 | { .div = 0 } | |
688 | }; | |
689 | ||
690 | static const struct clksel_rate clkout2_src_54m_rates[] = { | |
691 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
692 | { .div = 0 } | |
693 | }; | |
694 | ||
695 | static const struct clksel clkout2_src_clksel[] = { | |
696 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, | |
697 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, | |
698 | { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, | |
699 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, | |
700 | { .parent = NULL } | |
701 | }; | |
702 | ||
703 | static struct clk clkout2_src_ck = { | |
704 | .name = "clkout2_src_ck", | |
705 | .init = &omap2_init_clksel_parent, | |
706 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, | |
707 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, | |
708 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | |
709 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, | |
710 | .clksel = clkout2_src_clksel, | |
711 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
712 | .recalc = &omap2_clksel_recalc, | |
713 | }; | |
714 | ||
715 | static const struct clksel_rate sys_clkout2_rates[] = { | |
716 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
717 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | |
718 | { .div = 4, .val = 2, .flags = RATE_IN_343X }, | |
719 | { .div = 8, .val = 3, .flags = RATE_IN_343X }, | |
720 | { .div = 16, .val = 4, .flags = RATE_IN_343X }, | |
721 | { .div = 0 }, | |
722 | }; | |
723 | ||
724 | static const struct clksel sys_clkout2_clksel[] = { | |
725 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, | |
726 | { .parent = NULL }, | |
727 | }; | |
728 | ||
729 | static struct clk sys_clkout2 = { | |
730 | .name = "sys_clkout2", | |
731 | .init = &omap2_init_clksel_parent, | |
732 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | |
733 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, | |
734 | .clksel = sys_clkout2_clksel, | |
735 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | |
736 | .recalc = &omap2_clksel_recalc, | |
737 | }; | |
738 | ||
739 | /* CM OUTPUT CLOCKS */ | |
740 | ||
741 | static struct clk corex2_fck = { | |
742 | .name = "corex2_fck", | |
743 | .parent = &dpll3_m2x2_ck, | |
744 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
745 | PARENT_CONTROLS_CLOCK, | |
746 | .recalc = &followparent_recalc, | |
747 | }; | |
748 | ||
749 | /* DPLL power domain clock controls */ | |
750 | ||
751 | static const struct clksel div2_core_clksel[] = { | |
752 | { .parent = &core_ck, .rates = div2_rates }, | |
753 | { .parent = NULL } | |
754 | }; | |
755 | ||
756 | /* TRM s. 4.7.7.4 lists the input for these two clocks as CORE_CK, | |
757 | but presuming that is an error, or at least an overgeneralization */ | |
758 | /* REVISIT: Are these in DPLL power domain or CM power domain? docs | |
759 | may be inconsistent here? */ | |
760 | static struct clk dpll1_fck = { | |
761 | .name = "dpll1_fck", | |
762 | .parent = &core_ck, | |
763 | .init = &omap2_init_clksel_parent, | |
764 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
765 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, | |
766 | .clksel = div2_core_clksel, | |
767 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
768 | PARENT_CONTROLS_CLOCK, | |
769 | .recalc = &omap2_clksel_recalc, | |
770 | }; | |
771 | ||
772 | static struct clk dpll2_fck = { | |
773 | .name = "dpll2_fck", | |
774 | .parent = &core_ck, | |
775 | .init = &omap2_init_clksel_parent, | |
776 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
777 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, | |
778 | .clksel = div2_core_clksel, | |
779 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
780 | PARENT_CONTROLS_CLOCK, | |
781 | .recalc = &omap2_clksel_recalc, | |
782 | }; | |
783 | ||
784 | /* Common interface clocks */ | |
785 | ||
786 | static struct clk l3_ick = { | |
787 | .name = "l3_ick", | |
788 | .parent = &core_ck, | |
789 | .init = &omap2_init_clksel_parent, | |
790 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
791 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, | |
792 | .clksel = div2_core_clksel, | |
793 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
794 | PARENT_CONTROLS_CLOCK, | |
795 | .recalc = &omap2_clksel_recalc, | |
796 | }; | |
797 | ||
798 | static const struct clksel div2_l3_clksel[] = { | |
799 | { .parent = &l3_ick, .rates = div2_rates }, | |
800 | { .parent = NULL } | |
801 | }; | |
802 | ||
803 | static struct clk l4_ick = { | |
804 | .name = "l4_ick", | |
805 | .parent = &l3_ick, | |
806 | .init = &omap2_init_clksel_parent, | |
807 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
808 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, | |
809 | .clksel = div2_l3_clksel, | |
810 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
811 | PARENT_CONTROLS_CLOCK, | |
812 | .recalc = &omap2_clksel_recalc, | |
813 | ||
814 | }; | |
815 | ||
816 | static const struct clksel div2_l4_clksel[] = { | |
817 | { .parent = &l4_ick, .rates = div2_rates }, | |
818 | { .parent = NULL } | |
819 | }; | |
820 | ||
821 | static struct clk rm_ick = { | |
822 | .name = "rm_ick", | |
823 | .parent = &l4_ick, | |
824 | .init = &omap2_init_clksel_parent, | |
825 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
826 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, | |
827 | .clksel = div2_l4_clksel, | |
828 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | |
829 | .recalc = &omap2_clksel_recalc, | |
830 | }; | |
831 | ||
832 | /* GFX power domain */ | |
833 | ||
834 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ | |
835 | ||
836 | static const struct clksel gfx_l3_clksel[] = { | |
837 | { .parent = &l3_ick, .rates = gfx_l3_rates }, | |
838 | { .parent = NULL } | |
839 | }; | |
840 | ||
841 | static struct clk gfx_l3_fck = { | |
842 | .name = "gfx_l3_fck", | |
843 | .parent = &l3_ick, | |
844 | .init = &omap2_init_clksel_parent, | |
845 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | |
846 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
847 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
848 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
849 | .clksel = gfx_l3_clksel, | |
850 | .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, | |
851 | .recalc = &omap2_clksel_recalc, | |
852 | }; | |
853 | ||
854 | static struct clk gfx_l3_ick = { | |
855 | .name = "gfx_l3_ick", | |
856 | .parent = &l3_ick, | |
857 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | |
858 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
859 | .flags = CLOCK_IN_OMAP3430ES1, | |
860 | .recalc = &followparent_recalc, | |
861 | }; | |
862 | ||
863 | static struct clk gfx_cg1_ck = { | |
864 | .name = "gfx_cg1_ck", | |
865 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | |
866 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | |
867 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | |
868 | .flags = CLOCK_IN_OMAP3430ES1, | |
869 | .recalc = &followparent_recalc, | |
870 | }; | |
871 | ||
872 | static struct clk gfx_cg2_ck = { | |
873 | .name = "gfx_cg2_ck", | |
874 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | |
875 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | |
876 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | |
877 | .flags = CLOCK_IN_OMAP3430ES1, | |
878 | .recalc = &followparent_recalc, | |
879 | }; | |
880 | ||
881 | /* SGX power domain - 3430ES2 only */ | |
882 | ||
883 | static const struct clksel_rate sgx_core_rates[] = { | |
884 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
885 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, | |
886 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, | |
887 | { .div = 0 }, | |
888 | }; | |
889 | ||
890 | static const struct clksel_rate sgx_96m_rates[] = { | |
891 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
892 | { .div = 0 }, | |
893 | }; | |
894 | ||
895 | static const struct clksel sgx_clksel[] = { | |
896 | { .parent = &core_ck, .rates = sgx_core_rates }, | |
897 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, | |
898 | { .parent = NULL }, | |
899 | }; | |
900 | ||
901 | static struct clk sgx_fck = { | |
902 | .name = "sgx_fck", | |
903 | .init = &omap2_init_clksel_parent, | |
904 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), | |
905 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | |
906 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), | |
907 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, | |
908 | .clksel = sgx_clksel, | |
909 | .flags = CLOCK_IN_OMAP3430ES2, | |
910 | .recalc = &omap2_clksel_recalc, | |
911 | }; | |
912 | ||
913 | static struct clk sgx_ick = { | |
914 | .name = "sgx_ick", | |
915 | .parent = &l3_ick, | |
916 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), | |
917 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | |
918 | .flags = CLOCK_IN_OMAP3430ES2, | |
919 | .recalc = &followparent_recalc, | |
920 | }; | |
921 | ||
922 | /* CORE power domain */ | |
923 | ||
924 | static struct clk d2d_26m_fck = { | |
925 | .name = "d2d_26m_fck", | |
926 | .parent = &sys_ck, | |
927 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
928 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | |
929 | .flags = CLOCK_IN_OMAP3430ES1, | |
930 | .recalc = &followparent_recalc, | |
931 | }; | |
932 | ||
933 | static const struct clksel omap343x_gpt_clksel[] = { | |
934 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, | |
935 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | |
936 | { .parent = NULL} | |
937 | }; | |
938 | ||
939 | static struct clk gpt10_fck = { | |
940 | .name = "gpt10_fck", | |
941 | .parent = &sys_ck, | |
942 | .init = &omap2_init_clksel_parent, | |
943 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
944 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | |
945 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
946 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, | |
947 | .clksel = omap343x_gpt_clksel, | |
948 | .flags = CLOCK_IN_OMAP343X, | |
949 | .recalc = &omap2_clksel_recalc, | |
950 | }; | |
951 | ||
952 | static struct clk gpt11_fck = { | |
953 | .name = "gpt11_fck", | |
954 | .parent = &sys_ck, | |
955 | .init = &omap2_init_clksel_parent, | |
956 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
957 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | |
958 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
959 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, | |
960 | .clksel = omap343x_gpt_clksel, | |
961 | .flags = CLOCK_IN_OMAP343X, | |
962 | .recalc = &omap2_clksel_recalc, | |
963 | }; | |
964 | ||
965 | static struct clk cpefuse_fck = { | |
966 | .name = "cpefuse_fck", | |
967 | .parent = &sys_ck, | |
968 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
969 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | |
970 | .flags = CLOCK_IN_OMAP3430ES2, | |
971 | .recalc = &followparent_recalc, | |
972 | }; | |
973 | ||
974 | static struct clk ts_fck = { | |
975 | .name = "ts_fck", | |
976 | .parent = &omap_32k_fck, | |
977 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
978 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | |
979 | .flags = CLOCK_IN_OMAP3430ES2, | |
980 | .recalc = &followparent_recalc, | |
981 | }; | |
982 | ||
983 | static struct clk usbtll_fck = { | |
984 | .name = "usbtll_fck", | |
985 | .parent = &omap_120m_fck, | |
986 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
987 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
988 | .flags = CLOCK_IN_OMAP3430ES2, | |
989 | .recalc = &followparent_recalc, | |
990 | }; | |
991 | ||
992 | /* CORE 96M FCLK-derived clocks */ | |
993 | ||
994 | static struct clk core_96m_fck = { | |
995 | .name = "core_96m_fck", | |
996 | .parent = &omap_96m_fck, | |
997 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
998 | PARENT_CONTROLS_CLOCK, | |
999 | .recalc = &followparent_recalc, | |
1000 | }; | |
1001 | ||
1002 | static struct clk mmchs3_fck = { | |
1003 | .name = "mmchs_fck", | |
1004 | .id = 3, | |
1005 | .parent = &core_96m_fck, | |
1006 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1007 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | |
1008 | .flags = CLOCK_IN_OMAP3430ES2, | |
1009 | .recalc = &followparent_recalc, | |
1010 | }; | |
1011 | ||
1012 | static struct clk mmchs2_fck = { | |
1013 | .name = "mmchs_fck", | |
1014 | .id = 2, | |
1015 | .parent = &core_96m_fck, | |
1016 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1017 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | |
1018 | .flags = CLOCK_IN_OMAP343X, | |
1019 | .recalc = &followparent_recalc, | |
1020 | }; | |
1021 | ||
1022 | static struct clk mspro_fck = { | |
1023 | .name = "mspro_fck", | |
1024 | .parent = &core_96m_fck, | |
1025 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1026 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | |
1027 | .flags = CLOCK_IN_OMAP343X, | |
1028 | .recalc = &followparent_recalc, | |
1029 | }; | |
1030 | ||
1031 | static struct clk mmchs1_fck = { | |
1032 | .name = "mmchs_fck", | |
1033 | .id = 1, | |
1034 | .parent = &core_96m_fck, | |
1035 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1036 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | |
1037 | .flags = CLOCK_IN_OMAP343X, | |
1038 | .recalc = &followparent_recalc, | |
1039 | }; | |
1040 | ||
1041 | static struct clk i2c3_fck = { | |
1042 | .name = "i2c_fck", | |
1043 | .id = 3, | |
1044 | .parent = &core_96m_fck, | |
1045 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1046 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | |
1047 | .flags = CLOCK_IN_OMAP343X, | |
1048 | .recalc = &followparent_recalc, | |
1049 | }; | |
1050 | ||
1051 | static struct clk i2c2_fck = { | |
1052 | .name = "i2c_fck", | |
1053 | .id = 2, | |
1054 | .parent = &core_96m_fck, | |
1055 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1056 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | |
1057 | .flags = CLOCK_IN_OMAP343X, | |
1058 | .recalc = &followparent_recalc, | |
1059 | }; | |
1060 | ||
1061 | static struct clk i2c1_fck = { | |
1062 | .name = "i2c_fck", | |
1063 | .id = 1, | |
1064 | .parent = &core_96m_fck, | |
1065 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1066 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | |
1067 | .flags = CLOCK_IN_OMAP343X, | |
1068 | .recalc = &followparent_recalc, | |
1069 | }; | |
1070 | ||
1071 | /* | |
1072 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; | |
1073 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. | |
1074 | */ | |
1075 | static const struct clksel_rate common_mcbsp_96m_rates[] = { | |
1076 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1077 | { .div = 0 } | |
1078 | }; | |
1079 | ||
1080 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { | |
1081 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1082 | { .div = 0 } | |
1083 | }; | |
1084 | ||
1085 | static const struct clksel mcbsp_15_clksel[] = { | |
1086 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, | |
1087 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | |
1088 | { .parent = NULL } | |
1089 | }; | |
1090 | ||
1091 | static struct clk mcbsp5_fck = { | |
1092 | .name = "mcbsp5_fck", | |
1093 | .init = &omap2_init_clksel_parent, | |
1094 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1095 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | |
1096 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
1097 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | |
1098 | .clksel = mcbsp_15_clksel, | |
1099 | .flags = CLOCK_IN_OMAP343X, | |
1100 | .recalc = &omap2_clksel_recalc, | |
1101 | }; | |
1102 | ||
1103 | static struct clk mcbsp1_fck = { | |
1104 | .name = "mcbsp1_fck", | |
1105 | .init = &omap2_init_clksel_parent, | |
1106 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1107 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1108 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
1109 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | |
1110 | .clksel = mcbsp_15_clksel, | |
1111 | .flags = CLOCK_IN_OMAP343X, | |
1112 | .recalc = &omap2_clksel_recalc, | |
1113 | }; | |
1114 | ||
1115 | /* CORE_48M_FCK-derived clocks */ | |
1116 | ||
1117 | static struct clk core_48m_fck = { | |
1118 | .name = "core_48m_fck", | |
1119 | .parent = &omap_48m_fck, | |
1120 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1121 | PARENT_CONTROLS_CLOCK, | |
1122 | .recalc = &followparent_recalc, | |
1123 | }; | |
1124 | ||
1125 | static struct clk mcspi4_fck = { | |
1126 | .name = "mcspi_fck", | |
1127 | .id = 4, | |
1128 | .parent = &core_48m_fck, | |
1129 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1130 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
1131 | .flags = CLOCK_IN_OMAP343X, | |
1132 | .recalc = &followparent_recalc, | |
1133 | }; | |
1134 | ||
1135 | static struct clk mcspi3_fck = { | |
1136 | .name = "mcspi_fck", | |
1137 | .id = 3, | |
1138 | .parent = &core_48m_fck, | |
1139 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1140 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
1141 | .flags = CLOCK_IN_OMAP343X, | |
1142 | .recalc = &followparent_recalc, | |
1143 | }; | |
1144 | ||
1145 | static struct clk mcspi2_fck = { | |
1146 | .name = "mcspi_fck", | |
1147 | .id = 2, | |
1148 | .parent = &core_48m_fck, | |
1149 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1150 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
1151 | .flags = CLOCK_IN_OMAP343X, | |
1152 | .recalc = &followparent_recalc, | |
1153 | }; | |
1154 | ||
1155 | static struct clk mcspi1_fck = { | |
1156 | .name = "mcspi_fck", | |
1157 | .id = 1, | |
1158 | .parent = &core_48m_fck, | |
1159 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1160 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1161 | .flags = CLOCK_IN_OMAP343X, | |
1162 | .recalc = &followparent_recalc, | |
1163 | }; | |
1164 | ||
1165 | static struct clk uart2_fck = { | |
1166 | .name = "uart2_fck", | |
1167 | .parent = &core_48m_fck, | |
1168 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1169 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | |
1170 | .flags = CLOCK_IN_OMAP343X, | |
1171 | .recalc = &followparent_recalc, | |
1172 | }; | |
1173 | ||
1174 | static struct clk uart1_fck = { | |
1175 | .name = "uart1_fck", | |
1176 | .parent = &core_48m_fck, | |
1177 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1178 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | |
1179 | .flags = CLOCK_IN_OMAP343X, | |
1180 | .recalc = &followparent_recalc, | |
1181 | }; | |
1182 | ||
1183 | static struct clk fshostusb_fck = { | |
1184 | .name = "fshostusb_fck", | |
1185 | .parent = &core_48m_fck, | |
1186 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1187 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | |
1188 | .flags = CLOCK_IN_OMAP3430ES1, | |
1189 | .recalc = &followparent_recalc, | |
1190 | }; | |
1191 | ||
1192 | /* CORE_12M_FCK based clocks */ | |
1193 | ||
1194 | static struct clk core_12m_fck = { | |
1195 | .name = "core_12m_fck", | |
1196 | .parent = &omap_12m_fck, | |
1197 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1198 | PARENT_CONTROLS_CLOCK, | |
1199 | .recalc = &followparent_recalc, | |
1200 | }; | |
1201 | ||
1202 | static struct clk hdq_fck = { | |
1203 | .name = "hdq_fck", | |
1204 | .parent = &core_12m_fck, | |
1205 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1206 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | |
1207 | .flags = CLOCK_IN_OMAP343X, | |
1208 | .recalc = &followparent_recalc, | |
1209 | }; | |
1210 | ||
1211 | /* DPLL3-derived clock */ | |
1212 | ||
1213 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { | |
1214 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1215 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
1216 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
1217 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
1218 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
1219 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
1220 | { .div = 0 } | |
1221 | }; | |
1222 | ||
1223 | static const struct clksel ssi_ssr_clksel[] = { | |
1224 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, | |
1225 | { .parent = NULL } | |
1226 | }; | |
1227 | ||
1228 | static struct clk ssi_ssr_fck = { | |
1229 | .name = "ssi_ssr_fck", | |
1230 | .init = &omap2_init_clksel_parent, | |
1231 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1232 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1233 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1234 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | |
1235 | .clksel = ssi_ssr_clksel, | |
1236 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
1237 | .recalc = &omap2_clksel_recalc, | |
1238 | }; | |
1239 | ||
1240 | static struct clk ssi_sst_fck = { | |
1241 | .name = "ssi_sst_fck", | |
1242 | .parent = &ssi_ssr_fck, | |
1243 | .fixed_div = 2, | |
1244 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | |
1245 | .recalc = &omap2_fixed_divisor_recalc, | |
1246 | }; | |
1247 | ||
1248 | ||
1249 | ||
1250 | /* CORE_L3_ICK based clocks */ | |
1251 | ||
1252 | static struct clk core_l3_ick = { | |
1253 | .name = "core_l3_ick", | |
1254 | .parent = &l3_ick, | |
1255 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1256 | PARENT_CONTROLS_CLOCK, | |
1257 | .recalc = &followparent_recalc, | |
1258 | }; | |
1259 | ||
1260 | static struct clk hsotgusb_ick = { | |
1261 | .name = "hsotgusb_ick", | |
1262 | .parent = &core_l3_ick, | |
1263 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1264 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | |
1265 | .flags = CLOCK_IN_OMAP343X, | |
1266 | .recalc = &followparent_recalc, | |
1267 | }; | |
1268 | ||
1269 | static struct clk sdrc_ick = { | |
1270 | .name = "sdrc_ick", | |
1271 | .parent = &core_l3_ick, | |
1272 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1273 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, | |
1274 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | |
1275 | .recalc = &followparent_recalc, | |
1276 | }; | |
1277 | ||
1278 | static struct clk gpmc_fck = { | |
1279 | .name = "gpmc_fck", | |
1280 | .parent = &core_l3_ick, | |
1281 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | | |
1282 | ENABLE_ON_INIT, | |
1283 | .recalc = &followparent_recalc, | |
1284 | }; | |
1285 | ||
1286 | /* SECURITY_L3_ICK based clocks */ | |
1287 | ||
1288 | static struct clk security_l3_ick = { | |
1289 | .name = "security_l3_ick", | |
1290 | .parent = &l3_ick, | |
1291 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1292 | PARENT_CONTROLS_CLOCK, | |
1293 | .recalc = &followparent_recalc, | |
1294 | }; | |
1295 | ||
1296 | static struct clk pka_ick = { | |
1297 | .name = "pka_ick", | |
1298 | .parent = &security_l3_ick, | |
1299 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1300 | .enable_bit = OMAP3430_EN_PKA_SHIFT, | |
1301 | .flags = CLOCK_IN_OMAP343X, | |
1302 | .recalc = &followparent_recalc, | |
1303 | }; | |
1304 | ||
1305 | /* CORE_L4_ICK based clocks */ | |
1306 | ||
1307 | static struct clk core_l4_ick = { | |
1308 | .name = "core_l4_ick", | |
1309 | .parent = &l4_ick, | |
1310 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1311 | PARENT_CONTROLS_CLOCK, | |
1312 | .recalc = &followparent_recalc, | |
1313 | }; | |
1314 | ||
1315 | static struct clk usbtll_ick = { | |
1316 | .name = "usbtll_ick", | |
1317 | .parent = &core_l4_ick, | |
1318 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | |
1319 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
1320 | .flags = CLOCK_IN_OMAP3430ES2, | |
1321 | .recalc = &followparent_recalc, | |
1322 | }; | |
1323 | ||
1324 | static struct clk mmchs3_ick = { | |
1325 | .name = "mmchs_ick", | |
1326 | .id = 3, | |
1327 | .parent = &core_l4_ick, | |
1328 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1329 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | |
1330 | .flags = CLOCK_IN_OMAP3430ES2, | |
1331 | .recalc = &followparent_recalc, | |
1332 | }; | |
1333 | ||
1334 | /* Intersystem Communication Registers - chassis mode only */ | |
1335 | static struct clk icr_ick = { | |
1336 | .name = "icr_ick", | |
1337 | .parent = &core_l4_ick, | |
1338 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1339 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | |
1340 | .flags = CLOCK_IN_OMAP343X, | |
1341 | .recalc = &followparent_recalc, | |
1342 | }; | |
1343 | ||
1344 | static struct clk aes2_ick = { | |
1345 | .name = "aes2_ick", | |
1346 | .parent = &core_l4_ick, | |
1347 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1348 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | |
1349 | .flags = CLOCK_IN_OMAP343X, | |
1350 | .recalc = &followparent_recalc, | |
1351 | }; | |
1352 | ||
1353 | static struct clk sha12_ick = { | |
1354 | .name = "sha12_ick", | |
1355 | .parent = &core_l4_ick, | |
1356 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1357 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | |
1358 | .flags = CLOCK_IN_OMAP343X, | |
1359 | .recalc = &followparent_recalc, | |
1360 | }; | |
1361 | ||
1362 | static struct clk des2_ick = { | |
1363 | .name = "des2_ick", | |
1364 | .parent = &core_l4_ick, | |
1365 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1366 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | |
1367 | .flags = CLOCK_IN_OMAP343X, | |
1368 | .recalc = &followparent_recalc, | |
1369 | }; | |
1370 | ||
1371 | static struct clk mmchs2_ick = { | |
1372 | .name = "mmchs_ick", | |
1373 | .id = 2, | |
1374 | .parent = &core_l4_ick, | |
1375 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1376 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | |
1377 | .flags = CLOCK_IN_OMAP343X, | |
1378 | .recalc = &followparent_recalc, | |
1379 | }; | |
1380 | ||
1381 | static struct clk mmchs1_ick = { | |
1382 | .name = "mmchs_ick", | |
1383 | .id = 1, | |
1384 | .parent = &core_l4_ick, | |
1385 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1386 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | |
1387 | .flags = CLOCK_IN_OMAP343X, | |
1388 | .recalc = &followparent_recalc, | |
1389 | }; | |
1390 | ||
1391 | static struct clk mspro_ick = { | |
1392 | .name = "mspro_ick", | |
1393 | .parent = &core_l4_ick, | |
1394 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1395 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | |
1396 | .flags = CLOCK_IN_OMAP343X, | |
1397 | .recalc = &followparent_recalc, | |
1398 | }; | |
1399 | ||
1400 | static struct clk hdq_ick = { | |
1401 | .name = "hdq_ick", | |
1402 | .parent = &core_l4_ick, | |
1403 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1404 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | |
1405 | .flags = CLOCK_IN_OMAP343X, | |
1406 | .recalc = &followparent_recalc, | |
1407 | }; | |
1408 | ||
1409 | static struct clk mcspi4_ick = { | |
1410 | .name = "mcspi_ick", | |
1411 | .id = 4, | |
1412 | .parent = &core_l4_ick, | |
1413 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1414 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
1415 | .flags = CLOCK_IN_OMAP343X, | |
1416 | .recalc = &followparent_recalc, | |
1417 | }; | |
1418 | ||
1419 | static struct clk mcspi3_ick = { | |
1420 | .name = "mcspi_ick", | |
1421 | .id = 3, | |
1422 | .parent = &core_l4_ick, | |
1423 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1424 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
1425 | .flags = CLOCK_IN_OMAP343X, | |
1426 | .recalc = &followparent_recalc, | |
1427 | }; | |
1428 | ||
1429 | static struct clk mcspi2_ick = { | |
1430 | .name = "mcspi_ick", | |
1431 | .id = 2, | |
1432 | .parent = &core_l4_ick, | |
1433 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1434 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
1435 | .flags = CLOCK_IN_OMAP343X, | |
1436 | .recalc = &followparent_recalc, | |
1437 | }; | |
1438 | ||
1439 | static struct clk mcspi1_ick = { | |
1440 | .name = "mcspi_ick", | |
1441 | .id = 1, | |
1442 | .parent = &core_l4_ick, | |
1443 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1444 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1445 | .flags = CLOCK_IN_OMAP343X, | |
1446 | .recalc = &followparent_recalc, | |
1447 | }; | |
1448 | ||
1449 | static struct clk i2c3_ick = { | |
1450 | .name = "i2c_ick", | |
1451 | .id = 3, | |
1452 | .parent = &core_l4_ick, | |
1453 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1454 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | |
1455 | .flags = CLOCK_IN_OMAP343X, | |
1456 | .recalc = &followparent_recalc, | |
1457 | }; | |
1458 | ||
1459 | static struct clk i2c2_ick = { | |
1460 | .name = "i2c_ick", | |
1461 | .id = 2, | |
1462 | .parent = &core_l4_ick, | |
1463 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1464 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | |
1465 | .flags = CLOCK_IN_OMAP343X, | |
1466 | .recalc = &followparent_recalc, | |
1467 | }; | |
1468 | ||
1469 | static struct clk i2c1_ick = { | |
1470 | .name = "i2c_ick", | |
1471 | .id = 1, | |
1472 | .parent = &core_l4_ick, | |
1473 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1474 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | |
1475 | .flags = CLOCK_IN_OMAP343X, | |
1476 | .recalc = &followparent_recalc, | |
1477 | }; | |
1478 | ||
1479 | static struct clk uart2_ick = { | |
1480 | .name = "uart2_ick", | |
1481 | .parent = &core_l4_ick, | |
1482 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1483 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | |
1484 | .flags = CLOCK_IN_OMAP343X, | |
1485 | .recalc = &followparent_recalc, | |
1486 | }; | |
1487 | ||
1488 | static struct clk uart1_ick = { | |
1489 | .name = "uart1_ick", | |
1490 | .parent = &core_l4_ick, | |
1491 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1492 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | |
1493 | .flags = CLOCK_IN_OMAP343X, | |
1494 | .recalc = &followparent_recalc, | |
1495 | }; | |
1496 | ||
1497 | static struct clk gpt11_ick = { | |
1498 | .name = "gpt11_ick", | |
1499 | .parent = &core_l4_ick, | |
1500 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1501 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | |
1502 | .flags = CLOCK_IN_OMAP343X, | |
1503 | .recalc = &followparent_recalc, | |
1504 | }; | |
1505 | ||
1506 | static struct clk gpt10_ick = { | |
1507 | .name = "gpt10_ick", | |
1508 | .parent = &core_l4_ick, | |
1509 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1510 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | |
1511 | .flags = CLOCK_IN_OMAP343X, | |
1512 | .recalc = &followparent_recalc, | |
1513 | }; | |
1514 | ||
1515 | static struct clk mcbsp5_ick = { | |
1516 | .name = "mcbsp5_ick", | |
1517 | .parent = &core_l4_ick, | |
1518 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1519 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | |
1520 | .flags = CLOCK_IN_OMAP343X, | |
1521 | .recalc = &followparent_recalc, | |
1522 | }; | |
1523 | ||
1524 | static struct clk mcbsp1_ick = { | |
1525 | .name = "mcbsp1_ick", | |
1526 | .parent = &core_l4_ick, | |
1527 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1528 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1529 | .flags = CLOCK_IN_OMAP343X, | |
1530 | .recalc = &followparent_recalc, | |
1531 | }; | |
1532 | ||
1533 | static struct clk fac_ick = { | |
1534 | .name = "fac_ick", | |
1535 | .parent = &core_l4_ick, | |
1536 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1537 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | |
1538 | .flags = CLOCK_IN_OMAP3430ES1, | |
1539 | .recalc = &followparent_recalc, | |
1540 | }; | |
1541 | ||
1542 | static struct clk mailboxes_ick = { | |
1543 | .name = "mailboxes_ick", | |
1544 | .parent = &core_l4_ick, | |
1545 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1546 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | |
1547 | .flags = CLOCK_IN_OMAP343X, | |
1548 | .recalc = &followparent_recalc, | |
1549 | }; | |
1550 | ||
1551 | static struct clk omapctrl_ick = { | |
1552 | .name = "omapctrl_ick", | |
1553 | .parent = &core_l4_ick, | |
1554 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1555 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | |
1556 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | |
1557 | .recalc = &followparent_recalc, | |
1558 | }; | |
1559 | ||
1560 | /* SSI_L4_ICK based clocks */ | |
1561 | ||
1562 | static struct clk ssi_l4_ick = { | |
1563 | .name = "ssi_l4_ick", | |
1564 | .parent = &l4_ick, | |
1565 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
1566 | .recalc = &followparent_recalc, | |
1567 | }; | |
1568 | ||
1569 | static struct clk ssi_ick = { | |
1570 | .name = "ssi_ick", | |
1571 | .parent = &ssi_l4_ick, | |
1572 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1573 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1574 | .flags = CLOCK_IN_OMAP343X, | |
1575 | .recalc = &followparent_recalc, | |
1576 | }; | |
1577 | ||
1578 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, | |
1579 | * but l4_ick makes more sense to me */ | |
1580 | ||
1581 | static const struct clksel usb_l4_clksel[] = { | |
1582 | { .parent = &l4_ick, .rates = div2_rates }, | |
1583 | { .parent = NULL }, | |
1584 | }; | |
1585 | ||
1586 | static struct clk usb_l4_ick = { | |
1587 | .name = "usb_l4_ick", | |
1588 | .parent = &l4_ick, | |
1589 | .init = &omap2_init_clksel_parent, | |
1590 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1591 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | |
1592 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1593 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | |
1594 | .clksel = usb_l4_clksel, | |
1595 | .flags = CLOCK_IN_OMAP3430ES1, | |
1596 | .recalc = &omap2_clksel_recalc, | |
1597 | }; | |
1598 | ||
1599 | /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */ | |
1600 | ||
1601 | /* SECURITY_L4_ICK2 based clocks */ | |
1602 | ||
1603 | static struct clk security_l4_ick2 = { | |
1604 | .name = "security_l4_ick2", | |
1605 | .parent = &l4_ick, | |
1606 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1607 | PARENT_CONTROLS_CLOCK, | |
1608 | .recalc = &followparent_recalc, | |
1609 | }; | |
1610 | ||
1611 | static struct clk aes1_ick = { | |
1612 | .name = "aes1_ick", | |
1613 | .parent = &security_l4_ick2, | |
1614 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1615 | .enable_bit = OMAP3430_EN_AES1_SHIFT, | |
1616 | .flags = CLOCK_IN_OMAP343X, | |
1617 | .recalc = &followparent_recalc, | |
1618 | }; | |
1619 | ||
1620 | static struct clk rng_ick = { | |
1621 | .name = "rng_ick", | |
1622 | .parent = &security_l4_ick2, | |
1623 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1624 | .enable_bit = OMAP3430_EN_RNG_SHIFT, | |
1625 | .flags = CLOCK_IN_OMAP343X, | |
1626 | .recalc = &followparent_recalc, | |
1627 | }; | |
1628 | ||
1629 | static struct clk sha11_ick = { | |
1630 | .name = "sha11_ick", | |
1631 | .parent = &security_l4_ick2, | |
1632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1633 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, | |
1634 | .flags = CLOCK_IN_OMAP343X, | |
1635 | .recalc = &followparent_recalc, | |
1636 | }; | |
1637 | ||
1638 | static struct clk des1_ick = { | |
1639 | .name = "des1_ick", | |
1640 | .parent = &security_l4_ick2, | |
1641 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1642 | .enable_bit = OMAP3430_EN_DES1_SHIFT, | |
1643 | .flags = CLOCK_IN_OMAP343X, | |
1644 | .recalc = &followparent_recalc, | |
1645 | }; | |
1646 | ||
1647 | /* DSS */ | |
1648 | ||
1649 | static struct clk dss1_alwon_fck = { | |
1650 | .name = "dss1_alwon_fck", | |
1651 | .parent = &dpll4_m4x2_ck, | |
1652 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
1653 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | |
1654 | .flags = CLOCK_IN_OMAP343X, | |
1655 | .recalc = &followparent_recalc, | |
1656 | }; | |
1657 | ||
1658 | static struct clk dss_tv_fck = { | |
1659 | .name = "dss_tv_fck", | |
1660 | .parent = &omap_54m_fck, | |
1661 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
1662 | .enable_bit = OMAP3430_EN_TV_SHIFT, | |
1663 | .flags = CLOCK_IN_OMAP343X, | |
1664 | .recalc = &followparent_recalc, | |
1665 | }; | |
1666 | ||
1667 | static struct clk dss_96m_fck = { | |
1668 | .name = "dss_96m_fck", | |
1669 | .parent = &omap_96m_fck, | |
1670 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
1671 | .enable_bit = OMAP3430_EN_TV_SHIFT, | |
1672 | .flags = CLOCK_IN_OMAP343X, | |
1673 | .recalc = &followparent_recalc, | |
1674 | }; | |
1675 | ||
1676 | static struct clk dss2_alwon_fck = { | |
1677 | .name = "dss2_alwon_fck", | |
1678 | .parent = &sys_ck, | |
1679 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
1680 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | |
1681 | .flags = CLOCK_IN_OMAP343X, | |
1682 | .recalc = &followparent_recalc, | |
1683 | }; | |
1684 | ||
1685 | static struct clk dss_ick = { | |
1686 | /* Handles both L3 and L4 clocks */ | |
1687 | .name = "dss_ick", | |
1688 | .parent = &l4_ick, | |
1689 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | |
1690 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | |
1691 | .flags = CLOCK_IN_OMAP343X, | |
1692 | .recalc = &followparent_recalc, | |
1693 | }; | |
1694 | ||
1695 | /* CAM */ | |
1696 | ||
1697 | static struct clk cam_mclk = { | |
1698 | .name = "cam_mclk", | |
1699 | .parent = &dpll4_m5x2_ck, | |
1700 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | |
1701 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
1702 | .flags = CLOCK_IN_OMAP343X, | |
1703 | .recalc = &followparent_recalc, | |
1704 | }; | |
1705 | ||
1706 | static struct clk cam_l3_ick = { | |
1707 | .name = "cam_l3_ick", | |
1708 | .parent = &l3_ick, | |
1709 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | |
1710 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
1711 | .flags = CLOCK_IN_OMAP343X, | |
1712 | .recalc = &followparent_recalc, | |
1713 | }; | |
1714 | ||
1715 | static struct clk cam_l4_ick = { | |
1716 | .name = "cam_l4_ick", | |
1717 | .parent = &l4_ick, | |
1718 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | |
1719 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
1720 | .flags = CLOCK_IN_OMAP343X, | |
1721 | .recalc = &followparent_recalc, | |
1722 | }; | |
1723 | ||
1724 | /* USBHOST - 3430ES2 only */ | |
1725 | ||
1726 | static struct clk usbhost_120m_fck = { | |
1727 | .name = "usbhost_120m_fck", | |
1728 | .parent = &omap_120m_fck, | |
1729 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | |
1730 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | |
1731 | .flags = CLOCK_IN_OMAP3430ES2, | |
1732 | .recalc = &followparent_recalc, | |
1733 | }; | |
1734 | ||
1735 | static struct clk usbhost_48m_fck = { | |
1736 | .name = "usbhost_48m_fck", | |
1737 | .parent = &omap_48m_fck, | |
1738 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | |
1739 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | |
1740 | .flags = CLOCK_IN_OMAP3430ES2, | |
1741 | .recalc = &followparent_recalc, | |
1742 | }; | |
1743 | ||
1744 | static struct clk usbhost_l3_ick = { | |
1745 | .name = "usbhost_l3_ick", | |
1746 | .parent = &l3_ick, | |
1747 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | |
1748 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | |
1749 | .flags = CLOCK_IN_OMAP3430ES2, | |
1750 | .recalc = &followparent_recalc, | |
1751 | }; | |
1752 | ||
1753 | static struct clk usbhost_l4_ick = { | |
1754 | .name = "usbhost_l4_ick", | |
1755 | .parent = &l4_ick, | |
1756 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | |
1757 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | |
1758 | .flags = CLOCK_IN_OMAP3430ES2, | |
1759 | .recalc = &followparent_recalc, | |
1760 | }; | |
1761 | ||
1762 | static struct clk usbhost_sar_fck = { | |
1763 | .name = "usbhost_sar_fck", | |
1764 | .parent = &osc_sys_ck, | |
1765 | .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), | |
1766 | .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, | |
1767 | .flags = CLOCK_IN_OMAP3430ES2, | |
1768 | .recalc = &followparent_recalc, | |
1769 | }; | |
1770 | ||
1771 | /* WKUP */ | |
1772 | ||
1773 | static const struct clksel_rate usim_96m_rates[] = { | |
1774 | { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1775 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
1776 | { .div = 8, .val = 5, .flags = RATE_IN_343X }, | |
1777 | { .div = 10, .val = 6, .flags = RATE_IN_343X }, | |
1778 | { .div = 0 }, | |
1779 | }; | |
1780 | ||
1781 | static const struct clksel_rate usim_120m_rates[] = { | |
1782 | { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1783 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
1784 | { .div = 16, .val = 9, .flags = RATE_IN_343X }, | |
1785 | { .div = 20, .val = 10, .flags = RATE_IN_343X }, | |
1786 | { .div = 0 }, | |
1787 | }; | |
1788 | ||
1789 | static const struct clksel usim_clksel[] = { | |
1790 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, | |
1791 | { .parent = &omap_120m_fck, .rates = usim_120m_rates }, | |
1792 | { .parent = &sys_ck, .rates = div2_rates }, | |
1793 | { .parent = NULL }, | |
1794 | }; | |
1795 | ||
1796 | /* 3430ES2 only */ | |
1797 | static struct clk usim_fck = { | |
1798 | .name = "usim_fck", | |
1799 | .init = &omap2_init_clksel_parent, | |
1800 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
1801 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | |
1802 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
1803 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, | |
1804 | .clksel = usim_clksel, | |
1805 | .flags = CLOCK_IN_OMAP3430ES2, | |
1806 | .recalc = &omap2_clksel_recalc, | |
1807 | }; | |
1808 | ||
1809 | static struct clk gpt1_fck = { | |
1810 | .name = "gpt1_fck", | |
1811 | .init = &omap2_init_clksel_parent, | |
1812 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
1813 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | |
1814 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
1815 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, | |
1816 | .clksel = omap343x_gpt_clksel, | |
1817 | .flags = CLOCK_IN_OMAP343X, | |
1818 | .recalc = &omap2_clksel_recalc, | |
1819 | }; | |
1820 | ||
1821 | static struct clk wkup_32k_fck = { | |
1822 | .name = "wkup_32k_fck", | |
1823 | .parent = &omap_32k_fck, | |
1824 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
1825 | .recalc = &followparent_recalc, | |
1826 | }; | |
1827 | ||
1828 | static struct clk gpio1_fck = { | |
1829 | .name = "gpio1_fck", | |
1830 | .parent = &wkup_32k_fck, | |
1831 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
1832 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | |
1833 | .flags = CLOCK_IN_OMAP343X, | |
1834 | .recalc = &followparent_recalc, | |
1835 | }; | |
1836 | ||
1837 | static struct clk wdt2_fck = { | |
1838 | .name = "wdt2_fck", | |
1839 | .parent = &wkup_32k_fck, | |
1840 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
1841 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | |
1842 | .flags = CLOCK_IN_OMAP343X, | |
1843 | .recalc = &followparent_recalc, | |
1844 | }; | |
1845 | ||
1846 | static struct clk wkup_l4_ick = { | |
1847 | .name = "wkup_l4_ick", | |
1848 | .parent = &sys_ck, | |
1849 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
1850 | .recalc = &followparent_recalc, | |
1851 | }; | |
1852 | ||
1853 | /* 3430ES2 only */ | |
1854 | /* Never specifically named in the TRM, so we have to infer a likely name */ | |
1855 | static struct clk usim_ick = { | |
1856 | .name = "usim_ick", | |
1857 | .parent = &wkup_l4_ick, | |
1858 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1859 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | |
1860 | .flags = CLOCK_IN_OMAP3430ES2, | |
1861 | .recalc = &followparent_recalc, | |
1862 | }; | |
1863 | ||
1864 | static struct clk wdt2_ick = { | |
1865 | .name = "wdt2_ick", | |
1866 | .parent = &wkup_l4_ick, | |
1867 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1868 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | |
1869 | .flags = CLOCK_IN_OMAP343X, | |
1870 | .recalc = &followparent_recalc, | |
1871 | }; | |
1872 | ||
1873 | static struct clk wdt1_ick = { | |
1874 | .name = "wdt1_ick", | |
1875 | .parent = &wkup_l4_ick, | |
1876 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1877 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | |
1878 | .flags = CLOCK_IN_OMAP343X, | |
1879 | .recalc = &followparent_recalc, | |
1880 | }; | |
1881 | ||
1882 | static struct clk gpio1_ick = { | |
1883 | .name = "gpio1_ick", | |
1884 | .parent = &wkup_l4_ick, | |
1885 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1886 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | |
1887 | .flags = CLOCK_IN_OMAP343X, | |
1888 | .recalc = &followparent_recalc, | |
1889 | }; | |
1890 | ||
1891 | static struct clk omap_32ksync_ick = { | |
1892 | .name = "omap_32ksync_ick", | |
1893 | .parent = &wkup_l4_ick, | |
1894 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1895 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | |
1896 | .flags = CLOCK_IN_OMAP343X, | |
1897 | .recalc = &followparent_recalc, | |
1898 | }; | |
1899 | ||
1900 | static struct clk gpt12_ick = { | |
1901 | .name = "gpt12_ick", | |
1902 | .parent = &wkup_l4_ick, | |
1903 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1904 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | |
1905 | .flags = CLOCK_IN_OMAP343X, | |
1906 | .recalc = &followparent_recalc, | |
1907 | }; | |
1908 | ||
1909 | static struct clk gpt1_ick = { | |
1910 | .name = "gpt1_ick", | |
1911 | .parent = &wkup_l4_ick, | |
1912 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
1913 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | |
1914 | .flags = CLOCK_IN_OMAP343X, | |
1915 | .recalc = &followparent_recalc, | |
1916 | }; | |
1917 | ||
1918 | ||
1919 | ||
1920 | /* PER clock domain */ | |
1921 | ||
1922 | static struct clk per_96m_fck = { | |
1923 | .name = "per_96m_fck", | |
1924 | .parent = &omap_96m_alwon_fck, | |
1925 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1926 | PARENT_CONTROLS_CLOCK, | |
1927 | .recalc = &followparent_recalc, | |
1928 | }; | |
1929 | ||
1930 | static struct clk per_48m_fck = { | |
1931 | .name = "per_48m_fck", | |
1932 | .parent = &omap_48m_fck, | |
1933 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1934 | PARENT_CONTROLS_CLOCK, | |
1935 | .recalc = &followparent_recalc, | |
1936 | }; | |
1937 | ||
1938 | static struct clk uart3_fck = { | |
1939 | .name = "uart3_fck", | |
1940 | .parent = &per_48m_fck, | |
1941 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
1942 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | |
1943 | .flags = CLOCK_IN_OMAP343X, | |
1944 | .recalc = &followparent_recalc, | |
1945 | }; | |
1946 | ||
1947 | static struct clk gpt2_fck = { | |
1948 | .name = "gpt2_fck", | |
1949 | .init = &omap2_init_clksel_parent, | |
1950 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
1951 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | |
1952 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
1953 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, | |
1954 | .clksel = omap343x_gpt_clksel, | |
1955 | .flags = CLOCK_IN_OMAP343X, | |
1956 | .recalc = &omap2_clksel_recalc, | |
1957 | }; | |
1958 | ||
1959 | static struct clk gpt3_fck = { | |
1960 | .name = "gpt3_fck", | |
1961 | .init = &omap2_init_clksel_parent, | |
1962 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
1963 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | |
1964 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
1965 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, | |
1966 | .clksel = omap343x_gpt_clksel, | |
1967 | .flags = CLOCK_IN_OMAP343X, | |
1968 | .recalc = &omap2_clksel_recalc, | |
1969 | }; | |
1970 | ||
1971 | static struct clk gpt4_fck = { | |
1972 | .name = "gpt4_fck", | |
1973 | .init = &omap2_init_clksel_parent, | |
1974 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
1975 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | |
1976 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
1977 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, | |
1978 | .clksel = omap343x_gpt_clksel, | |
1979 | .flags = CLOCK_IN_OMAP343X, | |
1980 | .recalc = &omap2_clksel_recalc, | |
1981 | }; | |
1982 | ||
1983 | static struct clk gpt5_fck = { | |
1984 | .name = "gpt5_fck", | |
1985 | .init = &omap2_init_clksel_parent, | |
1986 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
1987 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | |
1988 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
1989 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, | |
1990 | .clksel = omap343x_gpt_clksel, | |
1991 | .flags = CLOCK_IN_OMAP343X, | |
1992 | .recalc = &omap2_clksel_recalc, | |
1993 | }; | |
1994 | ||
1995 | static struct clk gpt6_fck = { | |
1996 | .name = "gpt6_fck", | |
1997 | .init = &omap2_init_clksel_parent, | |
1998 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
1999 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | |
2000 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2001 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, | |
2002 | .clksel = omap343x_gpt_clksel, | |
2003 | .flags = CLOCK_IN_OMAP343X, | |
2004 | .recalc = &omap2_clksel_recalc, | |
2005 | }; | |
2006 | ||
2007 | static struct clk gpt7_fck = { | |
2008 | .name = "gpt7_fck", | |
2009 | .init = &omap2_init_clksel_parent, | |
2010 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2011 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | |
2012 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2013 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, | |
2014 | .clksel = omap343x_gpt_clksel, | |
2015 | .flags = CLOCK_IN_OMAP343X, | |
2016 | .recalc = &omap2_clksel_recalc, | |
2017 | }; | |
2018 | ||
2019 | static struct clk gpt8_fck = { | |
2020 | .name = "gpt8_fck", | |
2021 | .init = &omap2_init_clksel_parent, | |
2022 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2023 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | |
2024 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2025 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, | |
2026 | .clksel = omap343x_gpt_clksel, | |
2027 | .flags = CLOCK_IN_OMAP343X, | |
2028 | .recalc = &omap2_clksel_recalc, | |
2029 | }; | |
2030 | ||
2031 | static struct clk gpt9_fck = { | |
2032 | .name = "gpt9_fck", | |
2033 | .init = &omap2_init_clksel_parent, | |
2034 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2035 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | |
2036 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2037 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, | |
2038 | .clksel = omap343x_gpt_clksel, | |
2039 | .flags = CLOCK_IN_OMAP343X, | |
2040 | .recalc = &omap2_clksel_recalc, | |
2041 | }; | |
2042 | ||
2043 | static struct clk per_32k_alwon_fck = { | |
2044 | .name = "per_32k_alwon_fck", | |
2045 | .parent = &omap_32k_fck, | |
2046 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2047 | .recalc = &followparent_recalc, | |
2048 | }; | |
2049 | ||
2050 | static struct clk gpio6_fck = { | |
2051 | .name = "gpio6_fck", | |
2052 | .parent = &per_32k_alwon_fck, | |
2053 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2054 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | |
2055 | .flags = CLOCK_IN_OMAP343X, | |
2056 | .recalc = &followparent_recalc, | |
2057 | }; | |
2058 | ||
2059 | static struct clk gpio5_fck = { | |
2060 | .name = "gpio5_fck", | |
2061 | .parent = &per_32k_alwon_fck, | |
2062 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2063 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | |
2064 | .flags = CLOCK_IN_OMAP343X, | |
2065 | .recalc = &followparent_recalc, | |
2066 | }; | |
2067 | ||
2068 | static struct clk gpio4_fck = { | |
2069 | .name = "gpio4_fck", | |
2070 | .parent = &per_32k_alwon_fck, | |
2071 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2072 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | |
2073 | .flags = CLOCK_IN_OMAP343X, | |
2074 | .recalc = &followparent_recalc, | |
2075 | }; | |
2076 | ||
2077 | static struct clk gpio3_fck = { | |
2078 | .name = "gpio3_fck", | |
2079 | .parent = &per_32k_alwon_fck, | |
2080 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2081 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | |
2082 | .flags = CLOCK_IN_OMAP343X, | |
2083 | .recalc = &followparent_recalc, | |
2084 | }; | |
2085 | ||
2086 | static struct clk gpio2_fck = { | |
2087 | .name = "gpio2_fck", | |
2088 | .parent = &per_32k_alwon_fck, | |
2089 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2090 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | |
2091 | .flags = CLOCK_IN_OMAP343X, | |
2092 | .recalc = &followparent_recalc, | |
2093 | }; | |
2094 | ||
2095 | static struct clk wdt3_fck = { | |
2096 | .name = "wdt3_fck", | |
2097 | .parent = &per_32k_alwon_fck, | |
2098 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2099 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | |
2100 | .flags = CLOCK_IN_OMAP343X, | |
2101 | .recalc = &followparent_recalc, | |
2102 | }; | |
2103 | ||
2104 | static struct clk per_l4_ick = { | |
2105 | .name = "per_l4_ick", | |
2106 | .parent = &l4_ick, | |
2107 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
2108 | PARENT_CONTROLS_CLOCK, | |
2109 | .recalc = &followparent_recalc, | |
2110 | }; | |
2111 | ||
2112 | static struct clk gpio6_ick = { | |
2113 | .name = "gpio6_ick", | |
2114 | .parent = &per_l4_ick, | |
2115 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2116 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | |
2117 | .flags = CLOCK_IN_OMAP343X, | |
2118 | .recalc = &followparent_recalc, | |
2119 | }; | |
2120 | ||
2121 | static struct clk gpio5_ick = { | |
2122 | .name = "gpio5_ick", | |
2123 | .parent = &per_l4_ick, | |
2124 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2125 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | |
2126 | .flags = CLOCK_IN_OMAP343X, | |
2127 | .recalc = &followparent_recalc, | |
2128 | }; | |
2129 | ||
2130 | static struct clk gpio4_ick = { | |
2131 | .name = "gpio4_ick", | |
2132 | .parent = &per_l4_ick, | |
2133 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2134 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | |
2135 | .flags = CLOCK_IN_OMAP343X, | |
2136 | .recalc = &followparent_recalc, | |
2137 | }; | |
2138 | ||
2139 | static struct clk gpio3_ick = { | |
2140 | .name = "gpio3_ick", | |
2141 | .parent = &per_l4_ick, | |
2142 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2143 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | |
2144 | .flags = CLOCK_IN_OMAP343X, | |
2145 | .recalc = &followparent_recalc, | |
2146 | }; | |
2147 | ||
2148 | static struct clk gpio2_ick = { | |
2149 | .name = "gpio2_ick", | |
2150 | .parent = &per_l4_ick, | |
2151 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2152 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | |
2153 | .flags = CLOCK_IN_OMAP343X, | |
2154 | .recalc = &followparent_recalc, | |
2155 | }; | |
2156 | ||
2157 | static struct clk wdt3_ick = { | |
2158 | .name = "wdt3_ick", | |
2159 | .parent = &per_l4_ick, | |
2160 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2161 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | |
2162 | .flags = CLOCK_IN_OMAP343X, | |
2163 | .recalc = &followparent_recalc, | |
2164 | }; | |
2165 | ||
2166 | static struct clk uart3_ick = { | |
2167 | .name = "uart3_ick", | |
2168 | .parent = &per_l4_ick, | |
2169 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2170 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | |
2171 | .flags = CLOCK_IN_OMAP343X, | |
2172 | .recalc = &followparent_recalc, | |
2173 | }; | |
2174 | ||
2175 | static struct clk gpt9_ick = { | |
2176 | .name = "gpt9_ick", | |
2177 | .parent = &per_l4_ick, | |
2178 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2179 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | |
2180 | .flags = CLOCK_IN_OMAP343X, | |
2181 | .recalc = &followparent_recalc, | |
2182 | }; | |
2183 | ||
2184 | static struct clk gpt8_ick = { | |
2185 | .name = "gpt8_ick", | |
2186 | .parent = &per_l4_ick, | |
2187 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2188 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | |
2189 | .flags = CLOCK_IN_OMAP343X, | |
2190 | .recalc = &followparent_recalc, | |
2191 | }; | |
2192 | ||
2193 | static struct clk gpt7_ick = { | |
2194 | .name = "gpt7_ick", | |
2195 | .parent = &per_l4_ick, | |
2196 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2197 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | |
2198 | .flags = CLOCK_IN_OMAP343X, | |
2199 | .recalc = &followparent_recalc, | |
2200 | }; | |
2201 | ||
2202 | static struct clk gpt6_ick = { | |
2203 | .name = "gpt6_ick", | |
2204 | .parent = &per_l4_ick, | |
2205 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2206 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | |
2207 | .flags = CLOCK_IN_OMAP343X, | |
2208 | .recalc = &followparent_recalc, | |
2209 | }; | |
2210 | ||
2211 | static struct clk gpt5_ick = { | |
2212 | .name = "gpt5_ick", | |
2213 | .parent = &per_l4_ick, | |
2214 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2215 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | |
2216 | .flags = CLOCK_IN_OMAP343X, | |
2217 | .recalc = &followparent_recalc, | |
2218 | }; | |
2219 | ||
2220 | static struct clk gpt4_ick = { | |
2221 | .name = "gpt4_ick", | |
2222 | .parent = &per_l4_ick, | |
2223 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2224 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | |
2225 | .flags = CLOCK_IN_OMAP343X, | |
2226 | .recalc = &followparent_recalc, | |
2227 | }; | |
2228 | ||
2229 | static struct clk gpt3_ick = { | |
2230 | .name = "gpt3_ick", | |
2231 | .parent = &per_l4_ick, | |
2232 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2233 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | |
2234 | .flags = CLOCK_IN_OMAP343X, | |
2235 | .recalc = &followparent_recalc, | |
2236 | }; | |
2237 | ||
2238 | static struct clk gpt2_ick = { | |
2239 | .name = "gpt2_ick", | |
2240 | .parent = &per_l4_ick, | |
2241 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2242 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | |
2243 | .flags = CLOCK_IN_OMAP343X, | |
2244 | .recalc = &followparent_recalc, | |
2245 | }; | |
2246 | ||
2247 | static struct clk mcbsp2_ick = { | |
2248 | .name = "mcbsp2_ick", | |
2249 | .parent = &per_l4_ick, | |
2250 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2251 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
2252 | .flags = CLOCK_IN_OMAP343X, | |
2253 | .recalc = &followparent_recalc, | |
2254 | }; | |
2255 | ||
2256 | static struct clk mcbsp3_ick = { | |
2257 | .name = "mcbsp3_ick", | |
2258 | .parent = &per_l4_ick, | |
2259 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2260 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
2261 | .flags = CLOCK_IN_OMAP343X, | |
2262 | .recalc = &followparent_recalc, | |
2263 | }; | |
2264 | ||
2265 | static struct clk mcbsp4_ick = { | |
2266 | .name = "mcbsp4_ick", | |
2267 | .parent = &per_l4_ick, | |
2268 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2269 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | |
2270 | .flags = CLOCK_IN_OMAP343X, | |
2271 | .recalc = &followparent_recalc, | |
2272 | }; | |
2273 | ||
2274 | static const struct clksel mcbsp_234_clksel[] = { | |
2275 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, | |
2276 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | |
2277 | { .parent = NULL } | |
2278 | }; | |
2279 | ||
2280 | static struct clk mcbsp2_fck = { | |
2281 | .name = "mcbsp2_fck", | |
2282 | .init = &omap2_init_clksel_parent, | |
2283 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2284 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
2285 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
2286 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | |
2287 | .clksel = mcbsp_234_clksel, | |
2288 | .flags = CLOCK_IN_OMAP343X, | |
2289 | .recalc = &omap2_clksel_recalc, | |
2290 | }; | |
2291 | ||
2292 | static struct clk mcbsp3_fck = { | |
2293 | .name = "mcbsp3_fck", | |
2294 | .init = &omap2_init_clksel_parent, | |
2295 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2296 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
2297 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
2298 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | |
2299 | .clksel = mcbsp_234_clksel, | |
2300 | .flags = CLOCK_IN_OMAP343X, | |
2301 | .recalc = &omap2_clksel_recalc, | |
2302 | }; | |
2303 | ||
2304 | static struct clk mcbsp4_fck = { | |
2305 | .name = "mcbsp4_fck", | |
2306 | .init = &omap2_init_clksel_parent, | |
2307 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2308 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | |
2309 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
2310 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | |
2311 | .clksel = mcbsp_234_clksel, | |
2312 | .flags = CLOCK_IN_OMAP343X, | |
2313 | .recalc = &omap2_clksel_recalc, | |
2314 | }; | |
2315 | ||
2316 | /* EMU clocks */ | |
2317 | ||
2318 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ | |
2319 | ||
2320 | static const struct clksel_rate emu_src_sys_rates[] = { | |
2321 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2322 | { .div = 0 }, | |
2323 | }; | |
2324 | ||
2325 | static const struct clksel_rate emu_src_core_rates[] = { | |
2326 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2327 | { .div = 0 }, | |
2328 | }; | |
2329 | ||
2330 | static const struct clksel_rate emu_src_per_rates[] = { | |
2331 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2332 | { .div = 0 }, | |
2333 | }; | |
2334 | ||
2335 | static const struct clksel_rate emu_src_mpu_rates[] = { | |
2336 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2337 | { .div = 0 }, | |
2338 | }; | |
2339 | ||
2340 | static const struct clksel emu_src_clksel[] = { | |
2341 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, | |
2342 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, | |
2343 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, | |
2344 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, | |
2345 | { .parent = NULL }, | |
2346 | }; | |
2347 | ||
2348 | /* | |
2349 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only | |
2350 | * to switch the source of some of the EMU clocks. | |
2351 | * XXX Are there CLKEN bits for these EMU clks? | |
2352 | */ | |
2353 | static struct clk emu_src_ck = { | |
2354 | .name = "emu_src_ck", | |
2355 | .init = &omap2_init_clksel_parent, | |
2356 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2357 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | |
2358 | .clksel = emu_src_clksel, | |
2359 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2360 | .recalc = &omap2_clksel_recalc, | |
2361 | }; | |
2362 | ||
2363 | static const struct clksel_rate pclk_emu_rates[] = { | |
2364 | { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2365 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
2366 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2367 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
2368 | { .div = 0 }, | |
2369 | }; | |
2370 | ||
2371 | static const struct clksel pclk_emu_clksel[] = { | |
2372 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, | |
2373 | { .parent = NULL }, | |
2374 | }; | |
2375 | ||
2376 | static struct clk pclk_fck = { | |
2377 | .name = "pclk_fck", | |
2378 | .init = &omap2_init_clksel_parent, | |
2379 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2380 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | |
2381 | .clksel = pclk_emu_clksel, | |
2382 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2383 | .recalc = &omap2_clksel_recalc, | |
2384 | }; | |
2385 | ||
2386 | static const struct clksel_rate pclkx2_emu_rates[] = { | |
2387 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2388 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
2389 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
2390 | { .div = 0 }, | |
2391 | }; | |
2392 | ||
2393 | static const struct clksel pclkx2_emu_clksel[] = { | |
2394 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, | |
2395 | { .parent = NULL }, | |
2396 | }; | |
2397 | ||
2398 | static struct clk pclkx2_fck = { | |
2399 | .name = "pclkx2_fck", | |
2400 | .init = &omap2_init_clksel_parent, | |
2401 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2402 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | |
2403 | .clksel = pclkx2_emu_clksel, | |
2404 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2405 | .recalc = &omap2_clksel_recalc, | |
2406 | }; | |
2407 | ||
2408 | static const struct clksel atclk_emu_clksel[] = { | |
2409 | { .parent = &emu_src_ck, .rates = div2_rates }, | |
2410 | { .parent = NULL }, | |
2411 | }; | |
2412 | ||
2413 | static struct clk atclk_fck = { | |
2414 | .name = "atclk_fck", | |
2415 | .init = &omap2_init_clksel_parent, | |
2416 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2417 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | |
2418 | .clksel = atclk_emu_clksel, | |
2419 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2420 | .recalc = &omap2_clksel_recalc, | |
2421 | }; | |
2422 | ||
2423 | static struct clk traceclk_src_fck = { | |
2424 | .name = "traceclk_src_fck", | |
2425 | .init = &omap2_init_clksel_parent, | |
2426 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2427 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | |
2428 | .clksel = emu_src_clksel, | |
2429 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2430 | .recalc = &omap2_clksel_recalc, | |
2431 | }; | |
2432 | ||
2433 | static const struct clksel_rate traceclk_rates[] = { | |
2434 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2435 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
2436 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2437 | { .div = 0 }, | |
2438 | }; | |
2439 | ||
2440 | static const struct clksel traceclk_clksel[] = { | |
2441 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, | |
2442 | { .parent = NULL }, | |
2443 | }; | |
2444 | ||
2445 | static struct clk traceclk_fck = { | |
2446 | .name = "traceclk_fck", | |
2447 | .init = &omap2_init_clksel_parent, | |
2448 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2449 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | |
2450 | .clksel = traceclk_clksel, | |
2451 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | |
2452 | .recalc = &omap2_clksel_recalc, | |
2453 | }; | |
2454 | ||
2455 | /* SR clocks */ | |
2456 | ||
2457 | /* SmartReflex fclk (VDD1) */ | |
2458 | static struct clk sr1_fck = { | |
2459 | .name = "sr1_fck", | |
2460 | .parent = &sys_ck, | |
2461 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2462 | .enable_bit = OMAP3430_EN_SR1_SHIFT, | |
2463 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
2464 | .recalc = &followparent_recalc, | |
2465 | }; | |
2466 | ||
2467 | /* SmartReflex fclk (VDD2) */ | |
2468 | static struct clk sr2_fck = { | |
2469 | .name = "sr2_fck", | |
2470 | .parent = &sys_ck, | |
2471 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2472 | .enable_bit = OMAP3430_EN_SR2_SHIFT, | |
2473 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
2474 | .recalc = &followparent_recalc, | |
2475 | }; | |
2476 | ||
2477 | static struct clk sr_l4_ick = { | |
2478 | .name = "sr_l4_ick", | |
2479 | .parent = &l4_ick, | |
2480 | .flags = CLOCK_IN_OMAP343X, | |
2481 | .recalc = &followparent_recalc, | |
2482 | }; | |
2483 | ||
2484 | /* SECURE_32K_FCK clocks */ | |
2485 | ||
2486 | static struct clk gpt12_fck = { | |
2487 | .name = "gpt12_fck", | |
2488 | .parent = &secure_32k_fck, | |
2489 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | |
2490 | .recalc = &followparent_recalc, | |
2491 | }; | |
2492 | ||
2493 | static struct clk wdt1_fck = { | |
2494 | .name = "wdt1_fck", | |
2495 | .parent = &secure_32k_fck, | |
2496 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | |
2497 | .recalc = &followparent_recalc, | |
2498 | }; | |
2499 | ||
2500 | ||
2501 | static struct clk *onchip_34xx_clks[] __initdata = { | |
2502 | &omap_32k_fck, | |
2503 | &virt_12m_ck, | |
2504 | &virt_13m_ck, | |
2505 | &virt_16_8m_ck, | |
2506 | &virt_19_2m_ck, | |
2507 | &virt_26m_ck, | |
2508 | &virt_38_4m_ck, | |
2509 | &osc_sys_ck, | |
2510 | &sys_ck, | |
2511 | &sys_altclk, | |
2512 | &mcbsp_clks, | |
2513 | &sys_clkout1, | |
2514 | &dpll1_ck, | |
2515 | &emu_mpu_alwon_ck, | |
2516 | &dpll2_ck, | |
2517 | &dpll3_ck, | |
2518 | &core_ck, | |
2519 | &dpll3_x2_ck, | |
2520 | &dpll3_m2_ck, | |
2521 | &dpll3_m2x2_ck, | |
2522 | &dpll3_m3x2_ck, | |
2523 | &emu_core_alwon_ck, | |
2524 | &dpll4_ck, | |
2525 | &dpll4_x2_ck, | |
2526 | &omap_96m_alwon_fck, | |
2527 | &omap_96m_fck, | |
2528 | &cm_96m_fck, | |
2529 | &omap_54m_fck, | |
2530 | &omap_48m_fck, | |
2531 | &omap_12m_fck, | |
2532 | &dpll4_m2x2_ck, | |
2533 | &dpll4_m3x2_ck, | |
2534 | &dpll4_m4x2_ck, | |
2535 | &dpll4_m5x2_ck, | |
2536 | &dpll4_m6x2_ck, | |
2537 | &emu_per_alwon_ck, | |
2538 | &dpll5_ck, | |
2539 | &dpll5_m2_ck, | |
2540 | &omap_120m_fck, | |
2541 | &clkout2_src_ck, | |
2542 | &sys_clkout2, | |
2543 | &corex2_fck, | |
2544 | &dpll1_fck, | |
2545 | &dpll2_fck, | |
2546 | &l3_ick, | |
2547 | &l4_ick, | |
2548 | &rm_ick, | |
2549 | &gfx_l3_fck, | |
2550 | &gfx_l3_ick, | |
2551 | &gfx_cg1_ck, | |
2552 | &gfx_cg2_ck, | |
2553 | &sgx_fck, | |
2554 | &sgx_ick, | |
2555 | &d2d_26m_fck, | |
2556 | &gpt10_fck, | |
2557 | &gpt11_fck, | |
2558 | &cpefuse_fck, | |
2559 | &ts_fck, | |
2560 | &usbtll_fck, | |
2561 | &core_96m_fck, | |
2562 | &mmchs3_fck, | |
2563 | &mmchs2_fck, | |
2564 | &mspro_fck, | |
2565 | &mmchs1_fck, | |
2566 | &i2c3_fck, | |
2567 | &i2c2_fck, | |
2568 | &i2c1_fck, | |
2569 | &mcbsp5_fck, | |
2570 | &mcbsp1_fck, | |
2571 | &core_48m_fck, | |
2572 | &mcspi4_fck, | |
2573 | &mcspi3_fck, | |
2574 | &mcspi2_fck, | |
2575 | &mcspi1_fck, | |
2576 | &uart2_fck, | |
2577 | &uart1_fck, | |
2578 | &fshostusb_fck, | |
2579 | &core_12m_fck, | |
2580 | &hdq_fck, | |
2581 | &ssi_ssr_fck, | |
2582 | &ssi_sst_fck, | |
2583 | &core_l3_ick, | |
2584 | &hsotgusb_ick, | |
2585 | &sdrc_ick, | |
2586 | &gpmc_fck, | |
2587 | &security_l3_ick, | |
2588 | &pka_ick, | |
2589 | &core_l4_ick, | |
2590 | &usbtll_ick, | |
2591 | &mmchs3_ick, | |
2592 | &icr_ick, | |
2593 | &aes2_ick, | |
2594 | &sha12_ick, | |
2595 | &des2_ick, | |
2596 | &mmchs2_ick, | |
2597 | &mmchs1_ick, | |
2598 | &mspro_ick, | |
2599 | &hdq_ick, | |
2600 | &mcspi4_ick, | |
2601 | &mcspi3_ick, | |
2602 | &mcspi2_ick, | |
2603 | &mcspi1_ick, | |
2604 | &i2c3_ick, | |
2605 | &i2c2_ick, | |
2606 | &i2c1_ick, | |
2607 | &uart2_ick, | |
2608 | &uart1_ick, | |
2609 | &gpt11_ick, | |
2610 | &gpt10_ick, | |
2611 | &mcbsp5_ick, | |
2612 | &mcbsp1_ick, | |
2613 | &fac_ick, | |
2614 | &mailboxes_ick, | |
2615 | &omapctrl_ick, | |
2616 | &ssi_l4_ick, | |
2617 | &ssi_ick, | |
2618 | &usb_l4_ick, | |
2619 | &security_l4_ick2, | |
2620 | &aes1_ick, | |
2621 | &rng_ick, | |
2622 | &sha11_ick, | |
2623 | &des1_ick, | |
2624 | &dss1_alwon_fck, | |
2625 | &dss_tv_fck, | |
2626 | &dss_96m_fck, | |
2627 | &dss2_alwon_fck, | |
2628 | &dss_ick, | |
2629 | &cam_mclk, | |
2630 | &cam_l3_ick, | |
2631 | &cam_l4_ick, | |
2632 | &usbhost_120m_fck, | |
2633 | &usbhost_48m_fck, | |
2634 | &usbhost_l3_ick, | |
2635 | &usbhost_l4_ick, | |
2636 | &usbhost_sar_fck, | |
2637 | &usim_fck, | |
2638 | &gpt1_fck, | |
2639 | &wkup_32k_fck, | |
2640 | &gpio1_fck, | |
2641 | &wdt2_fck, | |
2642 | &wkup_l4_ick, | |
2643 | &usim_ick, | |
2644 | &wdt2_ick, | |
2645 | &wdt1_ick, | |
2646 | &gpio1_ick, | |
2647 | &omap_32ksync_ick, | |
2648 | &gpt12_ick, | |
2649 | &gpt1_ick, | |
2650 | &per_96m_fck, | |
2651 | &per_48m_fck, | |
2652 | &uart3_fck, | |
2653 | &gpt2_fck, | |
2654 | &gpt3_fck, | |
2655 | &gpt4_fck, | |
2656 | &gpt5_fck, | |
2657 | &gpt6_fck, | |
2658 | &gpt7_fck, | |
2659 | &gpt8_fck, | |
2660 | &gpt9_fck, | |
2661 | &per_32k_alwon_fck, | |
2662 | &gpio6_fck, | |
2663 | &gpio5_fck, | |
2664 | &gpio4_fck, | |
2665 | &gpio3_fck, | |
2666 | &gpio2_fck, | |
2667 | &wdt3_fck, | |
2668 | &per_l4_ick, | |
2669 | &gpio6_ick, | |
2670 | &gpio5_ick, | |
2671 | &gpio4_ick, | |
2672 | &gpio3_ick, | |
2673 | &gpio2_ick, | |
2674 | &wdt3_ick, | |
2675 | &uart3_ick, | |
2676 | &gpt9_ick, | |
2677 | &gpt8_ick, | |
2678 | &gpt7_ick, | |
2679 | &gpt6_ick, | |
2680 | &gpt5_ick, | |
2681 | &gpt4_ick, | |
2682 | &gpt3_ick, | |
2683 | &gpt2_ick, | |
2684 | &mcbsp2_ick, | |
2685 | &mcbsp3_ick, | |
2686 | &mcbsp4_ick, | |
2687 | &mcbsp2_fck, | |
2688 | &mcbsp3_fck, | |
2689 | &mcbsp4_fck, | |
2690 | &emu_src_ck, | |
2691 | &pclk_fck, | |
2692 | &pclkx2_fck, | |
2693 | &atclk_fck, | |
2694 | &traceclk_src_fck, | |
2695 | &traceclk_fck, | |
2696 | &sr1_fck, | |
2697 | &sr2_fck, | |
2698 | &sr_l4_ick, | |
2699 | &secure_32k_fck, | |
2700 | &gpt12_fck, | |
2701 | &wdt1_fck, | |
2702 | }; | |
2703 | ||
2704 | #endif |