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ARM: OMAP2: Clock: Add OMAP3 DPLL autoidle functions
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / clock24xx.h
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046d6b28 1/*
a16e9703 2 * linux/arch/arm/mach-omap2/clock24xx.h
046d6b28 3 *
a16e9703
TL		 4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
046d6b28 6 *
a16e9703
TL		 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
046d6b28
TL		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
6b8858a9
PW		 16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
046d6b28 18
6b8858a9
PW		 19#include "clock.h"
20
21#include "prm.h"
22#include "cm.h"
23#include "prm-regbits-24xx.h"
24#include "cm-regbits-24xx.h"
25#include "sdrc.h"
26
a16e9703
TL		 27static void omap2_table_mpu_recalc(struct clk *clk);
28static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30static void omap2_sys_clk_recalc(struct clk *clk);
31static void omap2_osc_clk_recalc(struct clk *clk);
32static void omap2_sys_clk_recalc(struct clk *clk);
33static void omap2_dpll_recalc(struct clk *clk);
34static int omap2_clk_fixed_enable(struct clk *clk);
35static void omap2_clk_fixed_disable(struct clk *clk);
36static int omap2_enable_osc_ck(struct clk *clk);
37static void omap2_disable_osc_ck(struct clk *clk);
38static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
046d6b28 39
046d6b28
TL		 40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
41 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
42 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
43 */
44struct prcm_config {
45 unsigned long xtal_speed; /* crystal rate */
46 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
47 unsigned long mpu_speed; /* speed of MPU */
48 unsigned long cm_clksel_mpu; /* mpu divider */
49 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
50 unsigned long cm_clksel_gfx; /* gfx dividers */
51 unsigned long cm_clksel1_core; /* major subsystem dividers */
52 unsigned long cm_clksel1_pll; /* m,n */
53 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
54 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
55 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
56 unsigned char flags;
57};
58
046d6b28
TL		 59/*
60 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
61 * These configurations are characterized by voltage and speed for clocks.
62 * The device is only validated for certain combinations. One way to express
63 * these combinations is via the 'ratio's' which the clocks operate with
64 * respect to each other. These ratio sets are for a given voltage/DPLL
65 * setting. All configurations can be described by a DPLL setting and a ratio
66 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
67 *
68 * 2430 differs from 2420 in that there are no more phase synchronizers used.
69 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
70 * 2430 (iva2.1, NOdsp, mdm)
71 */
72
73/* Core fields for cm_clksel, not ratio governed */
74#define RX_CLKSEL_DSS1 (0x10 << 8)
75#define RX_CLKSEL_DSS2 (0x0 << 13)
76#define RX_CLKSEL_SSI (0x5 << 20)
77
78/*-------------------------------------------------------------------------
79 * Voltage/DPLL ratios
80 *-------------------------------------------------------------------------*/
81
82/* 2430 Ratio's, 2430-Ratio Config 1 */
83#define R1_CLKSEL_L3 (4 << 0)
84#define R1_CLKSEL_L4 (2 << 5)
85#define R1_CLKSEL_USB (4 << 25)
86#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
87 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
88 R1_CLKSEL_L4 | R1_CLKSEL_L3
89#define R1_CLKSEL_MPU (2 << 0)
90#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
91#define R1_CLKSEL_DSP (2 << 0)
92#define R1_CLKSEL_DSP_IF (2 << 5)
93#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
94#define R1_CLKSEL_GFX (2 << 0)
95#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
96#define R1_CLKSEL_MDM (4 << 0)
97#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
98
99/* 2430-Ratio Config 2 */
100#define R2_CLKSEL_L3 (6 << 0)
101#define R2_CLKSEL_L4 (2 << 5)
102#define R2_CLKSEL_USB (2 << 25)
103#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
104 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
105 R2_CLKSEL_L4 | R2_CLKSEL_L3
106#define R2_CLKSEL_MPU (2 << 0)
107#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
108#define R2_CLKSEL_DSP (2 << 0)
109#define R2_CLKSEL_DSP_IF (3 << 5)
110#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
111#define R2_CLKSEL_GFX (2 << 0)
112#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
113#define R2_CLKSEL_MDM (6 << 0)
114#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
115
116/* 2430-Ratio Bootm (BYPASS) */
117#define RB_CLKSEL_L3 (1 << 0)
118#define RB_CLKSEL_L4 (1 << 5)
119#define RB_CLKSEL_USB (1 << 25)
120#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
121 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
122 RB_CLKSEL_L4 | RB_CLKSEL_L3
123#define RB_CLKSEL_MPU (1 << 0)
124#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
125#define RB_CLKSEL_DSP (1 << 0)
126#define RB_CLKSEL_DSP_IF (1 << 5)
127#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
128#define RB_CLKSEL_GFX (1 << 0)
129#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
130#define RB_CLKSEL_MDM (1 << 0)
131#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
132
133/* 2420 Ratio Equivalents */
134#define RXX_CLKSEL_VLYNQ (0x12 << 15)
135#define RXX_CLKSEL_SSI (0x8 << 20)
136
137/* 2420-PRCM III 532MHz core */
138#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
139#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
140#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
141#define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
142 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
143 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
144 RIII_CLKSEL_L3
145#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
146#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
147#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
148#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
149#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
150#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
151#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
152#define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
153 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
154 RIII_CLKSEL_DSP
155#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
156#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
157
158/* 2420-PRCM II 600MHz core */
159#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
160#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
161#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
162#define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
163 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
164 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
165 RII_CLKSEL_L4 | RII_CLKSEL_L3
166#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
167#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
168#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
169#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
170#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
6b8858a9 171#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
046d6b28
TL		 172#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
173#define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
174 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
175 RII_CLKSEL_DSP
176#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
177#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
178
6b8858a9
PW		 179/* 2420-PRCM I 660MHz core */
180#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
181#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
182#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
183#define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
184 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
185 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
186 RI_CLKSEL_L4 | RI_CLKSEL_L3
187#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
188#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
189#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
190#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
191#define RI_SYNC_DSP (1 << 7) /* Activate sync */
192#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
193#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
194#define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
195 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
196 RI_CLKSEL_DSP
197#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
198#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
199
046d6b28
TL		 200/* 2420-PRCM VII (boot) */
201#define RVII_CLKSEL_L3 (1 << 0)
202#define RVII_CLKSEL_L4 (1 << 5)
203#define RVII_CLKSEL_DSS1 (1 << 8)
204#define RVII_CLKSEL_DSS2 (0 << 13)
205#define RVII_CLKSEL_VLYNQ (1 << 15)
206#define RVII_CLKSEL_SSI (1 << 20)
207#define RVII_CLKSEL_USB (1 << 25)
208
209#define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
210 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
211 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
212
213#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
214#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
215
216#define RVII_CLKSEL_DSP (1 << 0)
217#define RVII_CLKSEL_DSP_IF (1 << 5)
218#define RVII_SYNC_DSP (0 << 7)
219#define RVII_CLKSEL_IVA (1 << 8)
220#define RVII_SYNC_IVA (0 << 13)
221#define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
222 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
223
224#define RVII_CLKSEL_GFX (1 << 0)
225#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
226
227/*-------------------------------------------------------------------------
228 * 2430 Target modes: Along with each configuration the CPU has several
229 * modes which goes along with them. Modes mainly are the addition of
230 * describe DPLL combinations to go along with a ratio.
231 *-------------------------------------------------------------------------*/
232
233/* Hardware governed */
234#define MX_48M_SRC (0 << 3)
235#define MX_54M_SRC (0 << 5)
236#define MX_APLLS_CLIKIN_12 (3 << 23)
237#define MX_APLLS_CLIKIN_13 (2 << 23)
238#define MX_APLLS_CLIKIN_19_2 (0 << 23)
239
240/*
241 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
046d6b28
TL		 242 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
243 */
244#define M5A_DPLL_MULT_12 (133 << 12)
245#define M5A_DPLL_DIV_12 (5 << 8)
246#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
247 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
248 MX_APLLS_CLIKIN_12
6b8858a9
PW		 249#define M5A_DPLL_MULT_13 (61 << 12)
250#define M5A_DPLL_DIV_13 (2 << 8)
046d6b28
TL		 251#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
252 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
253 MX_APLLS_CLIKIN_13
6b8858a9
PW		 254#define M5A_DPLL_MULT_19 (55 << 12)
255#define M5A_DPLL_DIV_19 (3 << 8)
046d6b28
TL		 256#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
257 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
258 MX_APLLS_CLIKIN_19_2
259/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
260#define M5B_DPLL_MULT_12 (50 << 12)
261#define M5B_DPLL_DIV_12 (2 << 8)
262#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
263 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
264 MX_APLLS_CLIKIN_12
265#define M5B_DPLL_MULT_13 (200 << 12)
266#define M5B_DPLL_DIV_13 (12 << 8)
267
268#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
269 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
270 MX_APLLS_CLIKIN_13
271#define M5B_DPLL_MULT_19 (125 << 12)
272#define M5B_DPLL_DIV_19 (31 << 8)
273#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
274 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
275 MX_APLLS_CLIKIN_19_2
276/*
6b8858a9
PW		 277 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
278 */
279#define M4_DPLL_MULT_12 (133 << 12)
280#define M4_DPLL_DIV_12 (3 << 8)
281#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
282 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
283 MX_APLLS_CLIKIN_12
284
285#define M4_DPLL_MULT_13 (399 << 12)
286#define M4_DPLL_DIV_13 (12 << 8)
287#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
288 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
289 MX_APLLS_CLIKIN_13
290
291#define M4_DPLL_MULT_19 (145 << 12)
292#define M4_DPLL_DIV_19 (6 << 8)
293#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
294 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
295 MX_APLLS_CLIKIN_19_2
296
297/*
046d6b28
TL		 298 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
299 */
300#define M3_DPLL_MULT_12 (55 << 12)
301#define M3_DPLL_DIV_12 (1 << 8)
302#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
303 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
304 MX_APLLS_CLIKIN_12
6b8858a9
PW		 305#define M3_DPLL_MULT_13 (76 << 12)
306#define M3_DPLL_DIV_13 (2 << 8)
046d6b28
TL		 307#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
308 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
309 MX_APLLS_CLIKIN_13
6b8858a9
PW		 310#define M3_DPLL_MULT_19 (17 << 12)
311#define M3_DPLL_DIV_19 (0 << 8)
046d6b28
TL		 312#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
313 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
314 MX_APLLS_CLIKIN_19_2
6b8858a9
PW		 315
316/*
317 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
318 */
319#define M2_DPLL_MULT_12 (55 << 12)
320#define M2_DPLL_DIV_12 (1 << 8)
321#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
322 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
323 MX_APLLS_CLIKIN_12
324
325/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
326 * relock time issue */
327/* Core frequency changed from 330/165 to 329/164 MHz*/
328#define M2_DPLL_MULT_13 (76 << 12)
329#define M2_DPLL_DIV_13 (2 << 8)
330#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
331 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
332 MX_APLLS_CLIKIN_13
333
334#define M2_DPLL_MULT_19 (17 << 12)
335#define M2_DPLL_DIV_19 (0 << 8)
336#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
337 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
338 MX_APLLS_CLIKIN_19_2
339
046d6b28
TL		 340/* boot (boot) */
341#define MB_DPLL_MULT (1 << 12)
342#define MB_DPLL_DIV (0 << 8)
343#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
344 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
345
346#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
347 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
348
349#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
350 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
351
352/*
353 * 2430 - chassis (sedna)
354 * 165 (ratio1) same as above #2
355 * 150 (ratio1)
356 * 133 (ratio2) same as above #4
357 * 110 (ratio2) same as above #3
358 * 104 (ratio2)
359 * boot (boot)
360 */
361
6b8858a9
PW		 362/* PRCM I target DPLL = 2*330MHz = 660MHz */
363#define MI_DPLL_MULT_12 (55 << 12)
364#define MI_DPLL_DIV_12 (1 << 8)
365#define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
366 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
367 MX_APLLS_CLIKIN_12
368
046d6b28
TL		 369/*
370 * 2420 Equivalent - mode registers
371 * PRCM II , target DPLL = 2*300MHz = 600MHz
372 */
373#define MII_DPLL_MULT_12 (50 << 12)
374#define MII_DPLL_DIV_12 (1 << 8)
375#define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
376 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
377 MX_APLLS_CLIKIN_12
378#define MII_DPLL_MULT_13 (300 << 12)
379#define MII_DPLL_DIV_13 (12 << 8)
380#define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
381 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
382 MX_APLLS_CLIKIN_13
383
384/* PRCM III target DPLL = 2*266 = 532MHz*/
385#define MIII_DPLL_MULT_12 (133 << 12)
386#define MIII_DPLL_DIV_12 (5 << 8)
387#define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
388 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
389 MX_APLLS_CLIKIN_12
390#define MIII_DPLL_MULT_13 (266 << 12)
391#define MIII_DPLL_DIV_13 (12 << 8)
392#define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
393 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
394 MX_APLLS_CLIKIN_13
395
396/* PRCM VII (boot bypass) */
397#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
398#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
399
400/* High and low operation value */
401#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
402#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
403
046d6b28
TL		 404/* MPU speed defines */
405#define S12M 12000000
406#define S13M 13000000
407#define S19M 19200000
408#define S26M 26000000
409#define S100M 100000000
410#define S133M 133000000
411#define S150M 150000000
6b8858a9 412#define S164M 164000000
046d6b28 413#define S165M 165000000
6b8858a9 414#define S199M 199000000
046d6b28
TL		 415#define S200M 200000000
416#define S266M 266000000
417#define S300M 300000000
6b8858a9 418#define S329M 329000000
046d6b28 419#define S330M 330000000
6b8858a9 420#define S399M 399000000
046d6b28
TL		 421#define S400M 400000000
422#define S532M 532000000
423#define S600M 600000000
6b8858a9 424#define S658M 658000000
046d6b28 425#define S660M 660000000
6b8858a9 426#define S798M 798000000
046d6b28
TL		 427
428/*-------------------------------------------------------------------------
429 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
430 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
431 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
432 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
433 *
434 * Filling in table based on H4 boards and 2430-SDPs variants available.
435 * There are quite a few more rates combinations which could be defined.
436 *
6cbdc8c5 437 * When multiple values are defined the start up will try and choose the
046d6b28
TL		 438 * fastest one. If a 'fast' value is defined, then automatically, the /2
439 * one should be included as it can be used. Generally having more that
440 * one fast set does not make sense, as static timings need to be changed
441 * to change the set. The exception is the bypass setting which is
442 * availble for low power bypass.
443 *
444 * Note: This table needs to be sorted, fastest to slowest.
445 *-------------------------------------------------------------------------*/
446static struct prcm_config rate_table[] = {
6b8858a9
PW		 447 /* PRCM I - FAST */
448 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
449 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
450 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
451 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
452 RATE_IN_242X},
453
046d6b28
TL		 454 /* PRCM II - FAST */
455 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
456 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
457 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
6b8858a9 458 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 459 RATE_IN_242X},
460
461 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
462 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
463 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
6b8858a9 464 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 465 RATE_IN_242X},
466
467 /* PRCM III - FAST */
468 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
469 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
470 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
6b8858a9 471 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 472 RATE_IN_242X},
473
474 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
475 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
476 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
6b8858a9 477 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 478 RATE_IN_242X},
479
480 /* PRCM II - SLOW */
481 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
482 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
483 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
6b8858a9 484 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 485 RATE_IN_242X},
486
487 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
488 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
489 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
6b8858a9 490 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 491 RATE_IN_242X},
492
493 /* PRCM III - SLOW */
494 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
495 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
496 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
6b8858a9 497 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 498 RATE_IN_242X},
499
500 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
501 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
502 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
6b8858a9 503 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 504 RATE_IN_242X},
505
506 /* PRCM-VII (boot-bypass) */
507 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
508 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
509 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
6b8858a9 510 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
046d6b28
TL		 511 RATE_IN_242X},
512
513 /* PRCM-VII (boot-bypass) */
514 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
515 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
516 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
6b8858a9 517 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
046d6b28
TL		 518 RATE_IN_242X},
519
6b8858a9
PW		 520 /* PRCM #4 - ratio2 (ES2.1) - FAST */
521 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
046d6b28 522 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
6b8858a9 523 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
046d6b28 524 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
6b8858a9
PW		 525 SDRC_RFR_CTRL_133MHz,
526 RATE_IN_243X},
527
528 /* PRCM #2 - ratio1 (ES2) - FAST */
529 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
530 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
531 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
532 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
533 SDRC_RFR_CTRL_165MHz,
046d6b28
TL		 534 RATE_IN_243X},
535
536 /* PRCM #5a - ratio1 - FAST */
537 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
538 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
539 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
540 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
6b8858a9 541 SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 542 RATE_IN_243X},
543
544 /* PRCM #5b - ratio1 - FAST */
545 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
546 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
547 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
548 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
6b8858a9 549 SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 550 RATE_IN_243X},
551
6b8858a9
PW		 552 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
553 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
046d6b28 554 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
6b8858a9 555 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
046d6b28 556 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
6b8858a9
PW		 557 SDRC_RFR_CTRL_133MHz,
558 RATE_IN_243X},
559
560 /* PRCM #2 - ratio1 (ES2) - SLOW */
561 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
562 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
563 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
564 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
565 SDRC_RFR_CTRL_165MHz,
046d6b28
TL		 566 RATE_IN_243X},
567
568 /* PRCM #5a - ratio1 - SLOW */
569 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
570 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
571 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
572 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
6b8858a9 573 SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 574 RATE_IN_243X},
575
576 /* PRCM #5b - ratio1 - SLOW*/
577 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
578 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
579 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
580 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
6b8858a9 581 SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 582 RATE_IN_243X},
583
584 /* PRCM-boot/bypass */
585 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
586 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
587 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
588 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
6b8858a9 589 SDRC_RFR_CTRL_BYPASS,
046d6b28
TL		 590 RATE_IN_243X},
591
592 /* PRCM-boot/bypass */
593 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
594 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
595 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
596 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
6b8858a9 597 SDRC_RFR_CTRL_BYPASS,
046d6b28
TL		 598 RATE_IN_243X},
599
600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
601};
602
603/*-------------------------------------------------------------------------
604 * 24xx clock tree.
605 *
606 * NOTE:In many cases here we are assigning a 'default' parent. In many
607 * cases the parent is selectable. The get/set parent calls will also
608 * switch sources.
609 *
610 * Many some clocks say always_enabled, but they can be auto idled for
611 * power savings. They will always be available upon clock request.
612 *
613 * Several sources are given initial rates which may be wrong, this will
614 * be fixed up in the init func.
615 *
616 * Things are broadly separated below by clock domains. It is
617 * noteworthy that most periferals have dependencies on multiple clock
618 * domains. Many get their interface clocks from the L4 domain, but get
619 * functional clocks from fixed sources or other core domain derived
620 * clocks.
621 *-------------------------------------------------------------------------*/
622
623/* Base external input clocks */
624static struct clk func_32k_ck = {
625 .name = "func_32k_ck",
626 .rate = 32000,
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0
PW		 628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
629 .recalc = &propagate_rate,
046d6b28 630};
e32744b0 631
046d6b28
TL		 632/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
633static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
634 .name = "osc_ck",
046d6b28 635 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0
PW		 636 RATE_PROPAGATES,
637 .enable = &omap2_enable_osc_ck,
638 .disable = &omap2_disable_osc_ck,
639 .recalc = &omap2_osc_clk_recalc,
046d6b28
TL		 640};
641
642/* With out modem likely 12MHz, with modem likely 13MHz */
643static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
644 .name = "sys_ck", /* ~ ref_clk also */
645 .parent = &osc_ck,
046d6b28 646 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 647 ALWAYS_ENABLED | RATE_PROPAGATES,
046d6b28
TL		 648 .recalc = &omap2_sys_clk_recalc,
649};
e32744b0 650
046d6b28
TL		 651static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
652 .name = "alt_ck",
653 .rate = 54000000,
654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
655 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
e32744b0 656 .recalc = &propagate_rate,
046d6b28 657};
e32744b0 658
046d6b28
TL		 659/*
660 * Analog domain root source clocks
661 */
662
663/* dpll_ck, is broken out in to special cases through clksel */
6b8858a9
PW		 664/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
665 * deal with this
666 */
667
668static const struct dpll_data dpll_dd = {
669 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
670 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
671 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
672};
673
046d6b28
TL		 674static struct clk dpll_ck = {
675 .name = "dpll_ck",
676 .parent = &sys_ck, /* Can be func_32k also */
6b8858a9 677 .dpll_data = &dpll_dd,
046d6b28 678 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
6b8858a9
PW		 679 RATE_PROPAGATES | ALWAYS_ENABLED,
680 .recalc = &omap2_dpll_recalc,
681 .set_rate = &omap2_reprogram_dpll,
046d6b28
TL		 682};
683
684static struct clk apll96_ck = {
685 .name = "apll96_ck",
686 .parent = &sys_ck,
687 .rate = 96000000,
6b8858a9
PW		 688 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
689 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
690 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
691 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
692 .enable = &omap2_clk_fixed_enable,
693 .disable = &omap2_clk_fixed_disable,
694 .recalc = &propagate_rate,
046d6b28
TL		 695};
696
697static struct clk apll54_ck = {
698 .name = "apll54_ck",
699 .parent = &sys_ck,
700 .rate = 54000000,
701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
6b8858a9
PW		 702 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
703 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
704 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
705 .enable = &omap2_clk_fixed_enable,
706 .disable = &omap2_clk_fixed_disable,
707 .recalc = &propagate_rate,
046d6b28
TL		 708};
709
710/*
711 * PRCM digital base sources
712 */
e32744b0
PW		 713
714/* func_54m_ck */
715
716static const struct clksel_rate func_54m_apll54_rates[] = {
717 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
718 { .div = 0 },
719};
720
721static const struct clksel_rate func_54m_alt_rates[] = {
722 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
723 { .div = 0 },
724};
725
726static const struct clksel func_54m_clksel[] = {
727 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
728 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
729 { .parent = NULL },
730};
731
046d6b28
TL		 732static struct clk func_54m_ck = {
733 .name = "func_54m_ck",
734 .parent = &apll54_ck, /* can also be alt_clk */
046d6b28 735 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0
PW		 736 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
737 .init = &omap2_init_clksel_parent,
738 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
739 .clksel_mask = OMAP24XX_54M_SOURCE,
740 .clksel = func_54m_clksel,
741 .recalc = &omap2_clksel_recalc,
046d6b28 742};
e32744b0 743
046d6b28
TL		 744static struct clk core_ck = {
745 .name = "core_ck",
746 .parent = &dpll_ck, /* can also be 32k */
747 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
748 ALWAYS_ENABLED | RATE_PROPAGATES,
6b8858a9 749 .recalc = &followparent_recalc,
046d6b28 750};
e32744b0
PW		 751
752/* func_96m_ck */
753static const struct clksel_rate func_96m_apll96_rates[] = {
754 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
755 { .div = 0 },
046d6b28
TL		 756};
757
e32744b0
PW		 758static const struct clksel_rate func_96m_alt_rates[] = {
759 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
760 { .div = 0 },
761};
762
763static const struct clksel func_96m_clksel[] = {
764 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
765 { .parent = &alt_ck, .rates = func_96m_alt_rates },
766 { .parent = NULL }
767};
768
769/* The parent of this clock is not selectable on 2420. */
046d6b28
TL		 770static struct clk func_96m_ck = {
771 .name = "func_96m_ck",
772 .parent = &apll96_ck,
046d6b28 773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0
PW		 774 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
775 .init = &omap2_init_clksel_parent,
776 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
777 .clksel_mask = OMAP2430_96M_SOURCE,
778 .clksel = func_96m_clksel,
779 .recalc = &omap2_clksel_recalc,
780 .round_rate = &omap2_clksel_round_rate,
781 .set_rate = &omap2_clksel_set_rate
782};
783
784/* func_48m_ck */
785
786static const struct clksel_rate func_48m_apll96_rates[] = {
787 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
788 { .div = 0 },
789};
790
791static const struct clksel_rate func_48m_alt_rates[] = {
792 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
793 { .div = 0 },
794};
795
796static const struct clksel func_48m_clksel[] = {
797 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
798 { .parent = &alt_ck, .rates = func_48m_alt_rates },
799 { .parent = NULL }
046d6b28
TL		 800};
801
802static struct clk func_48m_ck = {
803 .name = "func_48m_ck",
804 .parent = &apll96_ck, /* 96M or Alt */
046d6b28 805 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0
PW		 806 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
807 .init = &omap2_init_clksel_parent,
808 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
809 .clksel_mask = OMAP24XX_48M_SOURCE,
810 .clksel = func_48m_clksel,
811 .recalc = &omap2_clksel_recalc,
812 .round_rate = &omap2_clksel_round_rate,
813 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 814};
815
816static struct clk func_12m_ck = {
817 .name = "func_12m_ck",
818 .parent = &func_48m_ck,
e32744b0 819 .fixed_div = 4,
046d6b28 820 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0
PW		 821 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
822 .recalc = &omap2_fixed_divisor_recalc,
046d6b28
TL		 823};
824
825/* Secure timer, only available in secure mode */
826static struct clk wdt1_osc_ck = {
827 .name = "ck_wdt1_osc",
828 .parent = &osc_ck,
829 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 830 .recalc = &followparent_recalc,
831};
832
833/*
834 * The common_clkout* clksel_rate structs are common to
835 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
836 * sys_clkout2_* are 2420-only, so the
837 * clksel_rate flags fields are inaccurate for those clocks. This is
838 * harmless since access to those clocks are gated by the struct clk
839 * flags fields, which mark them as 2420-only.
840 */
841static const struct clksel_rate common_clkout_src_core_rates[] = {
842 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
843 { .div = 0 }
844};
845
846static const struct clksel_rate common_clkout_src_sys_rates[] = {
847 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
848 { .div = 0 }
849};
850
851static const struct clksel_rate common_clkout_src_96m_rates[] = {
852 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
853 { .div = 0 }
854};
855
856static const struct clksel_rate common_clkout_src_54m_rates[] = {
857 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
858 { .div = 0 }
859};
860
861static const struct clksel common_clkout_src_clksel[] = {
862 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
863 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
864 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
865 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
866 { .parent = NULL }
867};
868
869static struct clk sys_clkout_src = {
870 .name = "sys_clkout_src",
871 .parent = &func_54m_ck,
872 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
873 RATE_PROPAGATES,
874 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
875 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
876 .init = &omap2_init_clksel_parent,
877 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
878 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
879 .clksel = common_clkout_src_clksel,
880 .recalc = &omap2_clksel_recalc,
881 .round_rate = &omap2_clksel_round_rate,
882 .set_rate = &omap2_clksel_set_rate
883};
884
885static const struct clksel_rate common_clkout_rates[] = {
886 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
887 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
888 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
889 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
890 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
891 { .div = 0 },
892};
893
894static const struct clksel sys_clkout_clksel[] = {
895 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
896 { .parent = NULL }
046d6b28
TL		 897};
898
899static struct clk sys_clkout = {
900 .name = "sys_clkout",
e32744b0 901 .parent = &sys_clkout_src,
046d6b28 902 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0
PW		 903 PARENT_CONTROLS_CLOCK,
904 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
905 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
906 .clksel = sys_clkout_clksel,
907 .recalc = &omap2_clksel_recalc,
908 .round_rate = &omap2_clksel_round_rate,
909 .set_rate = &omap2_clksel_set_rate
910};
911
912/* In 2430, new in 2420 ES2 */
913static struct clk sys_clkout2_src = {
914 .name = "sys_clkout2_src",
915 .parent = &func_54m_ck,
916 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
917 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
918 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
919 .init = &omap2_init_clksel_parent,
920 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
921 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
922 .clksel = common_clkout_src_clksel,
046d6b28 923 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 924 .round_rate = &omap2_clksel_round_rate,
925 .set_rate = &omap2_clksel_set_rate
926};
927
928static const struct clksel sys_clkout2_clksel[] = {
929 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
930 { .parent = NULL }
046d6b28
TL		 931};
932
933/* In 2430, new in 2420 ES2 */
934static struct clk sys_clkout2 = {
935 .name = "sys_clkout2",
e32744b0
PW		 936 .parent = &sys_clkout2_src,
937 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
938 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
939 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
940 .clksel = sys_clkout2_clksel,
046d6b28 941 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 942 .round_rate = &omap2_clksel_round_rate,
943 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 944};
945
b824efae
TL		 946static struct clk emul_ck = {
947 .name = "emul_ck",
948 .parent = &func_54m_ck,
949 .flags = CLOCK_IN_OMAP242X,
e32744b0
PW		 950 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
951 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
952 .recalc = &followparent_recalc,
b824efae
TL		 953
954};
e32744b0 955
046d6b28
TL		 956/*
957 * MPU clock domain
958 * Clocks:
959 * MPU_FCLK, MPU_ICLK
960 * INT_M_FCLK, INT_M_I_CLK
961 *
962 * - Individual clocks are hardware managed.
963 * - Base divider comes from: CM_CLKSEL_MPU
964 *
965 */
e32744b0
PW		 966static const struct clksel_rate mpu_core_rates[] = {
967 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
968 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
969 { .div = 4, .val = 4, .flags = RATE_IN_242X },
970 { .div = 6, .val = 6, .flags = RATE_IN_242X },
971 { .div = 8, .val = 8, .flags = RATE_IN_242X },
972 { .div = 0 },
973};
974
975static const struct clksel mpu_clksel[] = {
976 { .parent = &core_ck, .rates = mpu_core_rates },
977 { .parent = NULL }
978};
979
046d6b28
TL		 980static struct clk mpu_ck = { /* Control cpu */
981 .name = "mpu_ck",
982 .parent = &core_ck,
6b8858a9
PW		 983 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
984 ALWAYS_ENABLED | DELAYED_APP |
046d6b28 985 CONFIG_PARTICIPANT | RATE_PROPAGATES,
6b8858a9
PW		 986 .init = &omap2_init_clksel_parent,
987 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
988 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
e32744b0 989 .clksel = mpu_clksel,
046d6b28 990 .recalc = &omap2_clksel_recalc,
6b8858a9
PW		 991 .round_rate = &omap2_clksel_round_rate,
992 .set_rate = &omap2_clksel_set_rate
046d6b28 993};
e32744b0 994
046d6b28
TL		 995/*
996 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
997 * Clocks:
e32744b0 998 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
046d6b28 999 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
e32744b0
PW		 1000 *
1001 * Won't be too specific here. The core clock comes into this block
1002 * it is divided then tee'ed. One branch goes directly to xyz enable
1003 * controls. The other branch gets further divided by 2 then possibly
1004 * routed into a synchronizer and out of clocks abc.
046d6b28 1005 */
e32744b0
PW		 1006static const struct clksel_rate dsp_fck_core_rates[] = {
1007 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1008 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1009 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1010 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1011 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1012 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1013 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1014 { .div = 0 },
1015};
1016
1017static const struct clksel dsp_fck_clksel[] = {
1018 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1019 { .parent = NULL }
1020};
1021
1022static struct clk dsp_fck = {
1023 .name = "dsp_fck",
046d6b28 1024 .parent = &core_ck,
e32744b0
PW		 1025 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1026 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1027 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1028 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1029 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1030 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1031 .clksel = dsp_fck_clksel,
046d6b28 1032 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1033 .round_rate = &omap2_clksel_round_rate,
1034 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1035};
1036
e32744b0
PW		 1037/* DSP interface clock */
1038static const struct clksel_rate dsp_irate_ick_rates[] = {
1039 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1040 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1041 { .div = 3, .val = 3, .flags = RATE_IN_243X },
1042 { .div = 0 },
1043};
1044
1045static const struct clksel dsp_irate_ick_clksel[] = {
1046 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1047 { .parent = NULL }
046d6b28
TL		 1048};
1049
1050/*
e32744b0
PW		 1051 * This clock does not exist as such in the TRM, but is added to
1052 * separate source selection from XXX
046d6b28 1053 */
e32744b0
PW		 1054static struct clk dsp_irate_ick = {
1055 .name = "dsp_irate_ick",
1056 .parent = &dsp_fck,
1057 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1058 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1059 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1060 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1061 .clksel = dsp_irate_ick_clksel,
046d6b28 1062 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1063 .round_rate = &omap2_clksel_round_rate,
1064 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1065};
1066
e32744b0 1067/* 2420 only */
046d6b28
TL		 1068static struct clk dsp_ick = {
1069 .name = "dsp_ick", /* apparently ipi and isp */
e32744b0
PW		 1070 .parent = &dsp_irate_ick,
1071 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1072 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1073 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1074};
1075
1076/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1077static struct clk iva2_1_ick = {
1078 .name = "iva2_1_ick",
1079 .parent = &dsp_irate_ick,
1080 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1081 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1082 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
046d6b28
TL		 1083};
1084
1085static struct clk iva1_ifck = {
1086 .name = "iva1_ifck",
1087 .parent = &core_ck,
e32744b0
PW		 1088 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1089 RATE_PROPAGATES | DELAYED_APP,
1090 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1091 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1092 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1093 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1094 .clksel = dsp_fck_clksel,
046d6b28 1095 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1096 .round_rate = &omap2_clksel_round_rate,
1097 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1098};
1099
1100/* IVA1 mpu/int/i/f clocks are /2 of parent */
1101static struct clk iva1_mpu_int_ifck = {
1102 .name = "iva1_mpu_int_ifck",
1103 .parent = &iva1_ifck,
e32744b0
PW		 1104 .flags = CLOCK_IN_OMAP242X,
1105 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1106 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1107 .fixed_div = 2,
1108 .recalc = &omap2_fixed_divisor_recalc,
046d6b28
TL		 1109};
1110
1111/*
1112 * L3 clock domain
1113 * L3 clocks are used for both interface and functional clocks to
1114 * multiple entities. Some of these clocks are completely managed
1115 * by hardware, and some others allow software control. Hardware
1116 * managed ones general are based on directly CLK_REQ signals and
1117 * various auto idle settings. The functional spec sets many of these
1118 * as 'tie-high' for their enables.
1119 *
1120 * I-CLOCKS:
1121 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1122 * CAM, HS-USB.
1123 * F-CLOCK
1124 * SSI.
1125 *
1126 * GPMC memories and SDRC have timing and clock sensitive registers which
1127 * may very well need notification when the clock changes. Currently for low
1128 * operating points, these are taken care of in sleep.S.
1129 */
e32744b0
PW		 1130static const struct clksel_rate core_l3_core_rates[] = {
1131 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1132 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1133 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1134 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1135 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1136 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1137 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1138 { .div = 0 }
1139};
1140
1141static const struct clksel core_l3_clksel[] = {
1142 { .parent = &core_ck, .rates = core_l3_core_rates },
1143 { .parent = NULL }
1144};
1145
046d6b28
TL		 1146static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1147 .name = "core_l3_ck",
1148 .parent = &core_ck,
1149 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0
PW		 1150 ALWAYS_ENABLED | DELAYED_APP |
1151 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1152 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1153 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1154 .clksel = core_l3_clksel,
046d6b28 1155 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1156 .round_rate = &omap2_clksel_round_rate,
1157 .set_rate = &omap2_clksel_set_rate
1158};
1159
1160/* usb_l4_ick */
1161static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1162 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1163 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1164 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1165 { .div = 0 }
1166};
1167
1168static const struct clksel usb_l4_ick_clksel[] = {
1169 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1170 { .parent = NULL },
046d6b28
TL		 1171};
1172
1173static struct clk usb_l4_ick = { /* FS-USB interface clock */
1174 .name = "usb_l4_ick",
fde0fd49 1175 .parent = &core_l3_ck,
046d6b28 1176 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0
PW		 1177 DELAYED_APP | CONFIG_PARTICIPANT,
1178 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1179 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1180 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1181 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1182 .clksel = usb_l4_ick_clksel,
046d6b28 1183 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1184 .round_rate = &omap2_clksel_round_rate,
1185 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1186};
1187
1188/*
1189 * SSI is in L3 management domain, its direct parent is core not l3,
1190 * many core power domain entities are grouped into the L3 clock
1191 * domain.
1192 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1193 *
1194 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1195 */
e32744b0
PW		 1196static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1197 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1198 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1199 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1200 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1201 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1202 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1203 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1204 { .div = 0 }
1205};
1206
1207static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1208 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1209 { .parent = NULL }
1210};
1211
046d6b28
TL		 1212static struct clk ssi_ssr_sst_fck = {
1213 .name = "ssi_fck",
1214 .parent = &core_ck,
1215 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0
PW		 1216 DELAYED_APP,
1217 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1218 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1219 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1220 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1221 .clksel = ssi_ssr_sst_fck_clksel,
046d6b28 1222 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1223 .round_rate = &omap2_clksel_round_rate,
1224 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1225};
1226
1227/*
1228 * GFX clock domain
1229 * Clocks:
1230 * GFX_FCLK, GFX_ICLK
1231 * GFX_CG1(2d), GFX_CG2(3d)
1232 *
1233 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1234 * The 2d and 3d clocks run at a hardware determined
1235 * divided value of fclk.
1236 *
1237 */
e32744b0
PW		 1238/* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1239
1240/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1241static const struct clksel gfx_fck_clksel[] = {
1242 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1243 { .parent = NULL },
1244};
1245
046d6b28
TL		 1246static struct clk gfx_3d_fck = {
1247 .name = "gfx_3d_fck",
1248 .parent = &core_l3_ck,
e32744b0
PW		 1249 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1250 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1251 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1252 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1253 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1254 .clksel = gfx_fck_clksel,
046d6b28 1255 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1256 .round_rate = &omap2_clksel_round_rate,
1257 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1258};
1259
1260static struct clk gfx_2d_fck = {
1261 .name = "gfx_2d_fck",
1262 .parent = &core_l3_ck,
e32744b0
PW		 1263 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1264 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1265 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1266 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1267 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1268 .clksel = gfx_fck_clksel,
046d6b28 1269 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1270 .round_rate = &omap2_clksel_round_rate,
1271 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1272};
1273
1274static struct clk gfx_ick = {
1275 .name = "gfx_ick", /* From l3 */
1276 .parent = &core_l3_ck,
e32744b0
PW		 1277 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1278 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1279 .enable_bit = OMAP_EN_GFX_SHIFT,
1280 .recalc = &followparent_recalc,
046d6b28
TL		 1281};
1282
1283/*
1284 * Modem clock domain (2430)
1285 * CLOCKS:
1286 * MDM_OSC_CLK
1287 * MDM_ICLK
e32744b0 1288 * These clocks are usable in chassis mode only.
046d6b28 1289 */
e32744b0
PW		 1290static const struct clksel_rate mdm_ick_core_rates[] = {
1291 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1292 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1293 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1294 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1295 { .div = 0 }
1296};
1297
1298static const struct clksel mdm_ick_clksel[] = {
1299 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1300 { .parent = NULL }
1301};
1302
046d6b28
TL		 1303static struct clk mdm_ick = { /* used both as a ick and fck */
1304 .name = "mdm_ick",
1305 .parent = &core_ck,
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PW		 1306 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1307 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1308 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1309 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1310 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1311 .clksel = mdm_ick_clksel,
046d6b28 1312 .recalc = &omap2_clksel_recalc,
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PW		 1313 .round_rate = &omap2_clksel_round_rate,
1314 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1315};
1316
1317static struct clk mdm_osc_ck = {
1318 .name = "mdm_osc_ck",
046d6b28 1319 .parent = &osc_ck,
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PW		 1320 .flags = CLOCK_IN_OMAP243X,
1321 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1322 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1323 .recalc = &followparent_recalc,
046d6b28
TL		 1324};
1325
1326/*
1327 * L4 clock management domain
1328 *
1329 * This domain contains lots of interface clocks from the L4 interface, some
1330 * functional clocks. Fixed APLL functional source clocks are managed in
1331 * this domain.
1332 */
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PW		 1333static const struct clksel_rate l4_core_l3_rates[] = {
1334 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1335 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1336 { .div = 0 }
1337};
1338
1339static const struct clksel l4_clksel[] = {
1340 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1341 { .parent = NULL }
1342};
1343
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TL		 1344static struct clk l4_ck = { /* used both as an ick and fck */
1345 .name = "l4_ck",
1346 .parent = &core_l3_ck,
1347 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
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PW		 1348 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1349 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1350 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1351 .clksel = l4_clksel,
046d6b28 1352 .recalc = &omap2_clksel_recalc,
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PW		 1353 .round_rate = &omap2_clksel_round_rate,
1354 .set_rate = &omap2_clksel_set_rate
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TL		 1355};
1356
1357static struct clk ssi_l4_ick = {
1358 .name = "ssi_l4_ick",
1359 .parent = &l4_ck,
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PW		 1360 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1361 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1362 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1363 .recalc = &followparent_recalc,
046d6b28
TL		 1364};
1365
1366/*
1367 * DSS clock domain
1368 * CLOCKs:
1369 * DSS_L4_ICLK, DSS_L3_ICLK,
1370 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1371 *
1372 * DSS is both initiator and target.
1373 */
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PW		 1374/* XXX Add RATE_NOT_VALIDATED */
1375
1376static const struct clksel_rate dss1_fck_sys_rates[] = {
1377 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1378 { .div = 0 }
1379};
1380
1381static const struct clksel_rate dss1_fck_core_rates[] = {
1382 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1383 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1384 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1385 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1386 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1387 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1388 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1389 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1390 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1391 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1392 { .div = 0 }
1393};
1394
1395static const struct clksel dss1_fck_clksel[] = {
1396 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1397 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1398 { .parent = NULL },
1399};
1400
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TL		 1401static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1402 .name = "dss_ick",
1403 .parent = &l4_ck, /* really both l3 and l4 */
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PW		 1404 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1405 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1406 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1407 .recalc = &followparent_recalc,
046d6b28
TL		 1408};
1409
1410static struct clk dss1_fck = {
1411 .name = "dss1_fck",
1412 .parent = &core_ck, /* Core or sys */
1413 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
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PW		 1414 DELAYED_APP,
1415 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1416 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1417 .init = &omap2_init_clksel_parent,
1418 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1419 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1420 .clksel = dss1_fck_clksel,
046d6b28 1421 .recalc = &omap2_clksel_recalc,
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PW		 1422 .round_rate = &omap2_clksel_round_rate,
1423 .set_rate = &omap2_clksel_set_rate
1424};
1425
1426static const struct clksel_rate dss2_fck_sys_rates[] = {
1427 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1428 { .div = 0 }
1429};
1430
1431static const struct clksel_rate dss2_fck_48m_rates[] = {
1432 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1433 { .div = 0 }
1434};
1435
1436static const struct clksel dss2_fck_clksel[] = {
1437 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1438 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1439 { .parent = NULL }
046d6b28
TL		 1440};
1441
1442static struct clk dss2_fck = { /* Alt clk used in power management */
1443 .name = "dss2_fck",
1444 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1445 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
474844f7 1446 DELAYED_APP,
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PW		 1447 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1448 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1449 .init = &omap2_init_clksel_parent,
1450 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1451 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1452 .clksel = dss2_fck_clksel,
1453 .recalc = &followparent_recalc,
046d6b28
TL		 1454};
1455
1456static struct clk dss_54m_fck = { /* Alt clk used in power management */
1457 .name = "dss_54m_fck", /* 54m tv clk */
1458 .parent = &func_54m_ck,
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PW		 1459 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1461 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1462 .recalc = &followparent_recalc,
046d6b28
TL		 1463};
1464
1465/*
1466 * CORE power domain ICLK & FCLK defines.
1467 * Many of the these can have more than one possible parent. Entries
1468 * here will likely have an L4 interface parent, and may have multiple
1469 * functional clock parents.
1470 */
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PW		 1471static const struct clksel_rate gpt_alt_rates[] = {
1472 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1473 { .div = 0 }
1474};
1475
1476static const struct clksel omap24xx_gpt_clksel[] = {
1477 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1478 { .parent = &sys_ck, .rates = gpt_sys_rates },
1479 { .parent = &alt_ck, .rates = gpt_alt_rates },
1480 { .parent = NULL },
1481};
1482
046d6b28
TL		 1483static struct clk gpt1_ick = {
1484 .name = "gpt1_ick",
1485 .parent = &l4_ck,
1486 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1487 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1488 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1489 .recalc = &followparent_recalc,
046d6b28
TL		 1490};
1491
1492static struct clk gpt1_fck = {
1493 .name = "gpt1_fck",
1494 .parent = &func_32k_ck,
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PW		 1495 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1496 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1497 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1498 .init = &omap2_init_clksel_parent,
1499 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1500 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1501 .clksel = omap24xx_gpt_clksel,
1502 .recalc = &omap2_clksel_recalc,
1503 .round_rate = &omap2_clksel_round_rate,
1504 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1505};
1506
1507static struct clk gpt2_ick = {
1508 .name = "gpt2_ick",
1509 .parent = &l4_ck,
1510 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1511 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1512 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1513 .recalc = &followparent_recalc,
046d6b28
TL		 1514};
1515
1516static struct clk gpt2_fck = {
1517 .name = "gpt2_fck",
1518 .parent = &func_32k_ck,
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PW		 1519 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1520 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1521 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1522 .init = &omap2_init_clksel_parent,
1523 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1524 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1525 .clksel = omap24xx_gpt_clksel,
1526 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1527};
1528
1529static struct clk gpt3_ick = {
1530 .name = "gpt3_ick",
1531 .parent = &l4_ck,
1532 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 1533 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1534 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1535 .recalc = &followparent_recalc,
046d6b28
TL		 1536};
1537
1538static struct clk gpt3_fck = {
1539 .name = "gpt3_fck",
1540 .parent = &func_32k_ck,
e32744b0
PW		 1541 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1543 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1544 .init = &omap2_init_clksel_parent,
1545 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1546 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1547 .clksel = omap24xx_gpt_clksel,
1548 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1549};
1550
1551static struct clk gpt4_ick = {
1552 .name = "gpt4_ick",
1553 .parent = &l4_ck,
1554 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1555 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1556 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1557 .recalc = &followparent_recalc,
046d6b28
TL		 1558};
1559
1560static struct clk gpt4_fck = {
1561 .name = "gpt4_fck",
1562 .parent = &func_32k_ck,
e32744b0
PW		 1563 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1564 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1565 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1566 .init = &omap2_init_clksel_parent,
1567 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1568 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1569 .clksel = omap24xx_gpt_clksel,
1570 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1571};
1572
1573static struct clk gpt5_ick = {
1574 .name = "gpt5_ick",
1575 .parent = &l4_ck,
1576 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 1577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1578 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1579 .recalc = &followparent_recalc,
046d6b28
TL		 1580};
1581
1582static struct clk gpt5_fck = {
1583 .name = "gpt5_fck",
1584 .parent = &func_32k_ck,
e32744b0
PW		 1585 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1586 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1587 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1588 .init = &omap2_init_clksel_parent,
1589 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1590 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1591 .clksel = omap24xx_gpt_clksel,
1592 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1593};
1594
1595static struct clk gpt6_ick = {
1596 .name = "gpt6_ick",
1597 .parent = &l4_ck,
1598 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 1599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1600 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1601 .recalc = &followparent_recalc,
046d6b28
TL		 1602};
1603
1604static struct clk gpt6_fck = {
1605 .name = "gpt6_fck",
1606 .parent = &func_32k_ck,
e32744b0
PW		 1607 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1610 .init = &omap2_init_clksel_parent,
1611 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1612 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1613 .clksel = omap24xx_gpt_clksel,
1614 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1615};
1616
1617static struct clk gpt7_ick = {
1618 .name = "gpt7_ick",
1619 .parent = &l4_ck,
1620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 1621 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1622 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1623 .recalc = &followparent_recalc,
046d6b28
TL		 1624};
1625
1626static struct clk gpt7_fck = {
1627 .name = "gpt7_fck",
1628 .parent = &func_32k_ck,
e32744b0
PW		 1629 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1630 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1631 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1632 .init = &omap2_init_clksel_parent,
1633 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1634 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1635 .clksel = omap24xx_gpt_clksel,
1636 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1637};
1638
1639static struct clk gpt8_ick = {
1640 .name = "gpt8_ick",
1641 .parent = &l4_ck,
1642 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 1643 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1644 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1645 .recalc = &followparent_recalc,
046d6b28
TL		 1646};
1647
1648static struct clk gpt8_fck = {
1649 .name = "gpt8_fck",
1650 .parent = &func_32k_ck,
e32744b0
PW		 1651 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1652 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1653 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1654 .init = &omap2_init_clksel_parent,
1655 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1656 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1657 .clksel = omap24xx_gpt_clksel,
1658 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1659};
1660
1661static struct clk gpt9_ick = {
1662 .name = "gpt9_ick",
1663 .parent = &l4_ck,
1664 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1666 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1667 .recalc = &followparent_recalc,
046d6b28
TL		 1668};
1669
1670static struct clk gpt9_fck = {
1671 .name = "gpt9_fck",
1672 .parent = &func_32k_ck,
e32744b0
PW		 1673 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1674 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1675 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1676 .init = &omap2_init_clksel_parent,
1677 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1678 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1679 .clksel = omap24xx_gpt_clksel,
1680 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1681};
1682
1683static struct clk gpt10_ick = {
1684 .name = "gpt10_ick",
1685 .parent = &l4_ck,
1686 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 1687 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1688 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1689 .recalc = &followparent_recalc,
046d6b28
TL		 1690};
1691
1692static struct clk gpt10_fck = {
1693 .name = "gpt10_fck",
1694 .parent = &func_32k_ck,
e32744b0
PW		 1695 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1696 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1697 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1698 .init = &omap2_init_clksel_parent,
1699 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1700 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1701 .clksel = omap24xx_gpt_clksel,
1702 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1703};
1704
1705static struct clk gpt11_ick = {
1706 .name = "gpt11_ick",
1707 .parent = &l4_ck,
1708 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 1709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1710 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1711 .recalc = &followparent_recalc,
046d6b28
TL		 1712};
1713
1714static struct clk gpt11_fck = {
1715 .name = "gpt11_fck",
1716 .parent = &func_32k_ck,
e32744b0
PW		 1717 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1718 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1719 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1720 .init = &omap2_init_clksel_parent,
1721 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1722 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1723 .clksel = omap24xx_gpt_clksel,
1724 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1725};
1726
1727static struct clk gpt12_ick = {
1728 .name = "gpt12_ick",
1729 .parent = &l4_ck,
1730 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1732 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1733 .recalc = &followparent_recalc,
046d6b28
TL		 1734};
1735
1736static struct clk gpt12_fck = {
1737 .name = "gpt12_fck",
1738 .parent = &func_32k_ck,
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PW		 1739 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1740 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1741 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1742 .init = &omap2_init_clksel_parent,
1743 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1744 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1745 .clksel = omap24xx_gpt_clksel,
1746 .recalc = &omap2_clksel_recalc,
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TL		 1747};
1748
1749static struct clk mcbsp1_ick = {
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EV		 1750 .name = "mcbsp_ick",
1751 .id = 1,
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TL		 1752 .parent = &l4_ck,
1753 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1755 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1756 .recalc = &followparent_recalc,
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TL		 1757};
1758
1759static struct clk mcbsp1_fck = {
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EV		 1760 .name = "mcbsp_fck",
1761 .id = 1,
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TL		 1762 .parent = &func_96m_ck,
1763 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1764 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1765 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1766 .recalc = &followparent_recalc,
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TL		 1767};
1768
1769static struct clk mcbsp2_ick = {
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EV		 1770 .name = "mcbsp_ick",
1771 .id = 2,
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TL		 1772 .parent = &l4_ck,
1773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1774 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1775 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1776 .recalc = &followparent_recalc,
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TL		 1777};
1778
1779static struct clk mcbsp2_fck = {
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EV		 1780 .name = "mcbsp_fck",
1781 .id = 2,
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TL		 1782 .parent = &func_96m_ck,
1783 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1785 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1786 .recalc = &followparent_recalc,
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TL		 1787};
1788
1789static struct clk mcbsp3_ick = {
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EV		 1790 .name = "mcbsp_ick",
1791 .id = 3,
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TL		 1792 .parent = &l4_ck,
1793 .flags = CLOCK_IN_OMAP243X,
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PW		 1794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1795 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1796 .recalc = &followparent_recalc,
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TL		 1797};
1798
1799static struct clk mcbsp3_fck = {
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EV		 1800 .name = "mcbsp_fck",
1801 .id = 3,
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TL		 1802 .parent = &func_96m_ck,
1803 .flags = CLOCK_IN_OMAP243X,
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PW		 1804 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1805 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1806 .recalc = &followparent_recalc,
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TL		 1807};
1808
1809static struct clk mcbsp4_ick = {
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EV		 1810 .name = "mcbsp_ick",
1811 .id = 4,
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TL		 1812 .parent = &l4_ck,
1813 .flags = CLOCK_IN_OMAP243X,
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PW		 1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1815 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1816 .recalc = &followparent_recalc,
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TL		 1817};
1818
1819static struct clk mcbsp4_fck = {
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EV		 1820 .name = "mcbsp_fck",
1821 .id = 4,
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TL		 1822 .parent = &func_96m_ck,
1823 .flags = CLOCK_IN_OMAP243X,
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PW		 1824 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1825 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1826 .recalc = &followparent_recalc,
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TL		 1827};
1828
1829static struct clk mcbsp5_ick = {
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EV		 1830 .name = "mcbsp_ick",
1831 .id = 5,
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TL		 1832 .parent = &l4_ck,
1833 .flags = CLOCK_IN_OMAP243X,
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PW		 1834 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1835 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1836 .recalc = &followparent_recalc,
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TL		 1837};
1838
1839static struct clk mcbsp5_fck = {
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EV		 1840 .name = "mcbsp_fck",
1841 .id = 5,
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TL		 1842 .parent = &func_96m_ck,
1843 .flags = CLOCK_IN_OMAP243X,
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PW		 1844 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1845 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1846 .recalc = &followparent_recalc,
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TL		 1847};
1848
1849static struct clk mcspi1_ick = {
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TL		 1850 .name = "mcspi_ick",
1851 .id = 1,
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TL		 1852 .parent = &l4_ck,
1853 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1854 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1855 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1856 .recalc = &followparent_recalc,
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TL		 1857};
1858
1859static struct clk mcspi1_fck = {
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TL		 1860 .name = "mcspi_fck",
1861 .id = 1,
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TL		 1862 .parent = &func_48m_ck,
1863 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1864 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1865 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1866 .recalc = &followparent_recalc,
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TL		 1867};
1868
1869static struct clk mcspi2_ick = {
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TL		 1870 .name = "mcspi_ick",
1871 .id = 2,
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TL		 1872 .parent = &l4_ck,
1873 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1874 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1875 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1876 .recalc = &followparent_recalc,
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TL		 1877};
1878
1879static struct clk mcspi2_fck = {
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TL		 1880 .name = "mcspi_fck",
1881 .id = 2,
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TL		 1882 .parent = &func_48m_ck,
1883 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1884 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1885 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1886 .recalc = &followparent_recalc,
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TL		 1887};
1888
1889static struct clk mcspi3_ick = {
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TL		 1890 .name = "mcspi_ick",
1891 .id = 3,
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TL		 1892 .parent = &l4_ck,
1893 .flags = CLOCK_IN_OMAP243X,
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PW		 1894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1895 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1896 .recalc = &followparent_recalc,
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TL		 1897};
1898
1899static struct clk mcspi3_fck = {
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TL		 1900 .name = "mcspi_fck",
1901 .id = 3,
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TL		 1902 .parent = &func_48m_ck,
1903 .flags = CLOCK_IN_OMAP243X,
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PW		 1904 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1905 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1906 .recalc = &followparent_recalc,
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TL		 1907};
1908
1909static struct clk uart1_ick = {
1910 .name = "uart1_ick",
1911 .parent = &l4_ck,
1912 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1914 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1915 .recalc = &followparent_recalc,
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TL		 1916};
1917
1918static struct clk uart1_fck = {
1919 .name = "uart1_fck",
1920 .parent = &func_48m_ck,
1921 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1923 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1924 .recalc = &followparent_recalc,
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TL		 1925};
1926
1927static struct clk uart2_ick = {
1928 .name = "uart2_ick",
1929 .parent = &l4_ck,
1930 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1932 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1933 .recalc = &followparent_recalc,
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TL		 1934};
1935
1936static struct clk uart2_fck = {
1937 .name = "uart2_fck",
1938 .parent = &func_48m_ck,
1939 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1941 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1942 .recalc = &followparent_recalc,
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TL		 1943};
1944
1945static struct clk uart3_ick = {
1946 .name = "uart3_ick",
1947 .parent = &l4_ck,
1948 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1949 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1950 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1951 .recalc = &followparent_recalc,
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TL		 1952};
1953
1954static struct clk uart3_fck = {
1955 .name = "uart3_fck",
1956 .parent = &func_48m_ck,
1957 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1958 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1959 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1960 .recalc = &followparent_recalc,
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TL		 1961};
1962
1963static struct clk gpios_ick = {
1964 .name = "gpios_ick",
1965 .parent = &l4_ck,
1966 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1967 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1968 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1969 .recalc = &followparent_recalc,
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TL		 1970};
1971
1972static struct clk gpios_fck = {
1973 .name = "gpios_fck",
1974 .parent = &func_32k_ck,
1975 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1976 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1977 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1978 .recalc = &followparent_recalc,
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TL		 1979};
1980
1981static struct clk mpu_wdt_ick = {
1982 .name = "mpu_wdt_ick",
1983 .parent = &l4_ck,
1984 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1985 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1986 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1987 .recalc = &followparent_recalc,
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TL		 1988};
1989
1990static struct clk mpu_wdt_fck = {
1991 .name = "mpu_wdt_fck",
1992 .parent = &func_32k_ck,
1993 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 1994 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1995 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1996 .recalc = &followparent_recalc,
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TL		 1997};
1998
1999static struct clk sync_32k_ick = {
2000 .name = "sync_32k_ick",
2001 .parent = &l4_ck,
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PW		 2002 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2003 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2004 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
2005 .recalc = &followparent_recalc,
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TL		 2006};
2007static struct clk wdt1_ick = {
2008 .name = "wdt1_ick",
2009 .parent = &l4_ck,
2010 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2011 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2012 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2013 .recalc = &followparent_recalc,
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TL		 2014};
2015static struct clk omapctrl_ick = {
2016 .name = "omapctrl_ick",
2017 .parent = &l4_ck,
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PW		 2018 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2019 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2020 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2021 .recalc = &followparent_recalc,
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TL		 2022};
2023static struct clk icr_ick = {
2024 .name = "icr_ick",
2025 .parent = &l4_ck,
2026 .flags = CLOCK_IN_OMAP243X,
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PW		 2027 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2028 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2029 .recalc = &followparent_recalc,
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TL		 2030};
2031
2032static struct clk cam_ick = {
2033 .name = "cam_ick",
2034 .parent = &l4_ck,
2035 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2036 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2037 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2038 .recalc = &followparent_recalc,
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TL		 2039};
2040
2041static struct clk cam_fck = {
2042 .name = "cam_fck",
2043 .parent = &func_96m_ck,
2044 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2045 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2046 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2047 .recalc = &followparent_recalc,
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TL		 2048};
2049
2050static struct clk mailboxes_ick = {
2051 .name = "mailboxes_ick",
2052 .parent = &l4_ck,
2053 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2054 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2055 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2056 .recalc = &followparent_recalc,
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TL		 2057};
2058
2059static struct clk wdt4_ick = {
2060 .name = "wdt4_ick",
2061 .parent = &l4_ck,
2062 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2063 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2064 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2065 .recalc = &followparent_recalc,
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TL		 2066};
2067
2068static struct clk wdt4_fck = {
2069 .name = "wdt4_fck",
2070 .parent = &func_32k_ck,
2071 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2072 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2073 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2074 .recalc = &followparent_recalc,
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TL		 2075};
2076
2077static struct clk wdt3_ick = {
2078 .name = "wdt3_ick",
2079 .parent = &l4_ck,
2080 .flags = CLOCK_IN_OMAP242X,
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PW		 2081 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2082 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2083 .recalc = &followparent_recalc,
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TL		 2084};
2085
2086static struct clk wdt3_fck = {
2087 .name = "wdt3_fck",
2088 .parent = &func_32k_ck,
2089 .flags = CLOCK_IN_OMAP242X,
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PW		 2090 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2091 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2092 .recalc = &followparent_recalc,
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TL		 2093};
2094
2095static struct clk mspro_ick = {
2096 .name = "mspro_ick",
2097 .parent = &l4_ck,
2098 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2099 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2100 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2101 .recalc = &followparent_recalc,
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TL		 2102};
2103
2104static struct clk mspro_fck = {
2105 .name = "mspro_fck",
2106 .parent = &func_96m_ck,
2107 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2108 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2109 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2110 .recalc = &followparent_recalc,
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TL		 2111};
2112
2113static struct clk mmc_ick = {
2114 .name = "mmc_ick",
2115 .parent = &l4_ck,
2116 .flags = CLOCK_IN_OMAP242X,
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PW		 2117 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2118 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2119 .recalc = &followparent_recalc,
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TL		 2120};
2121
2122static struct clk mmc_fck = {
2123 .name = "mmc_fck",
2124 .parent = &func_96m_ck,
2125 .flags = CLOCK_IN_OMAP242X,
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PW		 2126 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2127 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2128 .recalc = &followparent_recalc,
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TL		 2129};
2130
2131static struct clk fac_ick = {
2132 .name = "fac_ick",
2133 .parent = &l4_ck,
2134 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2135 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2136 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2137 .recalc = &followparent_recalc,
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TL		 2138};
2139
2140static struct clk fac_fck = {
2141 .name = "fac_fck",
2142 .parent = &func_12m_ck,
2143 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2144 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2145 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2146 .recalc = &followparent_recalc,
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TL		 2147};
2148
2149static struct clk eac_ick = {
2150 .name = "eac_ick",
2151 .parent = &l4_ck,
2152 .flags = CLOCK_IN_OMAP242X,
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PW		 2153 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2154 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2155 .recalc = &followparent_recalc,
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TL		 2156};
2157
2158static struct clk eac_fck = {
2159 .name = "eac_fck",
2160 .parent = &func_96m_ck,
2161 .flags = CLOCK_IN_OMAP242X,
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PW		 2162 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2163 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2164 .recalc = &followparent_recalc,
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TL		 2165};
2166
2167static struct clk hdq_ick = {
2168 .name = "hdq_ick",
2169 .parent = &l4_ck,
2170 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2171 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2172 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2173 .recalc = &followparent_recalc,
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TL		 2174};
2175
2176static struct clk hdq_fck = {
2177 .name = "hdq_fck",
2178 .parent = &func_12m_ck,
2179 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2180 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2181 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2182 .recalc = &followparent_recalc,
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TL		 2183};
2184
2185static struct clk i2c2_ick = {
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TL		 2186 .name = "i2c_ick",
2187 .id = 2,
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TL		 2188 .parent = &l4_ck,
2189 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
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PW		 2190 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2191 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2192 .recalc = &followparent_recalc,
046d6b28
TL		 2193};
2194
2195static struct clk i2c2_fck = {
b824efae
TL		 2196 .name = "i2c_fck",
2197 .id = 2,
046d6b28 2198 .parent = &func_12m_ck,
e32744b0
PW		 2199 .flags = CLOCK_IN_OMAP242X,
2200 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2201 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2202 .recalc = &followparent_recalc,
046d6b28
TL		 2203};
2204
2205static struct clk i2chs2_fck = {
e32744b0
PW		 2206 .name = "i2chs_fck",
2207 .id = 2,
046d6b28
TL		 2208 .parent = &func_96m_ck,
2209 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2210 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2211 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2212 .recalc = &followparent_recalc,
046d6b28
TL		 2213};
2214
2215static struct clk i2c1_ick = {
b824efae
TL		 2216 .name = "i2c_ick",
2217 .id = 1,
046d6b28
TL		 2218 .parent = &l4_ck,
2219 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 2220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2221 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2222 .recalc = &followparent_recalc,
046d6b28
TL		 2223};
2224
2225static struct clk i2c1_fck = {
b824efae
TL		 2226 .name = "i2c_fck",
2227 .id = 1,
046d6b28 2228 .parent = &func_12m_ck,
e32744b0
PW		 2229 .flags = CLOCK_IN_OMAP242X,
2230 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2231 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2232 .recalc = &followparent_recalc,
046d6b28
TL		 2233};
2234
2235static struct clk i2chs1_fck = {
e32744b0
PW		 2236 .name = "i2chs_fck",
2237 .id = 1,
046d6b28
TL		 2238 .parent = &func_96m_ck,
2239 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2240 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2241 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2242 .recalc = &followparent_recalc,
2243};
2244
2245static struct clk gpmc_fck = {
2246 .name = "gpmc_fck",
2247 .parent = &core_l3_ck,
2248 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2249 .recalc = &followparent_recalc,
2250};
2251
2252static struct clk sdma_fck = {
2253 .name = "sdma_fck",
2254 .parent = &core_l3_ck,
2255 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2256 .recalc = &followparent_recalc,
2257};
2258
2259static struct clk sdma_ick = {
2260 .name = "sdma_ick",
2261 .parent = &l4_ck,
2262 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2263 .recalc = &followparent_recalc,
046d6b28
TL		 2264};
2265
2266static struct clk vlynq_ick = {
2267 .name = "vlynq_ick",
2268 .parent = &core_l3_ck,
2269 .flags = CLOCK_IN_OMAP242X,
e32744b0
PW		 2270 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2271 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2272 .recalc = &followparent_recalc,
2273};
2274
2275static const struct clksel_rate vlynq_fck_96m_rates[] = {
2276 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2277 { .div = 0 }
2278};
2279
2280static const struct clksel_rate vlynq_fck_core_rates[] = {
2281 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2282 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2283 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2284 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2285 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2286 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2287 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2288 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2289 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2290 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2291 { .div = 0 }
2292};
2293
2294static const struct clksel vlynq_fck_clksel[] = {
2295 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2296 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2297 { .parent = NULL }
046d6b28
TL		 2298};
2299
2300static struct clk vlynq_fck = {
2301 .name = "vlynq_fck",
2302 .parent = &func_96m_ck,
e32744b0
PW		 2303 .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
2304 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2305 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2306 .init = &omap2_init_clksel_parent,
2307 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2308 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2309 .clksel = vlynq_fck_clksel,
2310 .recalc = &omap2_clksel_recalc,
2311 .round_rate = &omap2_clksel_round_rate,
2312 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 2313};
2314
2315static struct clk sdrc_ick = {
2316 .name = "sdrc_ick",
2317 .parent = &l4_ck,
e32744b0
PW		 2318 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2319 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2320 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2321 .recalc = &followparent_recalc,
046d6b28
TL		 2322};
2323
2324static struct clk des_ick = {
2325 .name = "des_ick",
2326 .parent = &l4_ck,
2327 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
e32744b0
PW		 2328 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2329 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2330 .recalc = &followparent_recalc,
046d6b28
TL		 2331};
2332
2333static struct clk sha_ick = {
2334 .name = "sha_ick",
2335 .parent = &l4_ck,
2336 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
e32744b0
PW		 2337 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2338 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2339 .recalc = &followparent_recalc,
046d6b28
TL		 2340};
2341
2342static struct clk rng_ick = {
2343 .name = "rng_ick",
2344 .parent = &l4_ck,
2345 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
e32744b0
PW		 2346 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2347 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2348 .recalc = &followparent_recalc,
046d6b28
TL		 2349};
2350
2351static struct clk aes_ick = {
2352 .name = "aes_ick",
2353 .parent = &l4_ck,
2354 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
e32744b0
PW		 2355 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2356 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2357 .recalc = &followparent_recalc,
046d6b28
TL		 2358};
2359
2360static struct clk pka_ick = {
2361 .name = "pka_ick",
2362 .parent = &l4_ck,
2363 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
e32744b0
PW		 2364 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2365 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2366 .recalc = &followparent_recalc,
046d6b28
TL		 2367};
2368
2369static struct clk usb_fck = {
2370 .name = "usb_fck",
2371 .parent = &func_48m_ck,
2372 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
e32744b0
PW		 2373 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2374 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2375 .recalc = &followparent_recalc,
046d6b28
TL		 2376};
2377
2378static struct clk usbhs_ick = {
2379 .name = "usbhs_ick",
fde0fd49 2380 .parent = &core_l3_ck,
046d6b28 2381 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2382 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2383 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2384 .recalc = &followparent_recalc,
046d6b28
TL		 2385};
2386
2387static struct clk mmchs1_ick = {
e32744b0
PW		 2388 .name = "mmchs_ick",
2389 .id = 1,
046d6b28
TL		 2390 .parent = &l4_ck,
2391 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2392 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2393 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2394 .recalc = &followparent_recalc,
046d6b28
TL		 2395};
2396
2397static struct clk mmchs1_fck = {
e32744b0
PW		 2398 .name = "mmchs_fck",
2399 .id = 1,
046d6b28
TL		 2400 .parent = &func_96m_ck,
2401 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2402 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2403 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2404 .recalc = &followparent_recalc,
046d6b28
TL		 2405};
2406
2407static struct clk mmchs2_ick = {
e32744b0
PW		 2408 .name = "mmchs_ick",
2409 .id = 2,
046d6b28
TL		 2410 .parent = &l4_ck,
2411 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2412 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2413 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2414 .recalc = &followparent_recalc,
046d6b28
TL		 2415};
2416
2417static struct clk mmchs2_fck = {
e32744b0
PW		 2418 .name = "mmchs_fck",
2419 .id = 2,
046d6b28
TL		 2420 .parent = &func_96m_ck,
2421 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2422 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2423 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2424 .recalc = &followparent_recalc,
046d6b28
TL		 2425};
2426
2427static struct clk gpio5_ick = {
2428 .name = "gpio5_ick",
2429 .parent = &l4_ck,
2430 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2431 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2432 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2433 .recalc = &followparent_recalc,
046d6b28
TL		 2434};
2435
2436static struct clk gpio5_fck = {
2437 .name = "gpio5_fck",
2438 .parent = &func_32k_ck,
2439 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2440 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2441 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2442 .recalc = &followparent_recalc,
046d6b28
TL		 2443};
2444
2445static struct clk mdm_intc_ick = {
2446 .name = "mdm_intc_ick",
2447 .parent = &l4_ck,
2448 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2450 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2451 .recalc = &followparent_recalc,
046d6b28
TL		 2452};
2453
2454static struct clk mmchsdb1_fck = {
e32744b0
PW		 2455 .name = "mmchsdb_fck",
2456 .id = 1,
046d6b28
TL		 2457 .parent = &func_32k_ck,
2458 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2459 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2460 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2461 .recalc = &followparent_recalc,
046d6b28
TL		 2462};
2463
2464static struct clk mmchsdb2_fck = {
e32744b0
PW		 2465 .name = "mmchsdb_fck",
2466 .id = 2,
046d6b28
TL		 2467 .parent = &func_32k_ck,
2468 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2469 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2470 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2471 .recalc = &followparent_recalc,
046d6b28 2472};
e32744b0 2473
046d6b28
TL		 2474/*
2475 * This clock is a composite clock which does entire set changes then
2476 * forces a rebalance. It keys on the MPU speed, but it really could
2477 * be any key speed part of a set in the rate table.
2478 *
2479 * to really change a set, you need memory table sets which get changed
2480 * in sram, pre-notifiers & post notifiers, changing the top set, without
2481 * having low level display recalc's won't work... this is why dpm notifiers
2482 * work, isr's off, walk a list of clocks already _off_ and not messing with
2483 * the bus.
2484 *
2485 * This clock should have no parent. It embodies the entire upper level
2486 * active set. A parent will mess up some of the init also.
2487 */
2488static struct clk virt_prcm_set = {
2489 .name = "virt_prcm_set",
2490 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2491 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2492 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
e32744b0 2493 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
046d6b28
TL		 2494 .set_rate = &omap2_select_table_rate,
2495 .round_rate = &omap2_round_to_table_rate,
2496};
e32744b0
PW		 2497
2498static struct clk *onchip_24xx_clks[] __initdata = {
046d6b28
TL		 2499 /* external root sources */
2500 &func_32k_ck,
2501 &osc_ck,
2502 &sys_ck,
2503 &alt_ck,
2504 /* internal analog sources */
2505 &dpll_ck,
2506 &apll96_ck,
2507 &apll54_ck,
2508 /* internal prcm root sources */
2509 &func_54m_ck,
2510 &core_ck,
046d6b28
TL		 2511 &func_96m_ck,
2512 &func_48m_ck,
2513 &func_12m_ck,
2514 &wdt1_osc_ck,
e32744b0 2515 &sys_clkout_src,
046d6b28 2516 &sys_clkout,
e32744b0 2517 &sys_clkout2_src,
046d6b28 2518 &sys_clkout2,
b824efae 2519 &emul_ck,
046d6b28
TL		 2520 /* mpu domain clocks */
2521 &mpu_ck,
2522 /* dsp domain clocks */
046d6b28 2523 &dsp_fck,
e32744b0
PW		 2524 &dsp_irate_ick,
2525 &dsp_ick, /* 242x */
2526 &iva2_1_ick, /* 243x */
2527 &iva1_ifck, /* 242x */
2528 &iva1_mpu_int_ifck, /* 242x */
046d6b28
TL		 2529 /* GFX domain clocks */
2530 &gfx_3d_fck,
2531 &gfx_2d_fck,
2532 &gfx_ick,
2533 /* Modem domain clocks */
2534 &mdm_ick,
2535 &mdm_osc_ck,
2536 /* DSS domain clocks */
2537 &dss_ick,
2538 &dss1_fck,
2539 &dss2_fck,
2540 &dss_54m_fck,
2541 /* L3 domain clocks */
2542 &core_l3_ck,
2543 &ssi_ssr_sst_fck,
2544 &usb_l4_ick,
2545 /* L4 domain clocks */
2546 &l4_ck, /* used as both core_l4 and wu_l4 */
2547 &ssi_l4_ick,
2548 /* virtual meta-group clock */
2549 &virt_prcm_set,
2550 /* general l4 interface ck, multi-parent functional clk */
2551 &gpt1_ick,
2552 &gpt1_fck,
2553 &gpt2_ick,
2554 &gpt2_fck,
2555 &gpt3_ick,
2556 &gpt3_fck,
2557 &gpt4_ick,
2558 &gpt4_fck,
2559 &gpt5_ick,
2560 &gpt5_fck,
2561 &gpt6_ick,
2562 &gpt6_fck,
2563 &gpt7_ick,
2564 &gpt7_fck,
2565 &gpt8_ick,
2566 &gpt8_fck,
2567 &gpt9_ick,
2568 &gpt9_fck,
2569 &gpt10_ick,
2570 &gpt10_fck,
2571 &gpt11_ick,
2572 &gpt11_fck,
2573 &gpt12_ick,
2574 &gpt12_fck,
2575 &mcbsp1_ick,
2576 &mcbsp1_fck,
2577 &mcbsp2_ick,
2578 &mcbsp2_fck,
2579 &mcbsp3_ick,
2580 &mcbsp3_fck,
2581 &mcbsp4_ick,
2582 &mcbsp4_fck,
2583 &mcbsp5_ick,
2584 &mcbsp5_fck,
2585 &mcspi1_ick,
2586 &mcspi1_fck,
2587 &mcspi2_ick,
2588 &mcspi2_fck,
2589 &mcspi3_ick,
2590 &mcspi3_fck,
2591 &uart1_ick,
2592 &uart1_fck,
2593 &uart2_ick,
2594 &uart2_fck,
2595 &uart3_ick,
2596 &uart3_fck,
2597 &gpios_ick,
2598 &gpios_fck,
2599 &mpu_wdt_ick,
2600 &mpu_wdt_fck,
2601 &sync_32k_ick,
2602 &wdt1_ick,
2603 &omapctrl_ick,
2604 &icr_ick,
2605 &cam_fck,
2606 &cam_ick,
2607 &mailboxes_ick,
2608 &wdt4_ick,
2609 &wdt4_fck,
2610 &wdt3_ick,
2611 &wdt3_fck,
2612 &mspro_ick,
2613 &mspro_fck,
2614 &mmc_ick,
2615 &mmc_fck,
2616 &fac_ick,
2617 &fac_fck,
2618 &eac_ick,
2619 &eac_fck,
2620 &hdq_ick,
2621 &hdq_fck,
2622 &i2c1_ick,
2623 &i2c1_fck,
2624 &i2chs1_fck,
2625 &i2c2_ick,
2626 &i2c2_fck,
2627 &i2chs2_fck,
e32744b0
PW		 2628 &gpmc_fck,
2629 &sdma_fck,
2630 &sdma_ick,
046d6b28
TL		 2631 &vlynq_ick,
2632 &vlynq_fck,
2633 &sdrc_ick,
2634 &des_ick,
2635 &sha_ick,
2636 &rng_ick,
2637 &aes_ick,
2638 &pka_ick,
2639 &usb_fck,
2640 &usbhs_ick,
2641 &mmchs1_ick,
2642 &mmchs1_fck,
2643 &mmchs2_ick,
2644 &mmchs2_fck,
2645 &gpio5_ick,
2646 &gpio5_fck,
2647 &mdm_intc_ick,
2648 &mmchsdb1_fck,
2649 &mmchsdb2_fck,
2650};
2651
2652#endif
6b8858a9 2653
kernel source for telekom puls (alcatel/mediatek)