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MX1 fix include
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / clock24xx.h
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046d6b28 1/*
a16e9703 2 * linux/arch/arm/mach-omap2/clock24xx.h
046d6b28 3 *
a16e9703
TL		 4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
046d6b28 6 *
a16e9703
TL		 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
046d6b28
TL		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
6b8858a9
PW		 16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
046d6b28 18
6b8858a9
PW		 19#include "clock.h"
20
21#include "prm.h"
22#include "cm.h"
23#include "prm-regbits-24xx.h"
24#include "cm-regbits-24xx.h"
25#include "sdrc.h"
26
a16e9703
TL		 27static void omap2_table_mpu_recalc(struct clk *clk);
28static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30static void omap2_sys_clk_recalc(struct clk *clk);
31static void omap2_osc_clk_recalc(struct clk *clk);
32static void omap2_sys_clk_recalc(struct clk *clk);
88b8ba90 33static void omap2_dpllcore_recalc(struct clk *clk);
a16e9703
TL		 34static int omap2_clk_fixed_enable(struct clk *clk);
35static void omap2_clk_fixed_disable(struct clk *clk);
36static int omap2_enable_osc_ck(struct clk *clk);
37static void omap2_disable_osc_ck(struct clk *clk);
88b8ba90 38static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
046d6b28 39
046d6b28
TL		 40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
41 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
42 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
43 */
44struct prcm_config {
45 unsigned long xtal_speed; /* crystal rate */
46 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
47 unsigned long mpu_speed; /* speed of MPU */
48 unsigned long cm_clksel_mpu; /* mpu divider */
49 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
50 unsigned long cm_clksel_gfx; /* gfx dividers */
51 unsigned long cm_clksel1_core; /* major subsystem dividers */
52 unsigned long cm_clksel1_pll; /* m,n */
53 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
54 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
55 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
56 unsigned char flags;
57};
58
046d6b28
TL		 59/*
60 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
61 * These configurations are characterized by voltage and speed for clocks.
62 * The device is only validated for certain combinations. One way to express
63 * these combinations is via the 'ratio's' which the clocks operate with
64 * respect to each other. These ratio sets are for a given voltage/DPLL
65 * setting. All configurations can be described by a DPLL setting and a ratio
66 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
67 *
68 * 2430 differs from 2420 in that there are no more phase synchronizers used.
69 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
70 * 2430 (iva2.1, NOdsp, mdm)
71 */
72
73/* Core fields for cm_clksel, not ratio governed */
74#define RX_CLKSEL_DSS1 (0x10 << 8)
75#define RX_CLKSEL_DSS2 (0x0 << 13)
76#define RX_CLKSEL_SSI (0x5 << 20)
77
78/*-------------------------------------------------------------------------
79 * Voltage/DPLL ratios
80 *-------------------------------------------------------------------------*/
81
82/* 2430 Ratio's, 2430-Ratio Config 1 */
83#define R1_CLKSEL_L3 (4 << 0)
84#define R1_CLKSEL_L4 (2 << 5)
85#define R1_CLKSEL_USB (4 << 25)
86#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
87 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
88 R1_CLKSEL_L4 | R1_CLKSEL_L3
89#define R1_CLKSEL_MPU (2 << 0)
90#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
91#define R1_CLKSEL_DSP (2 << 0)
92#define R1_CLKSEL_DSP_IF (2 << 5)
93#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
94#define R1_CLKSEL_GFX (2 << 0)
95#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
96#define R1_CLKSEL_MDM (4 << 0)
97#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
98
99/* 2430-Ratio Config 2 */
100#define R2_CLKSEL_L3 (6 << 0)
101#define R2_CLKSEL_L4 (2 << 5)
102#define R2_CLKSEL_USB (2 << 25)
103#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
104 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
105 R2_CLKSEL_L4 | R2_CLKSEL_L3
106#define R2_CLKSEL_MPU (2 << 0)
107#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
108#define R2_CLKSEL_DSP (2 << 0)
109#define R2_CLKSEL_DSP_IF (3 << 5)
110#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
111#define R2_CLKSEL_GFX (2 << 0)
112#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
113#define R2_CLKSEL_MDM (6 << 0)
114#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
115
116/* 2430-Ratio Bootm (BYPASS) */
117#define RB_CLKSEL_L3 (1 << 0)
118#define RB_CLKSEL_L4 (1 << 5)
119#define RB_CLKSEL_USB (1 << 25)
120#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
121 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
122 RB_CLKSEL_L4 | RB_CLKSEL_L3
123#define RB_CLKSEL_MPU (1 << 0)
124#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
125#define RB_CLKSEL_DSP (1 << 0)
126#define RB_CLKSEL_DSP_IF (1 << 5)
127#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
128#define RB_CLKSEL_GFX (1 << 0)
129#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
130#define RB_CLKSEL_MDM (1 << 0)
131#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
132
133/* 2420 Ratio Equivalents */
134#define RXX_CLKSEL_VLYNQ (0x12 << 15)
135#define RXX_CLKSEL_SSI (0x8 << 20)
136
137/* 2420-PRCM III 532MHz core */
138#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
139#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
140#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
141#define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
142 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
143 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
144 RIII_CLKSEL_L3
145#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
146#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
147#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
148#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
149#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
150#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
151#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
152#define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
153 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
154 RIII_CLKSEL_DSP
155#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
156#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
157
158/* 2420-PRCM II 600MHz core */
159#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
160#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
161#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
162#define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
163 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
164 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
165 RII_CLKSEL_L4 | RII_CLKSEL_L3
166#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
167#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
168#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
169#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
170#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
6b8858a9 171#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
046d6b28
TL		 172#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
173#define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
174 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
175 RII_CLKSEL_DSP
176#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
177#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
178
6b8858a9
PW		 179/* 2420-PRCM I 660MHz core */
180#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
181#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
182#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
183#define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
184 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
185 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
186 RI_CLKSEL_L4 | RI_CLKSEL_L3
187#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
188#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
189#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
190#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
191#define RI_SYNC_DSP (1 << 7) /* Activate sync */
192#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
193#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
194#define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
195 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
196 RI_CLKSEL_DSP
197#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
198#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
199
046d6b28
TL		 200/* 2420-PRCM VII (boot) */
201#define RVII_CLKSEL_L3 (1 << 0)
202#define RVII_CLKSEL_L4 (1 << 5)
203#define RVII_CLKSEL_DSS1 (1 << 8)
204#define RVII_CLKSEL_DSS2 (0 << 13)
205#define RVII_CLKSEL_VLYNQ (1 << 15)
206#define RVII_CLKSEL_SSI (1 << 20)
207#define RVII_CLKSEL_USB (1 << 25)
208
209#define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
210 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
211 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
212
213#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
214#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
215
216#define RVII_CLKSEL_DSP (1 << 0)
217#define RVII_CLKSEL_DSP_IF (1 << 5)
218#define RVII_SYNC_DSP (0 << 7)
219#define RVII_CLKSEL_IVA (1 << 8)
220#define RVII_SYNC_IVA (0 << 13)
221#define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
222 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
223
224#define RVII_CLKSEL_GFX (1 << 0)
225#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
226
227/*-------------------------------------------------------------------------
228 * 2430 Target modes: Along with each configuration the CPU has several
229 * modes which goes along with them. Modes mainly are the addition of
230 * describe DPLL combinations to go along with a ratio.
231 *-------------------------------------------------------------------------*/
232
233/* Hardware governed */
234#define MX_48M_SRC (0 << 3)
235#define MX_54M_SRC (0 << 5)
236#define MX_APLLS_CLIKIN_12 (3 << 23)
237#define MX_APLLS_CLIKIN_13 (2 << 23)
238#define MX_APLLS_CLIKIN_19_2 (0 << 23)
239
240/*
241 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
046d6b28
TL		 242 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
243 */
244#define M5A_DPLL_MULT_12 (133 << 12)
245#define M5A_DPLL_DIV_12 (5 << 8)
246#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
247 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
248 MX_APLLS_CLIKIN_12
6b8858a9
PW		 249#define M5A_DPLL_MULT_13 (61 << 12)
250#define M5A_DPLL_DIV_13 (2 << 8)
046d6b28
TL		 251#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
252 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
253 MX_APLLS_CLIKIN_13
6b8858a9
PW		 254#define M5A_DPLL_MULT_19 (55 << 12)
255#define M5A_DPLL_DIV_19 (3 << 8)
046d6b28
TL		 256#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
257 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
258 MX_APLLS_CLIKIN_19_2
259/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
260#define M5B_DPLL_MULT_12 (50 << 12)
261#define M5B_DPLL_DIV_12 (2 << 8)
262#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
263 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
264 MX_APLLS_CLIKIN_12
265#define M5B_DPLL_MULT_13 (200 << 12)
266#define M5B_DPLL_DIV_13 (12 << 8)
267
268#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
269 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
270 MX_APLLS_CLIKIN_13
271#define M5B_DPLL_MULT_19 (125 << 12)
272#define M5B_DPLL_DIV_19 (31 << 8)
273#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
274 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
275 MX_APLLS_CLIKIN_19_2
276/*
6b8858a9
PW		 277 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
278 */
279#define M4_DPLL_MULT_12 (133 << 12)
280#define M4_DPLL_DIV_12 (3 << 8)
281#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
282 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
283 MX_APLLS_CLIKIN_12
284
285#define M4_DPLL_MULT_13 (399 << 12)
286#define M4_DPLL_DIV_13 (12 << 8)
287#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
288 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
289 MX_APLLS_CLIKIN_13
290
291#define M4_DPLL_MULT_19 (145 << 12)
292#define M4_DPLL_DIV_19 (6 << 8)
293#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
294 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
295 MX_APLLS_CLIKIN_19_2
296
297/*
046d6b28
TL		 298 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
299 */
300#define M3_DPLL_MULT_12 (55 << 12)
301#define M3_DPLL_DIV_12 (1 << 8)
302#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
303 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
304 MX_APLLS_CLIKIN_12
6b8858a9
PW		 305#define M3_DPLL_MULT_13 (76 << 12)
306#define M3_DPLL_DIV_13 (2 << 8)
046d6b28
TL		 307#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
308 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
309 MX_APLLS_CLIKIN_13
6b8858a9
PW		 310#define M3_DPLL_MULT_19 (17 << 12)
311#define M3_DPLL_DIV_19 (0 << 8)
046d6b28
TL		 312#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
313 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
314 MX_APLLS_CLIKIN_19_2
6b8858a9
PW		 315
316/*
317 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
318 */
319#define M2_DPLL_MULT_12 (55 << 12)
320#define M2_DPLL_DIV_12 (1 << 8)
321#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
322 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
323 MX_APLLS_CLIKIN_12
324
325/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
326 * relock time issue */
327/* Core frequency changed from 330/165 to 329/164 MHz*/
328#define M2_DPLL_MULT_13 (76 << 12)
329#define M2_DPLL_DIV_13 (2 << 8)
330#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
331 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
332 MX_APLLS_CLIKIN_13
333
334#define M2_DPLL_MULT_19 (17 << 12)
335#define M2_DPLL_DIV_19 (0 << 8)
336#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
337 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
338 MX_APLLS_CLIKIN_19_2
339
046d6b28
TL		 340/* boot (boot) */
341#define MB_DPLL_MULT (1 << 12)
342#define MB_DPLL_DIV (0 << 8)
343#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
344 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
345
346#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
347 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
348
349#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
350 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
351
352/*
353 * 2430 - chassis (sedna)
354 * 165 (ratio1) same as above #2
355 * 150 (ratio1)
356 * 133 (ratio2) same as above #4
357 * 110 (ratio2) same as above #3
358 * 104 (ratio2)
359 * boot (boot)
360 */
361
6b8858a9
PW		 362/* PRCM I target DPLL = 2*330MHz = 660MHz */
363#define MI_DPLL_MULT_12 (55 << 12)
364#define MI_DPLL_DIV_12 (1 << 8)
365#define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
366 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
367 MX_APLLS_CLIKIN_12
368
046d6b28
TL		 369/*
370 * 2420 Equivalent - mode registers
371 * PRCM II , target DPLL = 2*300MHz = 600MHz
372 */
373#define MII_DPLL_MULT_12 (50 << 12)
374#define MII_DPLL_DIV_12 (1 << 8)
375#define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
376 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
377 MX_APLLS_CLIKIN_12
378#define MII_DPLL_MULT_13 (300 << 12)
379#define MII_DPLL_DIV_13 (12 << 8)
380#define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
381 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
382 MX_APLLS_CLIKIN_13
383
384/* PRCM III target DPLL = 2*266 = 532MHz*/
385#define MIII_DPLL_MULT_12 (133 << 12)
386#define MIII_DPLL_DIV_12 (5 << 8)
387#define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
388 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
389 MX_APLLS_CLIKIN_12
390#define MIII_DPLL_MULT_13 (266 << 12)
391#define MIII_DPLL_DIV_13 (12 << 8)
392#define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
393 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
394 MX_APLLS_CLIKIN_13
395
396/* PRCM VII (boot bypass) */
397#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
398#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
399
400/* High and low operation value */
401#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
402#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
403
046d6b28
TL		 404/* MPU speed defines */
405#define S12M 12000000
406#define S13M 13000000
407#define S19M 19200000
408#define S26M 26000000
409#define S100M 100000000
410#define S133M 133000000
411#define S150M 150000000
6b8858a9 412#define S164M 164000000
046d6b28 413#define S165M 165000000
6b8858a9 414#define S199M 199000000
046d6b28
TL		 415#define S200M 200000000
416#define S266M 266000000
417#define S300M 300000000
6b8858a9 418#define S329M 329000000
046d6b28 419#define S330M 330000000
6b8858a9 420#define S399M 399000000
046d6b28
TL		 421#define S400M 400000000
422#define S532M 532000000
423#define S600M 600000000
6b8858a9 424#define S658M 658000000
046d6b28 425#define S660M 660000000
6b8858a9 426#define S798M 798000000
046d6b28
TL		 427
428/*-------------------------------------------------------------------------
429 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
430 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
431 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
432 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
433 *
434 * Filling in table based on H4 boards and 2430-SDPs variants available.
435 * There are quite a few more rates combinations which could be defined.
436 *
6cbdc8c5 437 * When multiple values are defined the start up will try and choose the
046d6b28
TL		 438 * fastest one. If a 'fast' value is defined, then automatically, the /2
439 * one should be included as it can be used. Generally having more that
440 * one fast set does not make sense, as static timings need to be changed
441 * to change the set. The exception is the bypass setting which is
442 * availble for low power bypass.
443 *
444 * Note: This table needs to be sorted, fastest to slowest.
445 *-------------------------------------------------------------------------*/
446static struct prcm_config rate_table[] = {
6b8858a9
PW		 447 /* PRCM I - FAST */
448 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
449 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
450 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
451 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
452 RATE_IN_242X},
453
046d6b28
TL		 454 /* PRCM II - FAST */
455 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
456 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
457 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
6b8858a9 458 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 459 RATE_IN_242X},
460
461 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
462 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
463 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
6b8858a9 464 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 465 RATE_IN_242X},
466
467 /* PRCM III - FAST */
468 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
469 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
470 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
6b8858a9 471 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 472 RATE_IN_242X},
473
474 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
475 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
476 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
6b8858a9 477 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 478 RATE_IN_242X},
479
480 /* PRCM II - SLOW */
481 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
482 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
483 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
6b8858a9 484 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 485 RATE_IN_242X},
486
487 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
488 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
489 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
6b8858a9 490 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 491 RATE_IN_242X},
492
493 /* PRCM III - SLOW */
494 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
495 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
496 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
6b8858a9 497 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 498 RATE_IN_242X},
499
500 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
501 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
502 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
6b8858a9 503 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 504 RATE_IN_242X},
505
506 /* PRCM-VII (boot-bypass) */
507 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
508 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
509 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
6b8858a9 510 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
046d6b28
TL		 511 RATE_IN_242X},
512
513 /* PRCM-VII (boot-bypass) */
514 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
515 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
516 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
6b8858a9 517 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
046d6b28
TL		 518 RATE_IN_242X},
519
6b8858a9
PW		 520 /* PRCM #4 - ratio2 (ES2.1) - FAST */
521 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
046d6b28 522 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
6b8858a9 523 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
046d6b28 524 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
6b8858a9
PW		 525 SDRC_RFR_CTRL_133MHz,
526 RATE_IN_243X},
527
528 /* PRCM #2 - ratio1 (ES2) - FAST */
529 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
530 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
531 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
532 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
533 SDRC_RFR_CTRL_165MHz,
046d6b28
TL		 534 RATE_IN_243X},
535
536 /* PRCM #5a - ratio1 - FAST */
537 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
538 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
539 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
540 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
6b8858a9 541 SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 542 RATE_IN_243X},
543
544 /* PRCM #5b - ratio1 - FAST */
545 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
546 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
547 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
548 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
6b8858a9 549 SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 550 RATE_IN_243X},
551
6b8858a9
PW		 552 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
553 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
046d6b28 554 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
6b8858a9 555 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
046d6b28 556 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
6b8858a9
PW		 557 SDRC_RFR_CTRL_133MHz,
558 RATE_IN_243X},
559
560 /* PRCM #2 - ratio1 (ES2) - SLOW */
561 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
562 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
563 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
564 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
565 SDRC_RFR_CTRL_165MHz,
046d6b28
TL		 566 RATE_IN_243X},
567
568 /* PRCM #5a - ratio1 - SLOW */
569 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
570 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
571 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
572 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
6b8858a9 573 SDRC_RFR_CTRL_133MHz,
046d6b28
TL		 574 RATE_IN_243X},
575
576 /* PRCM #5b - ratio1 - SLOW*/
577 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
578 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
579 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
580 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
6b8858a9 581 SDRC_RFR_CTRL_100MHz,
046d6b28
TL		 582 RATE_IN_243X},
583
584 /* PRCM-boot/bypass */
585 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
586 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
587 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
588 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
6b8858a9 589 SDRC_RFR_CTRL_BYPASS,
046d6b28
TL		 590 RATE_IN_243X},
591
592 /* PRCM-boot/bypass */
593 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
594 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
595 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
596 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
6b8858a9 597 SDRC_RFR_CTRL_BYPASS,
046d6b28
TL		 598 RATE_IN_243X},
599
600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
601};
602
603/*-------------------------------------------------------------------------
604 * 24xx clock tree.
605 *
606 * NOTE:In many cases here we are assigning a 'default' parent. In many
607 * cases the parent is selectable. The get/set parent calls will also
608 * switch sources.
609 *
610 * Many some clocks say always_enabled, but they can be auto idled for
611 * power savings. They will always be available upon clock request.
612 *
613 * Several sources are given initial rates which may be wrong, this will
614 * be fixed up in the init func.
615 *
616 * Things are broadly separated below by clock domains. It is
617 * noteworthy that most periferals have dependencies on multiple clock
618 * domains. Many get their interface clocks from the L4 domain, but get
619 * functional clocks from fixed sources or other core domain derived
620 * clocks.
621 *-------------------------------------------------------------------------*/
622
623/* Base external input clocks */
624static struct clk func_32k_ck = {
625 .name = "func_32k_ck",
626 .rate = 32000,
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
d1b03f61 629 .clkdm_name = "wkup_clkdm",
e32744b0 630 .recalc = &propagate_rate,
046d6b28 631};
e32744b0 632
046d6b28
TL		 633/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
634static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
635 .name = "osc_ck",
046d6b28 636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 637 RATE_PROPAGATES,
d1b03f61 638 .clkdm_name = "wkup_clkdm",
e32744b0
PW		 639 .enable = &omap2_enable_osc_ck,
640 .disable = &omap2_disable_osc_ck,
641 .recalc = &omap2_osc_clk_recalc,
046d6b28
TL		 642};
643
d1b03f61 644/* Without modem likely 12MHz, with modem likely 13MHz */
046d6b28
TL		 645static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
646 .name = "sys_ck", /* ~ ref_clk also */
647 .parent = &osc_ck,
046d6b28 648 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 649 ALWAYS_ENABLED | RATE_PROPAGATES,
d1b03f61 650 .clkdm_name = "wkup_clkdm",
046d6b28
TL		 651 .recalc = &omap2_sys_clk_recalc,
652};
e32744b0 653
046d6b28
TL		 654static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
655 .name = "alt_ck",
656 .rate = 54000000,
657 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
658 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
d1b03f61 659 .clkdm_name = "wkup_clkdm",
e32744b0 660 .recalc = &propagate_rate,
046d6b28 661};
e32744b0 662
046d6b28
TL		 663/*
664 * Analog domain root source clocks
665 */
666
667/* dpll_ck, is broken out in to special cases through clksel */
6b8858a9
PW		 668/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
669 * deal with this
670 */
671
88b8ba90 672static struct dpll_data dpll_dd = {
6b8858a9
PW		 673 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
674 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
675 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
88b8ba90
PW		 676 .max_multiplier = 1024,
677 .max_divider = 16,
678 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
6b8858a9
PW		 679};
680
88b8ba90
PW		 681/*
682 * XXX Cannot add round_rate here yet, as this is still a composite clock,
683 * not just a DPLL
684 */
046d6b28
TL		 685static struct clk dpll_ck = {
686 .name = "dpll_ck",
687 .parent = &sys_ck, /* Can be func_32k also */
6b8858a9 688 .dpll_data = &dpll_dd,
046d6b28 689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
6b8858a9 690 RATE_PROPAGATES | ALWAYS_ENABLED,
d1b03f61 691 .clkdm_name = "wkup_clkdm",
88b8ba90
PW		 692 .recalc = &omap2_dpllcore_recalc,
693 .set_rate = &omap2_reprogram_dpllcore,
046d6b28
TL		 694};
695
696static struct clk apll96_ck = {
697 .name = "apll96_ck",
698 .parent = &sys_ck,
699 .rate = 96000000,
6b8858a9
PW		 700 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
701 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
d1b03f61 702 .clkdm_name = "wkup_clkdm",
6b8858a9
PW		 703 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
704 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
705 .enable = &omap2_clk_fixed_enable,
706 .disable = &omap2_clk_fixed_disable,
707 .recalc = &propagate_rate,
046d6b28
TL		 708};
709
710static struct clk apll54_ck = {
711 .name = "apll54_ck",
712 .parent = &sys_ck,
713 .rate = 54000000,
714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
6b8858a9 715 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
d1b03f61 716 .clkdm_name = "wkup_clkdm",
6b8858a9
PW		 717 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
718 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
719 .enable = &omap2_clk_fixed_enable,
720 .disable = &omap2_clk_fixed_disable,
721 .recalc = &propagate_rate,
046d6b28
TL		 722};
723
724/*
725 * PRCM digital base sources
726 */
e32744b0
PW		 727
728/* func_54m_ck */
729
730static const struct clksel_rate func_54m_apll54_rates[] = {
731 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
732 { .div = 0 },
733};
734
735static const struct clksel_rate func_54m_alt_rates[] = {
736 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
737 { .div = 0 },
738};
739
740static const struct clksel func_54m_clksel[] = {
741 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
742 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
743 { .parent = NULL },
744};
745
046d6b28
TL		 746static struct clk func_54m_ck = {
747 .name = "func_54m_ck",
748 .parent = &apll54_ck, /* can also be alt_clk */
046d6b28 749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 750 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
d1b03f61 751 .clkdm_name = "wkup_clkdm",
e32744b0
PW		 752 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
754 .clksel_mask = OMAP24XX_54M_SOURCE,
755 .clksel = func_54m_clksel,
756 .recalc = &omap2_clksel_recalc,
046d6b28 757};
e32744b0 758
046d6b28
TL		 759static struct clk core_ck = {
760 .name = "core_ck",
761 .parent = &dpll_ck, /* can also be 32k */
762 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
763 ALWAYS_ENABLED | RATE_PROPAGATES,
d1b03f61 764 .clkdm_name = "wkup_clkdm",
6b8858a9 765 .recalc = &followparent_recalc,
046d6b28 766};
e32744b0
PW		 767
768/* func_96m_ck */
769static const struct clksel_rate func_96m_apll96_rates[] = {
770 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
771 { .div = 0 },
046d6b28
TL		 772};
773
e32744b0
PW		 774static const struct clksel_rate func_96m_alt_rates[] = {
775 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
776 { .div = 0 },
777};
778
779static const struct clksel func_96m_clksel[] = {
780 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
781 { .parent = &alt_ck, .rates = func_96m_alt_rates },
782 { .parent = NULL }
783};
784
785/* The parent of this clock is not selectable on 2420. */
046d6b28
TL		 786static struct clk func_96m_ck = {
787 .name = "func_96m_ck",
788 .parent = &apll96_ck,
046d6b28 789 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 790 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
d1b03f61 791 .clkdm_name = "wkup_clkdm",
e32744b0
PW		 792 .init = &omap2_init_clksel_parent,
793 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
794 .clksel_mask = OMAP2430_96M_SOURCE,
795 .clksel = func_96m_clksel,
796 .recalc = &omap2_clksel_recalc,
797 .round_rate = &omap2_clksel_round_rate,
798 .set_rate = &omap2_clksel_set_rate
799};
800
801/* func_48m_ck */
802
803static const struct clksel_rate func_48m_apll96_rates[] = {
804 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
805 { .div = 0 },
806};
807
808static const struct clksel_rate func_48m_alt_rates[] = {
809 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
810 { .div = 0 },
811};
812
813static const struct clksel func_48m_clksel[] = {
814 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
815 { .parent = &alt_ck, .rates = func_48m_alt_rates },
816 { .parent = NULL }
046d6b28
TL		 817};
818
819static struct clk func_48m_ck = {
820 .name = "func_48m_ck",
821 .parent = &apll96_ck, /* 96M or Alt */
046d6b28 822 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 823 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
d1b03f61 824 .clkdm_name = "wkup_clkdm",
e32744b0
PW		 825 .init = &omap2_init_clksel_parent,
826 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
827 .clksel_mask = OMAP24XX_48M_SOURCE,
828 .clksel = func_48m_clksel,
829 .recalc = &omap2_clksel_recalc,
830 .round_rate = &omap2_clksel_round_rate,
831 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 832};
833
834static struct clk func_12m_ck = {
835 .name = "func_12m_ck",
836 .parent = &func_48m_ck,
e32744b0 837 .fixed_div = 4,
046d6b28 838 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 839 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
d1b03f61 840 .clkdm_name = "wkup_clkdm",
e32744b0 841 .recalc = &omap2_fixed_divisor_recalc,
046d6b28
TL		 842};
843
844/* Secure timer, only available in secure mode */
845static struct clk wdt1_osc_ck = {
846 .name = "ck_wdt1_osc",
847 .parent = &osc_ck,
848 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 849 .recalc = &followparent_recalc,
850};
851
852/*
853 * The common_clkout* clksel_rate structs are common to
854 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
855 * sys_clkout2_* are 2420-only, so the
856 * clksel_rate flags fields are inaccurate for those clocks. This is
857 * harmless since access to those clocks are gated by the struct clk
858 * flags fields, which mark them as 2420-only.
859 */
860static const struct clksel_rate common_clkout_src_core_rates[] = {
861 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
862 { .div = 0 }
863};
864
865static const struct clksel_rate common_clkout_src_sys_rates[] = {
866 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
867 { .div = 0 }
868};
869
870static const struct clksel_rate common_clkout_src_96m_rates[] = {
871 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
872 { .div = 0 }
873};
874
875static const struct clksel_rate common_clkout_src_54m_rates[] = {
876 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
877 { .div = 0 }
878};
879
880static const struct clksel common_clkout_src_clksel[] = {
881 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
882 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
883 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
884 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
885 { .parent = NULL }
886};
887
888static struct clk sys_clkout_src = {
889 .name = "sys_clkout_src",
890 .parent = &func_54m_ck,
891 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
892 RATE_PROPAGATES,
d1b03f61 893 .clkdm_name = "wkup_clkdm",
e32744b0
PW		 894 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
895 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
896 .init = &omap2_init_clksel_parent,
897 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
898 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
899 .clksel = common_clkout_src_clksel,
900 .recalc = &omap2_clksel_recalc,
901 .round_rate = &omap2_clksel_round_rate,
902 .set_rate = &omap2_clksel_set_rate
903};
904
905static const struct clksel_rate common_clkout_rates[] = {
906 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
907 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
908 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
909 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
910 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
911 { .div = 0 },
912};
913
914static const struct clksel sys_clkout_clksel[] = {
915 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
916 { .parent = NULL }
046d6b28
TL		 917};
918
919static struct clk sys_clkout = {
920 .name = "sys_clkout",
e32744b0 921 .parent = &sys_clkout_src,
046d6b28 922 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 923 PARENT_CONTROLS_CLOCK,
d1b03f61 924 .clkdm_name = "wkup_clkdm",
e32744b0
PW		 925 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
926 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
927 .clksel = sys_clkout_clksel,
928 .recalc = &omap2_clksel_recalc,
929 .round_rate = &omap2_clksel_round_rate,
930 .set_rate = &omap2_clksel_set_rate
931};
932
933/* In 2430, new in 2420 ES2 */
934static struct clk sys_clkout2_src = {
935 .name = "sys_clkout2_src",
936 .parent = &func_54m_ck,
937 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
d1b03f61 938 .clkdm_name = "wkup_clkdm",
e32744b0
PW		 939 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
940 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
941 .init = &omap2_init_clksel_parent,
942 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
943 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
944 .clksel = common_clkout_src_clksel,
046d6b28 945 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 946 .round_rate = &omap2_clksel_round_rate,
947 .set_rate = &omap2_clksel_set_rate
948};
949
950static const struct clksel sys_clkout2_clksel[] = {
951 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
952 { .parent = NULL }
046d6b28
TL		 953};
954
955/* In 2430, new in 2420 ES2 */
956static struct clk sys_clkout2 = {
957 .name = "sys_clkout2",
e32744b0
PW		 958 .parent = &sys_clkout2_src,
959 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
d1b03f61 960 .clkdm_name = "wkup_clkdm",
e32744b0
PW		 961 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
962 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
963 .clksel = sys_clkout2_clksel,
046d6b28 964 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 965 .round_rate = &omap2_clksel_round_rate,
966 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 967};
968
b824efae
TL		 969static struct clk emul_ck = {
970 .name = "emul_ck",
971 .parent = &func_54m_ck,
972 .flags = CLOCK_IN_OMAP242X,
d1b03f61 973 .clkdm_name = "wkup_clkdm",
e32744b0
PW		 974 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
975 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
976 .recalc = &followparent_recalc,
b824efae
TL		 977
978};
e32744b0 979
046d6b28
TL		 980/*
981 * MPU clock domain
982 * Clocks:
983 * MPU_FCLK, MPU_ICLK
984 * INT_M_FCLK, INT_M_I_CLK
985 *
986 * - Individual clocks are hardware managed.
987 * - Base divider comes from: CM_CLKSEL_MPU
988 *
989 */
e32744b0
PW		 990static const struct clksel_rate mpu_core_rates[] = {
991 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
992 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
993 { .div = 4, .val = 4, .flags = RATE_IN_242X },
994 { .div = 6, .val = 6, .flags = RATE_IN_242X },
995 { .div = 8, .val = 8, .flags = RATE_IN_242X },
996 { .div = 0 },
997};
998
999static const struct clksel mpu_clksel[] = {
1000 { .parent = &core_ck, .rates = mpu_core_rates },
1001 { .parent = NULL }
1002};
1003
046d6b28
TL		 1004static struct clk mpu_ck = { /* Control cpu */
1005 .name = "mpu_ck",
1006 .parent = &core_ck,
6b8858a9
PW		 1007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1008 ALWAYS_ENABLED | DELAYED_APP |
046d6b28 1009 CONFIG_PARTICIPANT | RATE_PROPAGATES,
d1b03f61 1010 .clkdm_name = "mpu_clkdm",
6b8858a9
PW		 1011 .init = &omap2_init_clksel_parent,
1012 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1013 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
e32744b0 1014 .clksel = mpu_clksel,
046d6b28 1015 .recalc = &omap2_clksel_recalc,
d1b03f61 1016 .round_rate = &omap2_clksel_round_rate,
6b8858a9 1017 .set_rate = &omap2_clksel_set_rate
046d6b28 1018};
e32744b0 1019
046d6b28
TL		 1020/*
1021 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1022 * Clocks:
e32744b0 1023 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
046d6b28 1024 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
e32744b0
PW		 1025 *
1026 * Won't be too specific here. The core clock comes into this block
1027 * it is divided then tee'ed. One branch goes directly to xyz enable
1028 * controls. The other branch gets further divided by 2 then possibly
1029 * routed into a synchronizer and out of clocks abc.
046d6b28 1030 */
e32744b0
PW		 1031static const struct clksel_rate dsp_fck_core_rates[] = {
1032 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1033 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1034 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1035 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1036 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1037 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1038 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1039 { .div = 0 },
1040};
1041
1042static const struct clksel dsp_fck_clksel[] = {
1043 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1044 { .parent = NULL }
1045};
1046
1047static struct clk dsp_fck = {
1048 .name = "dsp_fck",
046d6b28 1049 .parent = &core_ck,
e32744b0
PW		 1050 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1051 CONFIG_PARTICIPANT | RATE_PROPAGATES,
d1b03f61 1052 .clkdm_name = "dsp_clkdm",
e32744b0
PW		 1053 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1054 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1055 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1056 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1057 .clksel = dsp_fck_clksel,
046d6b28 1058 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1059 .round_rate = &omap2_clksel_round_rate,
1060 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1061};
1062
e32744b0
PW		 1063/* DSP interface clock */
1064static const struct clksel_rate dsp_irate_ick_rates[] = {
1065 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1066 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1067 { .div = 3, .val = 3, .flags = RATE_IN_243X },
1068 { .div = 0 },
1069};
1070
1071static const struct clksel dsp_irate_ick_clksel[] = {
1072 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1073 { .parent = NULL }
046d6b28
TL		 1074};
1075
d1b03f61 1076/* This clock does not exist as such in the TRM. */
e32744b0
PW		 1077static struct clk dsp_irate_ick = {
1078 .name = "dsp_irate_ick",
1079 .parent = &dsp_fck,
1080 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1081 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1082 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1083 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1084 .clksel = dsp_irate_ick_clksel,
046d6b28 1085 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1086 .round_rate = &omap2_clksel_round_rate,
1087 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1088};
1089
e32744b0 1090/* 2420 only */
046d6b28
TL		 1091static struct clk dsp_ick = {
1092 .name = "dsp_ick", /* apparently ipi and isp */
e32744b0
PW		 1093 .parent = &dsp_irate_ick,
1094 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1095 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1096 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1097};
1098
1099/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1100static struct clk iva2_1_ick = {
1101 .name = "iva2_1_ick",
1102 .parent = &dsp_irate_ick,
1103 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1104 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1105 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
046d6b28
TL		 1106};
1107
d1b03f61
PW		 1108/*
1109 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1110 * the C54x, but which is contained in the DSP powerdomain. Does not
1111 * exist on later OMAPs.
1112 */
046d6b28
TL		 1113static struct clk iva1_ifck = {
1114 .name = "iva1_ifck",
1115 .parent = &core_ck,
e32744b0
PW		 1116 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1117 RATE_PROPAGATES | DELAYED_APP,
d1b03f61 1118 .clkdm_name = "iva1_clkdm",
e32744b0
PW		 1119 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1120 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1121 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1122 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1123 .clksel = dsp_fck_clksel,
046d6b28 1124 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1125 .round_rate = &omap2_clksel_round_rate,
1126 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1127};
1128
1129/* IVA1 mpu/int/i/f clocks are /2 of parent */
1130static struct clk iva1_mpu_int_ifck = {
1131 .name = "iva1_mpu_int_ifck",
1132 .parent = &iva1_ifck,
e32744b0 1133 .flags = CLOCK_IN_OMAP242X,
d1b03f61 1134 .clkdm_name = "iva1_clkdm",
e32744b0
PW		 1135 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1136 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1137 .fixed_div = 2,
1138 .recalc = &omap2_fixed_divisor_recalc,
046d6b28
TL		 1139};
1140
1141/*
1142 * L3 clock domain
1143 * L3 clocks are used for both interface and functional clocks to
1144 * multiple entities. Some of these clocks are completely managed
1145 * by hardware, and some others allow software control. Hardware
1146 * managed ones general are based on directly CLK_REQ signals and
1147 * various auto idle settings. The functional spec sets many of these
1148 * as 'tie-high' for their enables.
1149 *
1150 * I-CLOCKS:
1151 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1152 * CAM, HS-USB.
1153 * F-CLOCK
1154 * SSI.
1155 *
1156 * GPMC memories and SDRC have timing and clock sensitive registers which
1157 * may very well need notification when the clock changes. Currently for low
1158 * operating points, these are taken care of in sleep.S.
1159 */
e32744b0
PW		 1160static const struct clksel_rate core_l3_core_rates[] = {
1161 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1162 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1163 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1164 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1165 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1166 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1167 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1168 { .div = 0 }
1169};
1170
1171static const struct clksel core_l3_clksel[] = {
1172 { .parent = &core_ck, .rates = core_l3_core_rates },
1173 { .parent = NULL }
1174};
1175
046d6b28
TL		 1176static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1177 .name = "core_l3_ck",
1178 .parent = &core_ck,
1179 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0
PW		 1180 ALWAYS_ENABLED | DELAYED_APP |
1181 CONFIG_PARTICIPANT | RATE_PROPAGATES,
d1b03f61 1182 .clkdm_name = "core_l3_clkdm",
e32744b0
PW		 1183 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1184 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1185 .clksel = core_l3_clksel,
046d6b28 1186 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1187 .round_rate = &omap2_clksel_round_rate,
1188 .set_rate = &omap2_clksel_set_rate
1189};
1190
1191/* usb_l4_ick */
1192static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1193 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1194 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1195 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1196 { .div = 0 }
1197};
1198
1199static const struct clksel usb_l4_ick_clksel[] = {
1200 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1201 { .parent = NULL },
046d6b28
TL		 1202};
1203
d1b03f61 1204/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
046d6b28
TL		 1205static struct clk usb_l4_ick = { /* FS-USB interface clock */
1206 .name = "usb_l4_ick",
fde0fd49 1207 .parent = &core_l3_ck,
046d6b28 1208 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 1209 DELAYED_APP | CONFIG_PARTICIPANT,
d1b03f61 1210 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1212 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1213 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1214 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1215 .clksel = usb_l4_ick_clksel,
046d6b28 1216 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1217 .round_rate = &omap2_clksel_round_rate,
1218 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1219};
1220
d1b03f61
PW		 1221/*
1222 * L4 clock management domain
1223 *
1224 * This domain contains lots of interface clocks from the L4 interface, some
1225 * functional clocks. Fixed APLL functional source clocks are managed in
1226 * this domain.
1227 */
1228static const struct clksel_rate l4_core_l3_rates[] = {
1229 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1230 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1231 { .div = 0 }
1232};
1233
1234static const struct clksel l4_clksel[] = {
1235 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1236 { .parent = NULL }
1237};
1238
1239static struct clk l4_ck = { /* used both as an ick and fck */
1240 .name = "l4_ck",
1241 .parent = &core_l3_ck,
1242 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1243 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1244 .clkdm_name = "core_l4_clkdm",
1245 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1246 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1247 .clksel = l4_clksel,
1248 .recalc = &omap2_clksel_recalc,
1249 .round_rate = &omap2_clksel_round_rate,
1250 .set_rate = &omap2_clksel_set_rate
1251};
1252
046d6b28
TL		 1253/*
1254 * SSI is in L3 management domain, its direct parent is core not l3,
1255 * many core power domain entities are grouped into the L3 clock
1256 * domain.
d1b03f61 1257 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
046d6b28
TL		 1258 *
1259 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1260 */
e32744b0
PW		 1261static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1262 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1263 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1264 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1265 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1266 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1267 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1268 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1269 { .div = 0 }
1270};
1271
1272static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1273 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1274 { .parent = NULL }
1275};
1276
046d6b28
TL		 1277static struct clk ssi_ssr_sst_fck = {
1278 .name = "ssi_fck",
1279 .parent = &core_ck,
1280 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 1281 DELAYED_APP,
d1b03f61 1282 .clkdm_name = "core_l3_clkdm",
e32744b0
PW		 1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1284 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1285 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1286 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1287 .clksel = ssi_ssr_sst_fck_clksel,
046d6b28 1288 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1289 .round_rate = &omap2_clksel_round_rate,
1290 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1291};
1292
d1b03f61 1293
046d6b28
TL		 1294/*
1295 * GFX clock domain
1296 * Clocks:
1297 * GFX_FCLK, GFX_ICLK
1298 * GFX_CG1(2d), GFX_CG2(3d)
1299 *
1300 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1301 * The 2d and 3d clocks run at a hardware determined
1302 * divided value of fclk.
1303 *
1304 */
e32744b0
PW		 1305/* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1306
1307/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1308static const struct clksel gfx_fck_clksel[] = {
1309 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1310 { .parent = NULL },
1311};
1312
046d6b28
TL		 1313static struct clk gfx_3d_fck = {
1314 .name = "gfx_3d_fck",
1315 .parent = &core_l3_ck,
e32744b0 1316 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1317 .clkdm_name = "gfx_clkdm",
e32744b0
PW		 1318 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1319 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1320 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1321 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1322 .clksel = gfx_fck_clksel,
046d6b28 1323 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1324 .round_rate = &omap2_clksel_round_rate,
1325 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1326};
1327
1328static struct clk gfx_2d_fck = {
1329 .name = "gfx_2d_fck",
1330 .parent = &core_l3_ck,
e32744b0 1331 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1332 .clkdm_name = "gfx_clkdm",
e32744b0
PW		 1333 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1334 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1335 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1336 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1337 .clksel = gfx_fck_clksel,
046d6b28 1338 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1339 .round_rate = &omap2_clksel_round_rate,
1340 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1341};
1342
1343static struct clk gfx_ick = {
1344 .name = "gfx_ick", /* From l3 */
1345 .parent = &core_l3_ck,
e32744b0 1346 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1347 .clkdm_name = "gfx_clkdm",
e32744b0
PW		 1348 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1349 .enable_bit = OMAP_EN_GFX_SHIFT,
1350 .recalc = &followparent_recalc,
046d6b28
TL		 1351};
1352
1353/*
1354 * Modem clock domain (2430)
1355 * CLOCKS:
1356 * MDM_OSC_CLK
1357 * MDM_ICLK
e32744b0 1358 * These clocks are usable in chassis mode only.
046d6b28 1359 */
e32744b0
PW		 1360static const struct clksel_rate mdm_ick_core_rates[] = {
1361 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1362 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1363 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1364 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1365 { .div = 0 }
1366};
1367
1368static const struct clksel mdm_ick_clksel[] = {
1369 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1370 { .parent = NULL }
1371};
1372
046d6b28
TL		 1373static struct clk mdm_ick = { /* used both as a ick and fck */
1374 .name = "mdm_ick",
1375 .parent = &core_ck,
e32744b0 1376 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
d1b03f61 1377 .clkdm_name = "mdm_clkdm",
e32744b0
PW		 1378 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1379 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1380 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1381 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1382 .clksel = mdm_ick_clksel,
046d6b28 1383 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1384 .round_rate = &omap2_clksel_round_rate,
1385 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1386};
1387
1388static struct clk mdm_osc_ck = {
1389 .name = "mdm_osc_ck",
046d6b28 1390 .parent = &osc_ck,
e32744b0 1391 .flags = CLOCK_IN_OMAP243X,
d1b03f61 1392 .clkdm_name = "mdm_clkdm",
e32744b0
PW		 1393 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1394 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1395 .recalc = &followparent_recalc,
046d6b28
TL		 1396};
1397
046d6b28
TL		 1398/*
1399 * DSS clock domain
1400 * CLOCKs:
1401 * DSS_L4_ICLK, DSS_L3_ICLK,
1402 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1403 *
1404 * DSS is both initiator and target.
1405 */
e32744b0
PW		 1406/* XXX Add RATE_NOT_VALIDATED */
1407
1408static const struct clksel_rate dss1_fck_sys_rates[] = {
1409 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1410 { .div = 0 }
1411};
1412
1413static const struct clksel_rate dss1_fck_core_rates[] = {
1414 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1415 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1416 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1417 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1418 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1419 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1420 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1421 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1422 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1423 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1424 { .div = 0 }
1425};
1426
1427static const struct clksel dss1_fck_clksel[] = {
1428 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1429 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1430 { .parent = NULL },
1431};
1432
046d6b28
TL		 1433static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1434 .name = "dss_ick",
1435 .parent = &l4_ck, /* really both l3 and l4 */
e32744b0 1436 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1437 .clkdm_name = "dss_clkdm",
e32744b0
PW		 1438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1439 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1440 .recalc = &followparent_recalc,
046d6b28
TL		 1441};
1442
1443static struct clk dss1_fck = {
1444 .name = "dss1_fck",
1445 .parent = &core_ck, /* Core or sys */
1446 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
e32744b0 1447 DELAYED_APP,
d1b03f61 1448 .clkdm_name = "dss_clkdm",
e32744b0
PW		 1449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1450 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1451 .init = &omap2_init_clksel_parent,
1452 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1453 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1454 .clksel = dss1_fck_clksel,
046d6b28 1455 .recalc = &omap2_clksel_recalc,
e32744b0
PW		 1456 .round_rate = &omap2_clksel_round_rate,
1457 .set_rate = &omap2_clksel_set_rate
1458};
1459
1460static const struct clksel_rate dss2_fck_sys_rates[] = {
1461 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1462 { .div = 0 }
1463};
1464
1465static const struct clksel_rate dss2_fck_48m_rates[] = {
1466 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1467 { .div = 0 }
1468};
1469
1470static const struct clksel dss2_fck_clksel[] = {
1471 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1472 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1473 { .parent = NULL }
046d6b28
TL		 1474};
1475
1476static struct clk dss2_fck = { /* Alt clk used in power management */
1477 .name = "dss2_fck",
1478 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1479 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
474844f7 1480 DELAYED_APP,
d1b03f61 1481 .clkdm_name = "dss_clkdm",
e32744b0
PW		 1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1484 .init = &omap2_init_clksel_parent,
1485 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1486 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1487 .clksel = dss2_fck_clksel,
1488 .recalc = &followparent_recalc,
046d6b28
TL		 1489};
1490
1491static struct clk dss_54m_fck = { /* Alt clk used in power management */
1492 .name = "dss_54m_fck", /* 54m tv clk */
1493 .parent = &func_54m_ck,
e32744b0 1494 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1495 .clkdm_name = "dss_clkdm",
e32744b0
PW		 1496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1498 .recalc = &followparent_recalc,
046d6b28
TL		 1499};
1500
1501/*
1502 * CORE power domain ICLK & FCLK defines.
1503 * Many of the these can have more than one possible parent. Entries
1504 * here will likely have an L4 interface parent, and may have multiple
1505 * functional clock parents.
1506 */
e32744b0
PW		 1507static const struct clksel_rate gpt_alt_rates[] = {
1508 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1509 { .div = 0 }
1510};
1511
1512static const struct clksel omap24xx_gpt_clksel[] = {
1513 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1514 { .parent = &sys_ck, .rates = gpt_sys_rates },
1515 { .parent = &alt_ck, .rates = gpt_alt_rates },
1516 { .parent = NULL },
1517};
1518
046d6b28
TL		 1519static struct clk gpt1_ick = {
1520 .name = "gpt1_ick",
1521 .parent = &l4_ck,
1522 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1523 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1524 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1525 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1526 .recalc = &followparent_recalc,
046d6b28
TL		 1527};
1528
1529static struct clk gpt1_fck = {
1530 .name = "gpt1_fck",
1531 .parent = &func_32k_ck,
e32744b0 1532 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1533 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1534 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1535 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1536 .init = &omap2_init_clksel_parent,
1537 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1538 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1539 .clksel = omap24xx_gpt_clksel,
1540 .recalc = &omap2_clksel_recalc,
1541 .round_rate = &omap2_clksel_round_rate,
1542 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 1543};
1544
1545static struct clk gpt2_ick = {
1546 .name = "gpt2_ick",
1547 .parent = &l4_ck,
1548 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1549 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1551 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1552 .recalc = &followparent_recalc,
046d6b28
TL		 1553};
1554
1555static struct clk gpt2_fck = {
1556 .name = "gpt2_fck",
1557 .parent = &func_32k_ck,
e32744b0 1558 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1559 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1561 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1562 .init = &omap2_init_clksel_parent,
1563 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1564 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1565 .clksel = omap24xx_gpt_clksel,
1566 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1567};
1568
1569static struct clk gpt3_ick = {
1570 .name = "gpt3_ick",
1571 .parent = &l4_ck,
1572 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1573 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1574 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1575 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1576 .recalc = &followparent_recalc,
046d6b28
TL		 1577};
1578
1579static struct clk gpt3_fck = {
1580 .name = "gpt3_fck",
1581 .parent = &func_32k_ck,
e32744b0 1582 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1583 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1584 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1585 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1586 .init = &omap2_init_clksel_parent,
1587 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1588 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1589 .clksel = omap24xx_gpt_clksel,
1590 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1591};
1592
1593static struct clk gpt4_ick = {
1594 .name = "gpt4_ick",
1595 .parent = &l4_ck,
1596 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1597 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1599 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1600 .recalc = &followparent_recalc,
046d6b28
TL		 1601};
1602
1603static struct clk gpt4_fck = {
1604 .name = "gpt4_fck",
1605 .parent = &func_32k_ck,
e32744b0 1606 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1607 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1610 .init = &omap2_init_clksel_parent,
1611 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1612 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1613 .clksel = omap24xx_gpt_clksel,
1614 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1615};
1616
1617static struct clk gpt5_ick = {
1618 .name = "gpt5_ick",
1619 .parent = &l4_ck,
1620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1621 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1623 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1624 .recalc = &followparent_recalc,
046d6b28
TL		 1625};
1626
1627static struct clk gpt5_fck = {
1628 .name = "gpt5_fck",
1629 .parent = &func_32k_ck,
e32744b0 1630 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1631 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1633 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1634 .init = &omap2_init_clksel_parent,
1635 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1636 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1637 .clksel = omap24xx_gpt_clksel,
1638 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1639};
1640
1641static struct clk gpt6_ick = {
1642 .name = "gpt6_ick",
1643 .parent = &l4_ck,
1644 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1645 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1646 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1647 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1648 .recalc = &followparent_recalc,
046d6b28
TL		 1649};
1650
1651static struct clk gpt6_fck = {
1652 .name = "gpt6_fck",
1653 .parent = &func_32k_ck,
e32744b0 1654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1655 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1657 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1658 .init = &omap2_init_clksel_parent,
1659 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1660 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1661 .clksel = omap24xx_gpt_clksel,
1662 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1663};
1664
1665static struct clk gpt7_ick = {
1666 .name = "gpt7_ick",
1667 .parent = &l4_ck,
1668 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1670 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1671 .recalc = &followparent_recalc,
046d6b28
TL		 1672};
1673
1674static struct clk gpt7_fck = {
1675 .name = "gpt7_fck",
1676 .parent = &func_32k_ck,
e32744b0 1677 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1678 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1679 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1680 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1681 .init = &omap2_init_clksel_parent,
1682 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1683 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1684 .clksel = omap24xx_gpt_clksel,
1685 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1686};
1687
1688static struct clk gpt8_ick = {
1689 .name = "gpt8_ick",
1690 .parent = &l4_ck,
1691 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1692 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1693 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1694 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1695 .recalc = &followparent_recalc,
046d6b28
TL		 1696};
1697
1698static struct clk gpt8_fck = {
1699 .name = "gpt8_fck",
1700 .parent = &func_32k_ck,
e32744b0 1701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1702 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1703 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1704 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1705 .init = &omap2_init_clksel_parent,
1706 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1707 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1708 .clksel = omap24xx_gpt_clksel,
1709 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1710};
1711
1712static struct clk gpt9_ick = {
1713 .name = "gpt9_ick",
1714 .parent = &l4_ck,
1715 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1716 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1718 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1719 .recalc = &followparent_recalc,
046d6b28
TL		 1720};
1721
1722static struct clk gpt9_fck = {
1723 .name = "gpt9_fck",
1724 .parent = &func_32k_ck,
e32744b0 1725 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1726 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1728 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1729 .init = &omap2_init_clksel_parent,
1730 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1731 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1732 .clksel = omap24xx_gpt_clksel,
1733 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1734};
1735
1736static struct clk gpt10_ick = {
1737 .name = "gpt10_ick",
1738 .parent = &l4_ck,
1739 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1740 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1743 .recalc = &followparent_recalc,
046d6b28
TL		 1744};
1745
1746static struct clk gpt10_fck = {
1747 .name = "gpt10_fck",
1748 .parent = &func_32k_ck,
e32744b0 1749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1750 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1752 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1753 .init = &omap2_init_clksel_parent,
1754 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1755 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1756 .clksel = omap24xx_gpt_clksel,
1757 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1758};
1759
1760static struct clk gpt11_ick = {
1761 .name = "gpt11_ick",
1762 .parent = &l4_ck,
1763 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1764 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1767 .recalc = &followparent_recalc,
046d6b28
TL		 1768};
1769
1770static struct clk gpt11_fck = {
1771 .name = "gpt11_fck",
1772 .parent = &func_32k_ck,
e32744b0 1773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1774 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1776 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1777 .init = &omap2_init_clksel_parent,
1778 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1779 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1780 .clksel = omap24xx_gpt_clksel,
1781 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1782};
1783
1784static struct clk gpt12_ick = {
1785 .name = "gpt12_ick",
1786 .parent = &l4_ck,
1787 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1788 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1790 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1791 .recalc = &followparent_recalc,
046d6b28
TL		 1792};
1793
1794static struct clk gpt12_fck = {
1795 .name = "gpt12_fck",
1796 .parent = &func_32k_ck,
e32744b0 1797 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1798 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1800 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1801 .init = &omap2_init_clksel_parent,
1802 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1803 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1804 .clksel = omap24xx_gpt_clksel,
1805 .recalc = &omap2_clksel_recalc,
046d6b28
TL		 1806};
1807
1808static struct clk mcbsp1_ick = {
44ec9a33
EV		 1809 .name = "mcbsp_ick",
1810 .id = 1,
046d6b28
TL		 1811 .parent = &l4_ck,
1812 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1813 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1816 .recalc = &followparent_recalc,
046d6b28
TL		 1817};
1818
1819static struct clk mcbsp1_fck = {
44ec9a33
EV		 1820 .name = "mcbsp_fck",
1821 .id = 1,
046d6b28
TL		 1822 .parent = &func_96m_ck,
1823 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1824 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1826 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1827 .recalc = &followparent_recalc,
046d6b28
TL		 1828};
1829
1830static struct clk mcbsp2_ick = {
44ec9a33
EV		 1831 .name = "mcbsp_ick",
1832 .id = 2,
046d6b28
TL		 1833 .parent = &l4_ck,
1834 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1835 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1838 .recalc = &followparent_recalc,
046d6b28
TL		 1839};
1840
1841static struct clk mcbsp2_fck = {
44ec9a33
EV		 1842 .name = "mcbsp_fck",
1843 .id = 2,
046d6b28
TL		 1844 .parent = &func_96m_ck,
1845 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1846 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1848 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1849 .recalc = &followparent_recalc,
046d6b28
TL		 1850};
1851
1852static struct clk mcbsp3_ick = {
44ec9a33
EV		 1853 .name = "mcbsp_ick",
1854 .id = 3,
046d6b28
TL		 1855 .parent = &l4_ck,
1856 .flags = CLOCK_IN_OMAP243X,
d1b03f61 1857 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1859 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1860 .recalc = &followparent_recalc,
046d6b28
TL		 1861};
1862
1863static struct clk mcbsp3_fck = {
44ec9a33
EV		 1864 .name = "mcbsp_fck",
1865 .id = 3,
046d6b28
TL		 1866 .parent = &func_96m_ck,
1867 .flags = CLOCK_IN_OMAP243X,
d1b03f61 1868 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1869 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1870 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1871 .recalc = &followparent_recalc,
046d6b28
TL		 1872};
1873
1874static struct clk mcbsp4_ick = {
44ec9a33
EV		 1875 .name = "mcbsp_ick",
1876 .id = 4,
046d6b28
TL		 1877 .parent = &l4_ck,
1878 .flags = CLOCK_IN_OMAP243X,
d1b03f61 1879 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1881 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1882 .recalc = &followparent_recalc,
046d6b28
TL		 1883};
1884
1885static struct clk mcbsp4_fck = {
44ec9a33
EV		 1886 .name = "mcbsp_fck",
1887 .id = 4,
046d6b28
TL		 1888 .parent = &func_96m_ck,
1889 .flags = CLOCK_IN_OMAP243X,
d1b03f61 1890 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1892 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1893 .recalc = &followparent_recalc,
046d6b28
TL		 1894};
1895
1896static struct clk mcbsp5_ick = {
44ec9a33
EV		 1897 .name = "mcbsp_ick",
1898 .id = 5,
046d6b28
TL		 1899 .parent = &l4_ck,
1900 .flags = CLOCK_IN_OMAP243X,
d1b03f61 1901 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1903 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1904 .recalc = &followparent_recalc,
046d6b28
TL		 1905};
1906
1907static struct clk mcbsp5_fck = {
44ec9a33
EV		 1908 .name = "mcbsp_fck",
1909 .id = 5,
046d6b28
TL		 1910 .parent = &func_96m_ck,
1911 .flags = CLOCK_IN_OMAP243X,
d1b03f61 1912 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1914 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1915 .recalc = &followparent_recalc,
046d6b28
TL		 1916};
1917
1918static struct clk mcspi1_ick = {
90afd5cb
TL		 1919 .name = "mcspi_ick",
1920 .id = 1,
046d6b28 1921 .parent = &l4_ck,
d1b03f61 1922 .clkdm_name = "core_l4_clkdm",
046d6b28 1923 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
e32744b0
PW		 1924 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1925 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1926 .recalc = &followparent_recalc,
046d6b28
TL		 1927};
1928
1929static struct clk mcspi1_fck = {
90afd5cb
TL		 1930 .name = "mcspi_fck",
1931 .id = 1,
046d6b28
TL		 1932 .parent = &func_48m_ck,
1933 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1934 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1935 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1936 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1937 .recalc = &followparent_recalc,
046d6b28
TL		 1938};
1939
1940static struct clk mcspi2_ick = {
90afd5cb
TL		 1941 .name = "mcspi_ick",
1942 .id = 2,
046d6b28
TL		 1943 .parent = &l4_ck,
1944 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1945 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1948 .recalc = &followparent_recalc,
046d6b28
TL		 1949};
1950
1951static struct clk mcspi2_fck = {
90afd5cb
TL		 1952 .name = "mcspi_fck",
1953 .id = 2,
046d6b28
TL		 1954 .parent = &func_48m_ck,
1955 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1956 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1958 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1959 .recalc = &followparent_recalc,
046d6b28
TL		 1960};
1961
1962static struct clk mcspi3_ick = {
90afd5cb
TL		 1963 .name = "mcspi_ick",
1964 .id = 3,
046d6b28
TL		 1965 .parent = &l4_ck,
1966 .flags = CLOCK_IN_OMAP243X,
d1b03f61 1967 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1969 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1970 .recalc = &followparent_recalc,
046d6b28
TL		 1971};
1972
1973static struct clk mcspi3_fck = {
90afd5cb
TL		 1974 .name = "mcspi_fck",
1975 .id = 3,
046d6b28
TL		 1976 .parent = &func_48m_ck,
1977 .flags = CLOCK_IN_OMAP243X,
d1b03f61 1978 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1980 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1981 .recalc = &followparent_recalc,
046d6b28
TL		 1982};
1983
1984static struct clk uart1_ick = {
1985 .name = "uart1_ick",
1986 .parent = &l4_ck,
1987 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1988 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1989 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1990 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1991 .recalc = &followparent_recalc,
046d6b28
TL		 1992};
1993
1994static struct clk uart1_fck = {
1995 .name = "uart1_fck",
1996 .parent = &func_48m_ck,
1997 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 1998 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 1999 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2000 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
2001 .recalc = &followparent_recalc,
046d6b28
TL		 2002};
2003
2004static struct clk uart2_ick = {
2005 .name = "uart2_ick",
2006 .parent = &l4_ck,
2007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2008 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2009 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2010 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2011 .recalc = &followparent_recalc,
046d6b28
TL		 2012};
2013
2014static struct clk uart2_fck = {
2015 .name = "uart2_fck",
2016 .parent = &func_48m_ck,
2017 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2018 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2019 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2020 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2021 .recalc = &followparent_recalc,
046d6b28
TL		 2022};
2023
2024static struct clk uart3_ick = {
2025 .name = "uart3_ick",
2026 .parent = &l4_ck,
2027 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2028 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2029 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2030 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2031 .recalc = &followparent_recalc,
046d6b28
TL		 2032};
2033
2034static struct clk uart3_fck = {
2035 .name = "uart3_fck",
2036 .parent = &func_48m_ck,
2037 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2038 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2039 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2040 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2041 .recalc = &followparent_recalc,
046d6b28
TL		 2042};
2043
2044static struct clk gpios_ick = {
2045 .name = "gpios_ick",
2046 .parent = &l4_ck,
2047 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2048 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2049 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2050 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2051 .recalc = &followparent_recalc,
046d6b28
TL		 2052};
2053
2054static struct clk gpios_fck = {
2055 .name = "gpios_fck",
2056 .parent = &func_32k_ck,
2057 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2058 .clkdm_name = "wkup_clkdm",
e32744b0
PW		 2059 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2060 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2061 .recalc = &followparent_recalc,
046d6b28
TL		 2062};
2063
2064static struct clk mpu_wdt_ick = {
2065 .name = "mpu_wdt_ick",
2066 .parent = &l4_ck,
2067 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2068 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2069 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2070 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2071 .recalc = &followparent_recalc,
046d6b28
TL		 2072};
2073
2074static struct clk mpu_wdt_fck = {
2075 .name = "mpu_wdt_fck",
2076 .parent = &func_32k_ck,
2077 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2078 .clkdm_name = "wkup_clkdm",
e32744b0
PW		 2079 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2080 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2081 .recalc = &followparent_recalc,
046d6b28
TL		 2082};
2083
2084static struct clk sync_32k_ick = {
2085 .name = "sync_32k_ick",
2086 .parent = &l4_ck,
d1b03f61
PW		 2087 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2088 ENABLE_ON_INIT,
2089 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2090 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2091 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
2092 .recalc = &followparent_recalc,
046d6b28 2093};
d1b03f61 2094
046d6b28
TL		 2095static struct clk wdt1_ick = {
2096 .name = "wdt1_ick",
2097 .parent = &l4_ck,
2098 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2099 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2100 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2101 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2102 .recalc = &followparent_recalc,
046d6b28 2103};
d1b03f61 2104
046d6b28
TL		 2105static struct clk omapctrl_ick = {
2106 .name = "omapctrl_ick",
2107 .parent = &l4_ck,
d1b03f61
PW		 2108 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2109 ENABLE_ON_INIT,
2110 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2111 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2112 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2113 .recalc = &followparent_recalc,
046d6b28 2114};
d1b03f61 2115
046d6b28
TL		 2116static struct clk icr_ick = {
2117 .name = "icr_ick",
2118 .parent = &l4_ck,
2119 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2120 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2121 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2122 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2123 .recalc = &followparent_recalc,
046d6b28
TL		 2124};
2125
2126static struct clk cam_ick = {
2127 .name = "cam_ick",
2128 .parent = &l4_ck,
2129 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2130 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2131 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2132 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2133 .recalc = &followparent_recalc,
046d6b28
TL		 2134};
2135
d1b03f61
PW		 2136/*
2137 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
2138 * split into two separate clocks, since the parent clocks are different
2139 * and the clockdomains are also different.
2140 */
046d6b28
TL		 2141static struct clk cam_fck = {
2142 .name = "cam_fck",
2143 .parent = &func_96m_ck,
2144 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2145 .clkdm_name = "core_l3_clkdm",
e32744b0
PW		 2146 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2147 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2148 .recalc = &followparent_recalc,
046d6b28
TL		 2149};
2150
2151static struct clk mailboxes_ick = {
2152 .name = "mailboxes_ick",
2153 .parent = &l4_ck,
2154 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2155 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2156 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2157 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2158 .recalc = &followparent_recalc,
046d6b28
TL		 2159};
2160
2161static struct clk wdt4_ick = {
2162 .name = "wdt4_ick",
2163 .parent = &l4_ck,
2164 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2165 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2166 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2167 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2168 .recalc = &followparent_recalc,
046d6b28
TL		 2169};
2170
2171static struct clk wdt4_fck = {
2172 .name = "wdt4_fck",
2173 .parent = &func_32k_ck,
2174 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2175 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2176 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2177 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2178 .recalc = &followparent_recalc,
046d6b28
TL		 2179};
2180
2181static struct clk wdt3_ick = {
2182 .name = "wdt3_ick",
2183 .parent = &l4_ck,
2184 .flags = CLOCK_IN_OMAP242X,
d1b03f61 2185 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2187 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2188 .recalc = &followparent_recalc,
046d6b28
TL		 2189};
2190
2191static struct clk wdt3_fck = {
2192 .name = "wdt3_fck",
2193 .parent = &func_32k_ck,
2194 .flags = CLOCK_IN_OMAP242X,
d1b03f61 2195 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2197 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2198 .recalc = &followparent_recalc,
046d6b28
TL		 2199};
2200
2201static struct clk mspro_ick = {
2202 .name = "mspro_ick",
2203 .parent = &l4_ck,
2204 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2205 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2206 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2207 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2208 .recalc = &followparent_recalc,
046d6b28
TL		 2209};
2210
2211static struct clk mspro_fck = {
2212 .name = "mspro_fck",
2213 .parent = &func_96m_ck,
2214 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2215 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2217 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2218 .recalc = &followparent_recalc,
046d6b28
TL		 2219};
2220
2221static struct clk mmc_ick = {
2222 .name = "mmc_ick",
2223 .parent = &l4_ck,
2224 .flags = CLOCK_IN_OMAP242X,
d1b03f61 2225 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2227 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2228 .recalc = &followparent_recalc,
046d6b28
TL		 2229};
2230
2231static struct clk mmc_fck = {
2232 .name = "mmc_fck",
2233 .parent = &func_96m_ck,
2234 .flags = CLOCK_IN_OMAP242X,
d1b03f61 2235 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2237 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2238 .recalc = &followparent_recalc,
046d6b28
TL		 2239};
2240
2241static struct clk fac_ick = {
2242 .name = "fac_ick",
2243 .parent = &l4_ck,
2244 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2245 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2247 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2248 .recalc = &followparent_recalc,
046d6b28
TL		 2249};
2250
2251static struct clk fac_fck = {
2252 .name = "fac_fck",
2253 .parent = &func_12m_ck,
2254 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2255 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2257 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2258 .recalc = &followparent_recalc,
046d6b28
TL		 2259};
2260
2261static struct clk eac_ick = {
2262 .name = "eac_ick",
2263 .parent = &l4_ck,
2264 .flags = CLOCK_IN_OMAP242X,
d1b03f61 2265 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2267 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2268 .recalc = &followparent_recalc,
046d6b28
TL		 2269};
2270
2271static struct clk eac_fck = {
2272 .name = "eac_fck",
2273 .parent = &func_96m_ck,
2274 .flags = CLOCK_IN_OMAP242X,
d1b03f61 2275 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2277 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2278 .recalc = &followparent_recalc,
046d6b28
TL		 2279};
2280
2281static struct clk hdq_ick = {
2282 .name = "hdq_ick",
2283 .parent = &l4_ck,
2284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2285 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2287 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2288 .recalc = &followparent_recalc,
046d6b28
TL		 2289};
2290
2291static struct clk hdq_fck = {
2292 .name = "hdq_fck",
2293 .parent = &func_12m_ck,
2294 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2295 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2297 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2298 .recalc = &followparent_recalc,
046d6b28
TL		 2299};
2300
2301static struct clk i2c2_ick = {
b824efae
TL		 2302 .name = "i2c_ick",
2303 .id = 2,
046d6b28
TL		 2304 .parent = &l4_ck,
2305 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2306 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2308 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2309 .recalc = &followparent_recalc,
046d6b28
TL		 2310};
2311
2312static struct clk i2c2_fck = {
b824efae
TL		 2313 .name = "i2c_fck",
2314 .id = 2,
046d6b28 2315 .parent = &func_12m_ck,
e32744b0 2316 .flags = CLOCK_IN_OMAP242X,
d1b03f61 2317 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2319 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2320 .recalc = &followparent_recalc,
046d6b28
TL		 2321};
2322
2323static struct clk i2chs2_fck = {
4574eb68 2324 .name = "i2c_fck",
e32744b0 2325 .id = 2,
046d6b28
TL		 2326 .parent = &func_96m_ck,
2327 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2328 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2329 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2330 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2331 .recalc = &followparent_recalc,
046d6b28
TL		 2332};
2333
2334static struct clk i2c1_ick = {
b824efae
TL		 2335 .name = "i2c_ick",
2336 .id = 1,
046d6b28
TL		 2337 .parent = &l4_ck,
2338 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2339 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2341 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2342 .recalc = &followparent_recalc,
046d6b28
TL		 2343};
2344
2345static struct clk i2c1_fck = {
b824efae
TL		 2346 .name = "i2c_fck",
2347 .id = 1,
046d6b28 2348 .parent = &func_12m_ck,
e32744b0 2349 .flags = CLOCK_IN_OMAP242X,
d1b03f61 2350 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2352 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2353 .recalc = &followparent_recalc,
046d6b28
TL		 2354};
2355
2356static struct clk i2chs1_fck = {
4574eb68 2357 .name = "i2c_fck",
e32744b0 2358 .id = 1,
046d6b28
TL		 2359 .parent = &func_96m_ck,
2360 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2361 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2363 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2364 .recalc = &followparent_recalc,
2365};
2366
2367static struct clk gpmc_fck = {
2368 .name = "gpmc_fck",
2369 .parent = &core_l3_ck,
d1b03f61
PW		 2370 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2371 ENABLE_ON_INIT,
2372 .clkdm_name = "core_l3_clkdm",
e32744b0
PW		 2373 .recalc = &followparent_recalc,
2374};
2375
2376static struct clk sdma_fck = {
2377 .name = "sdma_fck",
2378 .parent = &core_l3_ck,
2379 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2380 .clkdm_name = "core_l3_clkdm",
e32744b0
PW		 2381 .recalc = &followparent_recalc,
2382};
2383
2384static struct clk sdma_ick = {
2385 .name = "sdma_ick",
2386 .parent = &l4_ck,
2387 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
d1b03f61 2388 .clkdm_name = "core_l3_clkdm",
e32744b0 2389 .recalc = &followparent_recalc,
046d6b28
TL		 2390};
2391
2392static struct clk vlynq_ick = {
2393 .name = "vlynq_ick",
2394 .parent = &core_l3_ck,
2395 .flags = CLOCK_IN_OMAP242X,
d1b03f61 2396 .clkdm_name = "core_l3_clkdm",
e32744b0
PW		 2397 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2398 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2399 .recalc = &followparent_recalc,
2400};
2401
2402static const struct clksel_rate vlynq_fck_96m_rates[] = {
2403 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2404 { .div = 0 }
2405};
2406
2407static const struct clksel_rate vlynq_fck_core_rates[] = {
2408 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2409 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2410 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2411 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2412 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2413 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2414 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2415 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2416 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2417 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2418 { .div = 0 }
2419};
2420
2421static const struct clksel vlynq_fck_clksel[] = {
2422 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2423 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2424 { .parent = NULL }
046d6b28
TL		 2425};
2426
2427static struct clk vlynq_fck = {
2428 .name = "vlynq_fck",
2429 .parent = &func_96m_ck,
e32744b0 2430 .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
d1b03f61 2431 .clkdm_name = "core_l3_clkdm",
e32744b0
PW		 2432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2433 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2434 .init = &omap2_init_clksel_parent,
2435 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2436 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2437 .clksel = vlynq_fck_clksel,
2438 .recalc = &omap2_clksel_recalc,
2439 .round_rate = &omap2_clksel_round_rate,
2440 .set_rate = &omap2_clksel_set_rate
046d6b28
TL		 2441};
2442
2443static struct clk sdrc_ick = {
2444 .name = "sdrc_ick",
2445 .parent = &l4_ck,
e32744b0 2446 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
d1b03f61 2447 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2448 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2449 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2450 .recalc = &followparent_recalc,
046d6b28
TL		 2451};
2452
2453static struct clk des_ick = {
2454 .name = "des_ick",
2455 .parent = &l4_ck,
2456 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
d1b03f61 2457 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2459 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2460 .recalc = &followparent_recalc,
046d6b28
TL		 2461};
2462
2463static struct clk sha_ick = {
2464 .name = "sha_ick",
2465 .parent = &l4_ck,
2466 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
d1b03f61 2467 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2468 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2469 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2470 .recalc = &followparent_recalc,
046d6b28
TL		 2471};
2472
2473static struct clk rng_ick = {
2474 .name = "rng_ick",
2475 .parent = &l4_ck,
2476 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
d1b03f61 2477 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2478 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2479 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2480 .recalc = &followparent_recalc,
046d6b28
TL		 2481};
2482
2483static struct clk aes_ick = {
2484 .name = "aes_ick",
2485 .parent = &l4_ck,
2486 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
d1b03f61 2487 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2489 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2490 .recalc = &followparent_recalc,
046d6b28
TL		 2491};
2492
2493static struct clk pka_ick = {
2494 .name = "pka_ick",
2495 .parent = &l4_ck,
2496 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
d1b03f61 2497 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2499 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2500 .recalc = &followparent_recalc,
046d6b28
TL		 2501};
2502
2503static struct clk usb_fck = {
2504 .name = "usb_fck",
2505 .parent = &func_48m_ck,
2506 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
d1b03f61 2507 .clkdm_name = "core_l3_clkdm",
e32744b0
PW		 2508 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2509 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2510 .recalc = &followparent_recalc,
046d6b28
TL		 2511};
2512
2513static struct clk usbhs_ick = {
2514 .name = "usbhs_ick",
fde0fd49 2515 .parent = &core_l3_ck,
046d6b28 2516 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2517 .clkdm_name = "core_l3_clkdm",
e32744b0
PW		 2518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2519 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2520 .recalc = &followparent_recalc,
046d6b28
TL		 2521};
2522
2523static struct clk mmchs1_ick = {
e32744b0 2524 .name = "mmchs_ick",
046d6b28
TL		 2525 .parent = &l4_ck,
2526 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2527 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2528 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2529 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2530 .recalc = &followparent_recalc,
046d6b28
TL		 2531};
2532
2533static struct clk mmchs1_fck = {
e32744b0 2534 .name = "mmchs_fck",
046d6b28
TL		 2535 .parent = &func_96m_ck,
2536 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2537 .clkdm_name = "core_l3_clkdm",
e32744b0
PW		 2538 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2539 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2540 .recalc = &followparent_recalc,
046d6b28
TL		 2541};
2542
2543static struct clk mmchs2_ick = {
e32744b0 2544 .name = "mmchs_ick",
d8874665 2545 .id = 1,
046d6b28
TL		 2546 .parent = &l4_ck,
2547 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2548 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2549 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2550 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2551 .recalc = &followparent_recalc,
046d6b28
TL		 2552};
2553
2554static struct clk mmchs2_fck = {
e32744b0 2555 .name = "mmchs_fck",
d8874665 2556 .id = 1,
046d6b28
TL		 2557 .parent = &func_96m_ck,
2558 .flags = CLOCK_IN_OMAP243X,
e32744b0
PW		 2559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2560 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2561 .recalc = &followparent_recalc,
046d6b28
TL		 2562};
2563
2564static struct clk gpio5_ick = {
2565 .name = "gpio5_ick",
2566 .parent = &l4_ck,
2567 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2568 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2570 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2571 .recalc = &followparent_recalc,
046d6b28
TL		 2572};
2573
2574static struct clk gpio5_fck = {
2575 .name = "gpio5_fck",
2576 .parent = &func_32k_ck,
2577 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2578 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2580 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2581 .recalc = &followparent_recalc,
046d6b28
TL		 2582};
2583
2584static struct clk mdm_intc_ick = {
2585 .name = "mdm_intc_ick",
2586 .parent = &l4_ck,
2587 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2588 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2590 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2591 .recalc = &followparent_recalc,
046d6b28
TL		 2592};
2593
2594static struct clk mmchsdb1_fck = {
e32744b0 2595 .name = "mmchsdb_fck",
046d6b28
TL		 2596 .parent = &func_32k_ck,
2597 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2598 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2600 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2601 .recalc = &followparent_recalc,
046d6b28
TL		 2602};
2603
2604static struct clk mmchsdb2_fck = {
e32744b0 2605 .name = "mmchsdb_fck",
d8874665 2606 .id = 1,
046d6b28
TL		 2607 .parent = &func_32k_ck,
2608 .flags = CLOCK_IN_OMAP243X,
d1b03f61 2609 .clkdm_name = "core_l4_clkdm",
e32744b0
PW		 2610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2611 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2612 .recalc = &followparent_recalc,
046d6b28 2613};
e32744b0 2614
046d6b28
TL		 2615/*
2616 * This clock is a composite clock which does entire set changes then
2617 * forces a rebalance. It keys on the MPU speed, but it really could
2618 * be any key speed part of a set in the rate table.
2619 *
2620 * to really change a set, you need memory table sets which get changed
2621 * in sram, pre-notifiers & post notifiers, changing the top set, without
2622 * having low level display recalc's won't work... this is why dpm notifiers
2623 * work, isr's off, walk a list of clocks already _off_ and not messing with
2624 * the bus.
2625 *
2626 * This clock should have no parent. It embodies the entire upper level
2627 * active set. A parent will mess up some of the init also.
2628 */
2629static struct clk virt_prcm_set = {
2630 .name = "virt_prcm_set",
2631 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2632 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2633 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
e32744b0 2634 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
046d6b28
TL		 2635 .set_rate = &omap2_select_table_rate,
2636 .round_rate = &omap2_round_to_table_rate,
2637};
e32744b0
PW		 2638
2639static struct clk *onchip_24xx_clks[] __initdata = {
046d6b28
TL		 2640 /* external root sources */
2641 &func_32k_ck,
2642 &osc_ck,
2643 &sys_ck,
2644 &alt_ck,
2645 /* internal analog sources */
2646 &dpll_ck,
2647 &apll96_ck,
2648 &apll54_ck,
2649 /* internal prcm root sources */
2650 &func_54m_ck,
2651 &core_ck,
046d6b28
TL		 2652 &func_96m_ck,
2653 &func_48m_ck,
2654 &func_12m_ck,
2655 &wdt1_osc_ck,
e32744b0 2656 &sys_clkout_src,
046d6b28 2657 &sys_clkout,
e32744b0 2658 &sys_clkout2_src,
046d6b28 2659 &sys_clkout2,
b824efae 2660 &emul_ck,
046d6b28
TL		 2661 /* mpu domain clocks */
2662 &mpu_ck,
2663 /* dsp domain clocks */
046d6b28 2664 &dsp_fck,
e32744b0
PW		 2665 &dsp_irate_ick,
2666 &dsp_ick, /* 242x */
2667 &iva2_1_ick, /* 243x */
2668 &iva1_ifck, /* 242x */
2669 &iva1_mpu_int_ifck, /* 242x */
046d6b28
TL		 2670 /* GFX domain clocks */
2671 &gfx_3d_fck,
2672 &gfx_2d_fck,
2673 &gfx_ick,
2674 /* Modem domain clocks */
2675 &mdm_ick,
2676 &mdm_osc_ck,
2677 /* DSS domain clocks */
2678 &dss_ick,
2679 &dss1_fck,
2680 &dss2_fck,
2681 &dss_54m_fck,
2682 /* L3 domain clocks */
2683 &core_l3_ck,
2684 &ssi_ssr_sst_fck,
2685 &usb_l4_ick,
2686 /* L4 domain clocks */
2687 &l4_ck, /* used as both core_l4 and wu_l4 */
046d6b28
TL		 2688 /* virtual meta-group clock */
2689 &virt_prcm_set,
2690 /* general l4 interface ck, multi-parent functional clk */
2691 &gpt1_ick,
2692 &gpt1_fck,
2693 &gpt2_ick,
2694 &gpt2_fck,
2695 &gpt3_ick,
2696 &gpt3_fck,
2697 &gpt4_ick,
2698 &gpt4_fck,
2699 &gpt5_ick,
2700 &gpt5_fck,
2701 &gpt6_ick,
2702 &gpt6_fck,
2703 &gpt7_ick,
2704 &gpt7_fck,
2705 &gpt8_ick,
2706 &gpt8_fck,
2707 &gpt9_ick,
2708 &gpt9_fck,
2709 &gpt10_ick,
2710 &gpt10_fck,
2711 &gpt11_ick,
2712 &gpt11_fck,
2713 &gpt12_ick,
2714 &gpt12_fck,
2715 &mcbsp1_ick,
2716 &mcbsp1_fck,
2717 &mcbsp2_ick,
2718 &mcbsp2_fck,
2719 &mcbsp3_ick,
2720 &mcbsp3_fck,
2721 &mcbsp4_ick,
2722 &mcbsp4_fck,
2723 &mcbsp5_ick,
2724 &mcbsp5_fck,
2725 &mcspi1_ick,
2726 &mcspi1_fck,
2727 &mcspi2_ick,
2728 &mcspi2_fck,
2729 &mcspi3_ick,
2730 &mcspi3_fck,
2731 &uart1_ick,
2732 &uart1_fck,
2733 &uart2_ick,
2734 &uart2_fck,
2735 &uart3_ick,
2736 &uart3_fck,
2737 &gpios_ick,
2738 &gpios_fck,
2739 &mpu_wdt_ick,
2740 &mpu_wdt_fck,
2741 &sync_32k_ick,
2742 &wdt1_ick,
2743 &omapctrl_ick,
2744 &icr_ick,
2745 &cam_fck,
2746 &cam_ick,
2747 &mailboxes_ick,
2748 &wdt4_ick,
2749 &wdt4_fck,
2750 &wdt3_ick,
2751 &wdt3_fck,
2752 &mspro_ick,
2753 &mspro_fck,
2754 &mmc_ick,
2755 &mmc_fck,
2756 &fac_ick,
2757 &fac_fck,
2758 &eac_ick,
2759 &eac_fck,
2760 &hdq_ick,
2761 &hdq_fck,
2762 &i2c1_ick,
2763 &i2c1_fck,
2764 &i2chs1_fck,
2765 &i2c2_ick,
2766 &i2c2_fck,
2767 &i2chs2_fck,
e32744b0
PW		 2768 &gpmc_fck,
2769 &sdma_fck,
2770 &sdma_ick,
046d6b28
TL		 2771 &vlynq_ick,
2772 &vlynq_fck,
2773 &sdrc_ick,
2774 &des_ick,
2775 &sha_ick,
2776 &rng_ick,
2777 &aes_ick,
2778 &pka_ick,
2779 &usb_fck,
2780 &usbhs_ick,
2781 &mmchs1_ick,
2782 &mmchs1_fck,
2783 &mmchs2_ick,
2784 &mmchs2_fck,
2785 &gpio5_ick,
2786 &gpio5_fck,
2787 &mdm_intc_ick,
2788 &mmchsdb1_fck,
2789 &mmchsdb2_fck,
2790};
2791
2792#endif
6b8858a9 2793
kernel source for telekom puls (alcatel/mediatek)