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ARM: AM33XX: clock: add clock data in common clock format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / cclock33xx_data.c
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b4c63295
VH		 1/*
2 * AM33XX Clock data
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk-private.h>
20#include <linux/clkdev.h>
21#include <linux/io.h>
22
23#include "am33xx.h"
24#include "soc.h"
25#include "iomap.h"
26#include "clock.h"
27#include "control.h"
28#include "cm.h"
29#include "cm33xx.h"
30#include "cm-regbits-33xx.h"
31#include "prm.h"
32
33/* Modulemode control */
34#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
35#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
36
37/*LIST_HEAD(clocks);*/
38
39/* Root clocks */
40
41/* RTC 32k */
42DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
43
44/* On-Chip 32KHz RC OSC */
45DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
46
47/* Crystal input clks */
48DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
49
50DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
51
52DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
53
54DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
55
56/* Oscillator clock */
57/* 19.2, 24, 25 or 26 MHz */
58static const char *sys_clkin_ck_parents[] = {
59 "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
60 "virt_26000000_ck",
61};
62
63/*
64 * sys_clk in: input to the dpll and also used as funtional clock for,
65 * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
66 *
67 */
68DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
69 AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
70 AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
71 AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
72 0, NULL);
73
74/* External clock - 12 MHz */
75DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
76
77/* Module clocks and DPLL outputs */
78
79/* DPLL_CORE */
80static struct dpll_data dpll_core_dd = {
81 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
82 .clk_bypass = &sys_clkin_ck,
83 .clk_ref = &sys_clkin_ck,
84 .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
85 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
86 .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
87 .mult_mask = AM33XX_DPLL_MULT_MASK,
88 .div1_mask = AM33XX_DPLL_DIV_MASK,
89 .enable_mask = AM33XX_DPLL_EN_MASK,
90 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
91 .max_multiplier = 2047,
92 .max_divider = 128,
93 .min_divider = 1,
94};
95
96/* CLKDCOLDO output */
97static const char *dpll_core_ck_parents[] = {
98 "sys_clkin_ck",
99};
100
101static struct clk dpll_core_ck;
102
103static const struct clk_ops dpll_core_ck_ops = {
104 .recalc_rate = &omap3_dpll_recalc,
105 .get_parent = &omap2_init_dpll_parent,
106};
107
108static struct clk_hw_omap dpll_core_ck_hw = {
109 .hw = {
110 .clk = &dpll_core_ck,
111 },
112 .dpll_data = &dpll_core_dd,
113 .ops = &clkhwops_omap3_dpll,
114};
115
116DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
117
118static const char *dpll_core_x2_ck_parents[] = {
119 "dpll_core_ck",
120};
121
122static struct clk dpll_core_x2_ck;
123
124static const struct clk_ops dpll_x2_ck_ops = {
125 .recalc_rate = &omap3_clkoutx2_recalc,
126};
127
128static struct clk_hw_omap dpll_core_x2_ck_hw = {
129 .hw = {
130 .clk = &dpll_core_x2_ck,
131 },
132 .flags = CLOCK_CLKOUTX2,
133};
134
135DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
136
137DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
138 0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
139 AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
140 AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
141 NULL);
142
143DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
144 0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
145 AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
146 AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
147 CLK_DIVIDER_ONE_BASED, NULL);
148
149DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
150 0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
151 AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
152 AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
153 CLK_DIVIDER_ONE_BASED, NULL);
154
155
156/* DPLL_MPU */
157static struct dpll_data dpll_mpu_dd = {
158 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
159 .clk_bypass = &sys_clkin_ck,
160 .clk_ref = &sys_clkin_ck,
161 .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
162 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
163 .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
164 .mult_mask = AM33XX_DPLL_MULT_MASK,
165 .div1_mask = AM33XX_DPLL_DIV_MASK,
166 .enable_mask = AM33XX_DPLL_EN_MASK,
167 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
168 .max_multiplier = 2047,
169 .max_divider = 128,
170 .min_divider = 1,
171};
172
173/* CLKOUT: fdpll/M2 */
174static struct clk dpll_mpu_ck;
175
176static const struct clk_ops dpll_mpu_ck_ops = {
177 .enable = &omap3_noncore_dpll_enable,
178 .disable = &omap3_noncore_dpll_disable,
179 .recalc_rate = &omap3_dpll_recalc,
180 .round_rate = &omap2_dpll_round_rate,
181 .set_rate = &omap3_noncore_dpll_set_rate,
182 .get_parent = &omap2_init_dpll_parent,
183};
184
185static struct clk_hw_omap dpll_mpu_ck_hw = {
186 .hw = {
187 .clk = &dpll_mpu_ck,
188 },
189 .dpll_data = &dpll_mpu_dd,
190 .ops = &clkhwops_omap3_dpll,
191};
192
193DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
194
195/*
196 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
197 * and ALT_CLK1/2)
198 */
199DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
200 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
201 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
202
203/* DPLL_DDR */
204static struct dpll_data dpll_ddr_dd = {
205 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
206 .clk_bypass = &sys_clkin_ck,
207 .clk_ref = &sys_clkin_ck,
208 .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
209 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
210 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
211 .mult_mask = AM33XX_DPLL_MULT_MASK,
212 .div1_mask = AM33XX_DPLL_DIV_MASK,
213 .enable_mask = AM33XX_DPLL_EN_MASK,
214 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
215 .max_multiplier = 2047,
216 .max_divider = 128,
217 .min_divider = 1,
218};
219
220/* CLKOUT: fdpll/M2 */
221static struct clk dpll_ddr_ck;
222
223static const struct clk_ops dpll_ddr_ck_ops = {
224 .recalc_rate = &omap3_dpll_recalc,
225 .get_parent = &omap2_init_dpll_parent,
226 .round_rate = &omap2_dpll_round_rate,
227 .set_rate = &omap3_noncore_dpll_set_rate,
228};
229
230static struct clk_hw_omap dpll_ddr_ck_hw = {
231 .hw = {
232 .clk = &dpll_ddr_ck,
233 },
234 .dpll_data = &dpll_ddr_dd,
235 .ops = &clkhwops_omap3_dpll,
236};
237
238DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
239
240/*
241 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
242 * and ALT_CLK1/2)
243 */
244DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
245 0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
246 AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
247 CLK_DIVIDER_ONE_BASED, NULL);
248
249/* emif_fck functional clock */
250DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
251 0x0, 1, 2);
252
253/* DPLL_DISP */
254static struct dpll_data dpll_disp_dd = {
255 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
256 .clk_bypass = &sys_clkin_ck,
257 .clk_ref = &sys_clkin_ck,
258 .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
259 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
260 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
261 .mult_mask = AM33XX_DPLL_MULT_MASK,
262 .div1_mask = AM33XX_DPLL_DIV_MASK,
263 .enable_mask = AM33XX_DPLL_EN_MASK,
264 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
265 .max_multiplier = 2047,
266 .max_divider = 128,
267 .min_divider = 1,
268};
269
270/* CLKOUT: fdpll/M2 */
271static struct clk dpll_disp_ck;
272
273static struct clk_hw_omap dpll_disp_ck_hw = {
274 .hw = {
275 .clk = &dpll_disp_ck,
276 },
277 .dpll_data = &dpll_disp_dd,
278 .ops = &clkhwops_omap3_dpll,
279};
280
281DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
282
283/*
284 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
285 * and ALT_CLK1/2)
286 */
287DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0,
288 AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
289 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
290
291/* DPLL_PER */
292static struct dpll_data dpll_per_dd = {
293 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
294 .clk_bypass = &sys_clkin_ck,
295 .clk_ref = &sys_clkin_ck,
296 .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
297 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
298 .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
299 .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
300 .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
301 .enable_mask = AM33XX_DPLL_EN_MASK,
302 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
303 .max_multiplier = 2047,
304 .max_divider = 128,
305 .min_divider = 1,
306 .flags = DPLL_J_TYPE,
307};
308
309/* CLKDCOLDO */
310static struct clk dpll_per_ck;
311
312static struct clk_hw_omap dpll_per_ck_hw = {
313 .hw = {
314 .clk = &dpll_per_ck,
315 },
316 .dpll_data = &dpll_per_dd,
317 .ops = &clkhwops_omap3_dpll,
318};
319
320DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
321
322/* CLKOUT: fdpll/M2 */
323DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
324 AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
325 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
326 NULL);
327
328DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
329 &dpll_per_m2_ck, 0x0, 1, 4);
330
331DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
332 &dpll_per_m2_ck, 0x0, 1, 4);
333
334DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
335 &dpll_core_m4_ck, 0x0, 1, 2);
336
337DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
338 1, 2);
339
340DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
341 8);
342
343/*
344 * Below clock nodes describes clockdomains derived out
345 * of core clock.
346 */
347static const struct clk_ops clk_ops_null = {
348};
349
350static const char *l3_gclk_parents[] = {
351 "dpll_core_m4_ck"
352};
353
354static struct clk l3_gclk;
355DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
356DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
357
358static struct clk l4hs_gclk;
359DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
360DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
361
362static const char *l3s_gclk_parents[] = {
363 "dpll_core_m4_div2_ck"
364};
365
366static struct clk l3s_gclk;
367DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
368DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
369
370static struct clk l4fw_gclk;
371DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
372DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
373
374static struct clk l4ls_gclk;
375DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
376DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
377
378static struct clk sysclk_div_ck;
379DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
380DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
381
382/*
383 * In order to match the clock domain with hwmod clockdomain entry,
384 * separate clock nodes is required for the modules which are
385 * directly getting their funtioncal clock from sys_clkin.
386 */
387static struct clk adc_tsc_fck;
388DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
389DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
390
391static struct clk dcan0_fck;
392DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
393DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
394
395static struct clk dcan1_fck;
396DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
397DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
398
399static struct clk mcasp0_fck;
400DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
401DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
402
403static struct clk mcasp1_fck;
404DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
405DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
406
407static struct clk smartreflex0_fck;
408DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
409DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
410
411static struct clk smartreflex1_fck;
412DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
413DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
414
415/*
416 * Modules clock nodes
417 *
418 * The following clock leaf nodes are added for the moment because:
419 *
420 * - hwmod data is not present for these modules, either hwmod
421 * control is not required or its not populated.
422 * - Driver code is not yet migrated to use hwmod/runtime pm
423 * - Modules outside kernel access (to disable them by default)
424 *
425 * - debugss
426 * - mmu (gfx domain)
427 * - cefuse
428 * - usbotg_fck (its additional clock and not really a modulemode)
429 * - ieee5000
430 */
431DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
432 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
433 0x0, NULL);
434
435DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
436 AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
437 0x0, NULL);
438
439DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
440 AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
441 0x0, NULL);
442
443/*
444 * clkdiv32 is generated from fixed division of 732.4219
445 */
446DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
447
448DEFINE_CLK_GATE(clkdiv32k_ick, "clkdiv32k_ck", &clkdiv32k_ck, 0x0,
449 AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
450 0x0, NULL);
451
452/* "usbotg_fck" is an additional clock and not really a modulemode */
453DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
454 AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
455 0x0, NULL);
456
457DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
458 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
459 AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
460
461/* Timers */
462static const struct clksel timer1_clkmux_sel[] = {
463 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
464 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
465 { .parent = &tclkin_ck, .rates = div_1_2_rates },
466 { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
467 { .parent = &clk_32768_ck, .rates = div_1_4_rates },
468 { .parent = NULL },
469};
470
471static const char *timer1_ck_parents[] = {
472 "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
473 "clk_32768_ck",
474};
475
476static struct clk timer1_fck;
477
478static const struct clk_ops timer1_fck_ops = {
479 .recalc_rate = &omap2_clksel_recalc,
480 .get_parent = &omap2_clksel_find_parent_index,
481 .set_parent = &omap2_clksel_set_parent,
482 .init = &omap2_init_clk_clkdm,
483};
484
485static struct clk_hw_omap timer1_fck_hw = {
486 .hw = {
487 .clk = &timer1_fck,
488 },
489 .clkdm_name = "l4ls_clkdm",
490 .clksel = timer1_clkmux_sel,
491 .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
492 .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
493};
494
495DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
496
497static const struct clksel timer2_to_7_clk_sel[] = {
498 { .parent = &tclkin_ck, .rates = div_1_0_rates },
499 { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
500 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
501 { .parent = NULL },
502};
503
504static const char *timer2_to_7_ck_parents[] = {
505 "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
506};
507
508static struct clk timer2_fck;
509
510static struct clk_hw_omap timer2_fck_hw = {
511 .hw = {
512 .clk = &timer2_fck,
513 },
514 .clkdm_name = "l4ls_clkdm",
515 .clksel = timer2_to_7_clk_sel,
516 .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
517 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
518};
519
520DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
521
522static struct clk timer3_fck;
523
524static struct clk_hw_omap timer3_fck_hw = {
525 .hw = {
526 .clk = &timer3_fck,
527 },
528 .clkdm_name = "l4ls_clkdm",
529 .clksel = timer2_to_7_clk_sel,
530 .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
531 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
532};
533
534DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
535
536static struct clk timer4_fck;
537
538static struct clk_hw_omap timer4_fck_hw = {
539 .hw = {
540 .clk = &timer4_fck,
541 },
542 .clkdm_name = "l4ls_clkdm",
543 .clksel = timer2_to_7_clk_sel,
544 .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
545 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
546};
547
548DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
549
550static struct clk timer5_fck;
551
552static struct clk_hw_omap timer5_fck_hw = {
553 .hw = {
554 .clk = &timer5_fck,
555 },
556 .clkdm_name = "l4ls_clkdm",
557 .clksel = timer2_to_7_clk_sel,
558 .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
559 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
560};
561
562DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
563
564static struct clk timer6_fck;
565
566static struct clk_hw_omap timer6_fck_hw = {
567 .hw = {
568 .clk = &timer6_fck,
569 },
570 .clkdm_name = "l4ls_clkdm",
571 .clksel = timer2_to_7_clk_sel,
572 .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
573 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
574};
575
576DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
577
578static struct clk timer7_fck;
579
580static struct clk_hw_omap timer7_fck_hw = {
581 .hw = {
582 .clk = &timer7_fck,
583 },
584 .clkdm_name = "l4ls_clkdm",
585 .clksel = timer2_to_7_clk_sel,
586 .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
587 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
588};
589
590DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
591
592DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
593 "dpll_core_m5_ck",
594 &dpll_core_m5_ck,
595 0x0,
596 1, 2);
597
598static const struct clk_ops cpsw_fck_ops = {
599 .recalc_rate = &omap2_clksel_recalc,
600 .get_parent = &omap2_clksel_find_parent_index,
601 .set_parent = &omap2_clksel_set_parent,
602};
603
604static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
605 { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
606 { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
607 { .parent = NULL },
608};
609
610static const char *cpsw_cpts_rft_ck_parents[] = {
611 "dpll_core_m5_ck", "dpll_core_m4_ck",
612};
613
614static struct clk cpsw_cpts_rft_clk;
615
616static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
617 .hw = {
618 .clk = &cpsw_cpts_rft_clk,
619 },
620 .clkdm_name = "cpsw_125mhz_clkdm",
621 .clksel = cpsw_cpts_rft_clkmux_sel,
622 .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
623 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
624};
625
626DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
627
628
629/* gpio */
630static const char *gpio0_ck_parents[] = {
631 "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
632};
633
634static const struct clksel gpio0_dbclk_mux_sel[] = {
635 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
636 { .parent = &clk_32768_ck, .rates = div_1_1_rates },
637 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
638 { .parent = NULL },
639};
640
641static const struct clk_ops gpio_fck_ops = {
642 .recalc_rate = &omap2_clksel_recalc,
643 .get_parent = &omap2_clksel_find_parent_index,
644 .set_parent = &omap2_clksel_set_parent,
645 .init = &omap2_init_clk_clkdm,
646};
647
648static struct clk gpio0_dbclk_mux_ck;
649
650static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
651 .hw = {
652 .clk = &gpio0_dbclk_mux_ck,
653 },
654 .clkdm_name = "l4_wkup_clkdm",
655 .clksel = gpio0_dbclk_mux_sel,
656 .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
657 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
658};
659
660DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
661
662DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
663 AM33XX_CM_WKUP_GPIO0_CLKCTRL,
664 AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
665
666DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
667 AM33XX_CM_PER_GPIO1_CLKCTRL,
668 AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
669
670DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
671 AM33XX_CM_PER_GPIO2_CLKCTRL,
672 AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
673
674DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
675 AM33XX_CM_PER_GPIO3_CLKCTRL,
676 AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
677
678
679static const char *pruss_ck_parents[] = {
680 "l3_gclk", "dpll_disp_m2_ck",
681};
682
683static const struct clksel pruss_ocp_clk_mux_sel[] = {
684 { .parent = &l3_gclk, .rates = div_1_0_rates },
685 { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
686 { .parent = NULL },
687};
688
689static struct clk pruss_ocp_gclk;
690
691static struct clk_hw_omap pruss_ocp_gclk_hw = {
692 .hw = {
693 .clk = &pruss_ocp_gclk,
694 },
695 .clkdm_name = "pruss_ocp_clkdm",
696 .clksel = pruss_ocp_clk_mux_sel,
697 .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
698 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
699};
700
701DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
702
703static const char *lcd_ck_parents[] = {
704 "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
705};
706
707static const struct clksel lcd_clk_mux_sel[] = {
708 { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
709 { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
710 { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
711 { .parent = NULL },
712};
713
714static struct clk lcd_gclk;
715
716static struct clk_hw_omap lcd_gclk_hw = {
717 .hw = {
718 .clk = &lcd_gclk,
719 },
720 .clkdm_name = "lcdc_clkdm",
721 .clksel = lcd_clk_mux_sel,
722 .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
723 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
724};
725
726DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops);
727
728DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
729
730static const char *gfx_ck_parents[] = {
731 "dpll_core_m4_ck", "dpll_per_m2_ck",
732};
733
734static const struct clksel gfx_clksel_sel[] = {
735 { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
736 { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
737 { .parent = NULL },
738};
739
740static struct clk gfx_fclk_clksel_ck;
741
742static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
743 .hw = {
744 .clk = &gfx_fclk_clksel_ck,
745 },
746 .clksel = gfx_clksel_sel,
747 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
748 .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
749};
750
751DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
752
753static const struct clk_div_table div_1_0_2_1_rates[] = {
754 { .div = 1, .val = 0, },
755 { .div = 2, .val = 1, },
756 { .div = 0 },
757};
758
759DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
760 &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
761 AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
762 0x0, div_1_0_2_1_rates, NULL);
763
764static const char *sysclkout_ck_parents[] = {
765 "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
766 "lcd_gclk",
767};
768
769static const struct clksel sysclkout_pre_sel[] = {
770 { .parent = &clk_32768_ck, .rates = div_1_0_rates },
771 { .parent = &l3_gclk, .rates = div_1_1_rates },
772 { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
773 { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
774 { .parent = &lcd_gclk, .rates = div_1_4_rates },
775 { .parent = NULL },
776};
777
778static struct clk sysclkout_pre_ck;
779
780static struct clk_hw_omap sysclkout_pre_ck_hw = {
781 .hw = {
782 .clk = &sysclkout_pre_ck,
783 },
784 .clksel = sysclkout_pre_sel,
785 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
786 .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
787};
788
789DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
790
791/* Divide by 8 clock rates with default clock is 1/1*/
792static const struct clk_div_table div8_rates[] = {
793 { .div = 1, .val = 0, },
794 { .div = 2, .val = 1, },
795 { .div = 3, .val = 2, },
796 { .div = 4, .val = 3, },
797 { .div = 5, .val = 4, },
798 { .div = 6, .val = 5, },
799 { .div = 7, .val = 6, },
800 { .div = 8, .val = 7, },
801 { .div = 0 },
802};
803
804DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
805 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
806 AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
807
808DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
809 AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
810
811static const char *wdt_ck_parents[] = {
812 "clk_rc32k_ck", "clkdiv32k_ick",
813};
814
815static const struct clksel wdt_clkmux_sel[] = {
816 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
817 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
818 { .parent = NULL },
819};
820
821static struct clk wdt1_fck;
822
823static struct clk_hw_omap wdt1_fck_hw = {
824 .hw = {
825 .clk = &wdt1_fck,
826 },
827 .clkdm_name = "l4_wkup_clkdm",
828 .clksel = wdt_clkmux_sel,
829 .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
830 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
831};
832
833DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
834
835/*
836 * clkdev
837 */
838static struct omap_clk am33xx_clks[] = {
839 CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX),
840 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX),
841 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX),
842 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX),
843 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX),
844 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX),
845 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX),
846 CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX),
847 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX),
848 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX),
849 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX),
850 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
851 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
852 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
853 CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX),
854 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
855 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
856 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
857 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX),
858 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX),
859 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX),
860 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX),
861 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX),
862 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX),
863 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX),
864 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX),
865 CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX),
866 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX),
867 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX),
868 CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX),
869 CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX),
870 CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX),
871 CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX),
872 CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX),
873 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX),
874 CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX),
875 CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX),
876 CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
877 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
878 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
879 CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
880 CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
881 CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
882 CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
883 CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
884 CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
885 CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
886 CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
887 CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
888 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
889 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX),
890 CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX),
891 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX),
892 CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX),
893 CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX),
894 CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX),
895 CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX),
896 CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX),
897 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX),
898 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX),
899 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX),
900 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX),
901 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX),
902 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX),
903 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX),
904 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX),
905 CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX),
906 CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX),
907 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX),
908 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
909 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
910 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX),
911 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
912 CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
913};
914
915
916static const char *enable_init_clks[] = {
917 "dpll_ddr_m2_ck",
918 "dpll_mpu_m2_ck",
919 "l3_gclk",
920 "l4hs_gclk",
921 "l4fw_gclk",
922 "l4ls_gclk",
923};
924
925int __init am33xx_clk_init(void)
926{
927 struct omap_clk *c;
928 u32 cpu_clkflg;
929
930 if (soc_is_am33xx()) {
931 cpu_mask = RATE_IN_AM33XX;
932 cpu_clkflg = CK_AM33XX;
933 }
934
935 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
936 if (c->cpu & cpu_clkflg) {
937 clkdev_add(&c->lk);
938 if (!__clk_init(NULL, c->lk.clk))
939 omap2_init_clk_hw_omap_clocks(c->lk.clk);
940 }
941 }
942
943 omap2_clk_disable_autoidle_all();
944
945 omap2_clk_enable_init_clocks(enable_init_clks,
946 ARRAY_SIZE(enable_init_clks));
947
948 /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
949 * physically present, in such a case HWMOD enabling of
950 * clock would be failure with default parent. And timer
951 * probe thinks clock is already enabled, this leads to
952 * crash upon accessing timer 3 & 6 registers in probe.
953 * Fix by setting parent of both these timers to master
954 * oscillator clock.
955 */
956
957 clk_set_parent(&timer3_fck, &sys_clkin_ck);
958 clk_set_parent(&timer6_fck, &sys_clkin_ck);
959
960 return 0;
961}
kernel source for telekom puls (alcatel/mediatek)