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Linux 3.9-rc3
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap2 / cclock33xx_data.c
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b4c63295
VH		 1/*
2 * AM33XX Clock data
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk-private.h>
20#include <linux/clkdev.h>
21#include <linux/io.h>
22
23#include "am33xx.h"
24#include "soc.h"
25#include "iomap.h"
26#include "clock.h"
27#include "control.h"
28#include "cm.h"
29#include "cm33xx.h"
30#include "cm-regbits-33xx.h"
31#include "prm.h"
32
33/* Modulemode control */
34#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
35#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
36
37/*LIST_HEAD(clocks);*/
38
39/* Root clocks */
40
41/* RTC 32k */
42DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
43
44/* On-Chip 32KHz RC OSC */
45DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
46
47/* Crystal input clks */
48DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
49
50DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
51
52DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
53
54DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
55
56/* Oscillator clock */
57/* 19.2, 24, 25 or 26 MHz */
58static const char *sys_clkin_ck_parents[] = {
59 "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
60 "virt_26000000_ck",
61};
62
63/*
64 * sys_clk in: input to the dpll and also used as funtional clock for,
65 * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
66 *
67 */
68DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
69 AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
70 AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
71 AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
72 0, NULL);
73
74/* External clock - 12 MHz */
75DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
76
77/* Module clocks and DPLL outputs */
78
79/* DPLL_CORE */
80static struct dpll_data dpll_core_dd = {
81 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
82 .clk_bypass = &sys_clkin_ck,
83 .clk_ref = &sys_clkin_ck,
84 .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
85 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
86 .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
87 .mult_mask = AM33XX_DPLL_MULT_MASK,
88 .div1_mask = AM33XX_DPLL_DIV_MASK,
89 .enable_mask = AM33XX_DPLL_EN_MASK,
90 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
91 .max_multiplier = 2047,
92 .max_divider = 128,
93 .min_divider = 1,
94};
95
96/* CLKDCOLDO output */
97static const char *dpll_core_ck_parents[] = {
98 "sys_clkin_ck",
99};
100
101static struct clk dpll_core_ck;
102
103static const struct clk_ops dpll_core_ck_ops = {
104 .recalc_rate = &omap3_dpll_recalc,
105 .get_parent = &omap2_init_dpll_parent,
106};
107
108static struct clk_hw_omap dpll_core_ck_hw = {
109 .hw = {
110 .clk = &dpll_core_ck,
111 },
112 .dpll_data = &dpll_core_dd,
113 .ops = &clkhwops_omap3_dpll,
114};
115
116DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
117
118static const char *dpll_core_x2_ck_parents[] = {
119 "dpll_core_ck",
120};
121
122static struct clk dpll_core_x2_ck;
123
124static const struct clk_ops dpll_x2_ck_ops = {
125 .recalc_rate = &omap3_clkoutx2_recalc,
126};
127
128static struct clk_hw_omap dpll_core_x2_ck_hw = {
129 .hw = {
130 .clk = &dpll_core_x2_ck,
131 },
132 .flags = CLOCK_CLKOUTX2,
133};
134
135DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
136
137DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
138 0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
139 AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
140 AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
141 NULL);
142
143DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
144 0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
145 AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
146 AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
147 CLK_DIVIDER_ONE_BASED, NULL);
148
149DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
150 0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
151 AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
152 AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
153 CLK_DIVIDER_ONE_BASED, NULL);
154
155
156/* DPLL_MPU */
157static struct dpll_data dpll_mpu_dd = {
158 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
159 .clk_bypass = &sys_clkin_ck,
160 .clk_ref = &sys_clkin_ck,
161 .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
162 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
163 .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
164 .mult_mask = AM33XX_DPLL_MULT_MASK,
165 .div1_mask = AM33XX_DPLL_DIV_MASK,
166 .enable_mask = AM33XX_DPLL_EN_MASK,
167 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
168 .max_multiplier = 2047,
169 .max_divider = 128,
170 .min_divider = 1,
171};
172
173/* CLKOUT: fdpll/M2 */
174static struct clk dpll_mpu_ck;
175
176static const struct clk_ops dpll_mpu_ck_ops = {
177 .enable = &omap3_noncore_dpll_enable,
178 .disable = &omap3_noncore_dpll_disable,
179 .recalc_rate = &omap3_dpll_recalc,
180 .round_rate = &omap2_dpll_round_rate,
181 .set_rate = &omap3_noncore_dpll_set_rate,
182 .get_parent = &omap2_init_dpll_parent,
183};
184
185static struct clk_hw_omap dpll_mpu_ck_hw = {
186 .hw = {
187 .clk = &dpll_mpu_ck,
188 },
189 .dpll_data = &dpll_mpu_dd,
190 .ops = &clkhwops_omap3_dpll,
191};
192
193DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
194
195/*
196 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
197 * and ALT_CLK1/2)
198 */
199DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
200 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
201 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
202
203/* DPLL_DDR */
204static struct dpll_data dpll_ddr_dd = {
205 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
206 .clk_bypass = &sys_clkin_ck,
207 .clk_ref = &sys_clkin_ck,
208 .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
209 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
210 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
211 .mult_mask = AM33XX_DPLL_MULT_MASK,
212 .div1_mask = AM33XX_DPLL_DIV_MASK,
213 .enable_mask = AM33XX_DPLL_EN_MASK,
214 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
215 .max_multiplier = 2047,
216 .max_divider = 128,
217 .min_divider = 1,
218};
219
220/* CLKOUT: fdpll/M2 */
221static struct clk dpll_ddr_ck;
222
223static const struct clk_ops dpll_ddr_ck_ops = {
224 .recalc_rate = &omap3_dpll_recalc,
225 .get_parent = &omap2_init_dpll_parent,
226 .round_rate = &omap2_dpll_round_rate,
227 .set_rate = &omap3_noncore_dpll_set_rate,
228};
229
230static struct clk_hw_omap dpll_ddr_ck_hw = {
231 .hw = {
232 .clk = &dpll_ddr_ck,
233 },
234 .dpll_data = &dpll_ddr_dd,
235 .ops = &clkhwops_omap3_dpll,
236};
237
238DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
239
240/*
241 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
242 * and ALT_CLK1/2)
243 */
244DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
245 0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
246 AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
247 CLK_DIVIDER_ONE_BASED, NULL);
248
249/* emif_fck functional clock */
250DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
251 0x0, 1, 2);
252
253/* DPLL_DISP */
254static struct dpll_data dpll_disp_dd = {
255 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
256 .clk_bypass = &sys_clkin_ck,
257 .clk_ref = &sys_clkin_ck,
258 .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
259 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
260 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
261 .mult_mask = AM33XX_DPLL_MULT_MASK,
262 .div1_mask = AM33XX_DPLL_DIV_MASK,
263 .enable_mask = AM33XX_DPLL_EN_MASK,
264 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
265 .max_multiplier = 2047,
266 .max_divider = 128,
267 .min_divider = 1,
268};
269
270/* CLKOUT: fdpll/M2 */
271static struct clk dpll_disp_ck;
272
273static struct clk_hw_omap dpll_disp_ck_hw = {
274 .hw = {
275 .clk = &dpll_disp_ck,
276 },
277 .dpll_data = &dpll_disp_dd,
278 .ops = &clkhwops_omap3_dpll,
279};
280
281DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
282
283/*
284 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
285 * and ALT_CLK1/2)
286 */
0c3c22f9
AM		 287DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
288 CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
289 AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
290 CLK_DIVIDER_ONE_BASED, NULL);
b4c63295
VH		 291
292/* DPLL_PER */
293static struct dpll_data dpll_per_dd = {
294 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
295 .clk_bypass = &sys_clkin_ck,
296 .clk_ref = &sys_clkin_ck,
297 .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
298 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
299 .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
300 .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
301 .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
302 .enable_mask = AM33XX_DPLL_EN_MASK,
303 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
304 .max_multiplier = 2047,
305 .max_divider = 128,
306 .min_divider = 1,
307 .flags = DPLL_J_TYPE,
308};
309
310/* CLKDCOLDO */
311static struct clk dpll_per_ck;
312
313static struct clk_hw_omap dpll_per_ck_hw = {
314 .hw = {
315 .clk = &dpll_per_ck,
316 },
317 .dpll_data = &dpll_per_dd,
318 .ops = &clkhwops_omap3_dpll,
319};
320
321DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
322
323/* CLKOUT: fdpll/M2 */
324DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
325 AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
326 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
327 NULL);
328
329DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
330 &dpll_per_m2_ck, 0x0, 1, 4);
331
332DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
333 &dpll_per_m2_ck, 0x0, 1, 4);
334
335DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
336 &dpll_core_m4_ck, 0x0, 1, 2);
337
338DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
339 1, 2);
340
341DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
342 8);
343
344/*
345 * Below clock nodes describes clockdomains derived out
346 * of core clock.
347 */
348static const struct clk_ops clk_ops_null = {
349};
350
351static const char *l3_gclk_parents[] = {
352 "dpll_core_m4_ck"
353};
354
355static struct clk l3_gclk;
356DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
357DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
358
359static struct clk l4hs_gclk;
360DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
361DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
362
363static const char *l3s_gclk_parents[] = {
364 "dpll_core_m4_div2_ck"
365};
366
367static struct clk l3s_gclk;
368DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
369DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
370
371static struct clk l4fw_gclk;
372DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
373DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
374
375static struct clk l4ls_gclk;
376DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
377DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
378
379static struct clk sysclk_div_ck;
380DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
381DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
382
383/*
384 * In order to match the clock domain with hwmod clockdomain entry,
385 * separate clock nodes is required for the modules which are
386 * directly getting their funtioncal clock from sys_clkin.
387 */
388static struct clk adc_tsc_fck;
389DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
390DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
391
392static struct clk dcan0_fck;
393DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
394DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
395
396static struct clk dcan1_fck;
397DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
398DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
399
400static struct clk mcasp0_fck;
401DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
402DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
403
404static struct clk mcasp1_fck;
405DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
406DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
407
408static struct clk smartreflex0_fck;
409DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
410DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
411
412static struct clk smartreflex1_fck;
413DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
414DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
415
416/*
417 * Modules clock nodes
418 *
419 * The following clock leaf nodes are added for the moment because:
420 *
421 * - hwmod data is not present for these modules, either hwmod
422 * control is not required or its not populated.
423 * - Driver code is not yet migrated to use hwmod/runtime pm
424 * - Modules outside kernel access (to disable them by default)
425 *
426 * - debugss
427 * - mmu (gfx domain)
428 * - cefuse
429 * - usbotg_fck (its additional clock and not really a modulemode)
430 * - ieee5000
431 */
432DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
433 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
434 0x0, NULL);
435
436DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
437 AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
438 0x0, NULL);
439
440DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
441 AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
442 0x0, NULL);
443
444/*
445 * clkdiv32 is generated from fixed division of 732.4219
446 */
447DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
448
449DEFINE_CLK_GATE(clkdiv32k_ick, "clkdiv32k_ck", &clkdiv32k_ck, 0x0,
450 AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
451 0x0, NULL);
452
453/* "usbotg_fck" is an additional clock and not really a modulemode */
454DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
455 AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
456 0x0, NULL);
457
458DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
459 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
460 AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
461
462/* Timers */
463static const struct clksel timer1_clkmux_sel[] = {
464 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
465 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
466 { .parent = &tclkin_ck, .rates = div_1_2_rates },
467 { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
468 { .parent = &clk_32768_ck, .rates = div_1_4_rates },
469 { .parent = NULL },
470};
471
472static const char *timer1_ck_parents[] = {
473 "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
474 "clk_32768_ck",
475};
476
477static struct clk timer1_fck;
478
479static const struct clk_ops timer1_fck_ops = {
480 .recalc_rate = &omap2_clksel_recalc,
481 .get_parent = &omap2_clksel_find_parent_index,
482 .set_parent = &omap2_clksel_set_parent,
483 .init = &omap2_init_clk_clkdm,
484};
485
486static struct clk_hw_omap timer1_fck_hw = {
487 .hw = {
488 .clk = &timer1_fck,
489 },
490 .clkdm_name = "l4ls_clkdm",
491 .clksel = timer1_clkmux_sel,
492 .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
493 .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
494};
495
496DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
497
498static const struct clksel timer2_to_7_clk_sel[] = {
499 { .parent = &tclkin_ck, .rates = div_1_0_rates },
500 { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
501 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
502 { .parent = NULL },
503};
504
505static const char *timer2_to_7_ck_parents[] = {
506 "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
507};
508
509static struct clk timer2_fck;
510
511static struct clk_hw_omap timer2_fck_hw = {
512 .hw = {
513 .clk = &timer2_fck,
514 },
515 .clkdm_name = "l4ls_clkdm",
516 .clksel = timer2_to_7_clk_sel,
517 .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
518 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
519};
520
521DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
522
523static struct clk timer3_fck;
524
525static struct clk_hw_omap timer3_fck_hw = {
526 .hw = {
527 .clk = &timer3_fck,
528 },
529 .clkdm_name = "l4ls_clkdm",
530 .clksel = timer2_to_7_clk_sel,
531 .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
532 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
533};
534
535DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
536
537static struct clk timer4_fck;
538
539static struct clk_hw_omap timer4_fck_hw = {
540 .hw = {
541 .clk = &timer4_fck,
542 },
543 .clkdm_name = "l4ls_clkdm",
544 .clksel = timer2_to_7_clk_sel,
545 .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
546 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
547};
548
549DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
550
551static struct clk timer5_fck;
552
553static struct clk_hw_omap timer5_fck_hw = {
554 .hw = {
555 .clk = &timer5_fck,
556 },
557 .clkdm_name = "l4ls_clkdm",
558 .clksel = timer2_to_7_clk_sel,
559 .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
560 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
561};
562
563DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
564
565static struct clk timer6_fck;
566
567static struct clk_hw_omap timer6_fck_hw = {
568 .hw = {
569 .clk = &timer6_fck,
570 },
571 .clkdm_name = "l4ls_clkdm",
572 .clksel = timer2_to_7_clk_sel,
573 .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
574 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
575};
576
577DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
578
579static struct clk timer7_fck;
580
581static struct clk_hw_omap timer7_fck_hw = {
582 .hw = {
583 .clk = &timer7_fck,
584 },
585 .clkdm_name = "l4ls_clkdm",
586 .clksel = timer2_to_7_clk_sel,
587 .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
588 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
589};
590
591DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
592
593DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
594 "dpll_core_m5_ck",
595 &dpll_core_m5_ck,
596 0x0,
597 1, 2);
598
599static const struct clk_ops cpsw_fck_ops = {
600 .recalc_rate = &omap2_clksel_recalc,
601 .get_parent = &omap2_clksel_find_parent_index,
602 .set_parent = &omap2_clksel_set_parent,
603};
604
605static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
606 { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
607 { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
608 { .parent = NULL },
609};
610
611static const char *cpsw_cpts_rft_ck_parents[] = {
612 "dpll_core_m5_ck", "dpll_core_m4_ck",
613};
614
615static struct clk cpsw_cpts_rft_clk;
616
617static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
618 .hw = {
619 .clk = &cpsw_cpts_rft_clk,
620 },
621 .clkdm_name = "cpsw_125mhz_clkdm",
622 .clksel = cpsw_cpts_rft_clkmux_sel,
623 .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
624 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
625};
626
627DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
628
629
630/* gpio */
631static const char *gpio0_ck_parents[] = {
632 "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
633};
634
635static const struct clksel gpio0_dbclk_mux_sel[] = {
636 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
637 { .parent = &clk_32768_ck, .rates = div_1_1_rates },
638 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
639 { .parent = NULL },
640};
641
642static const struct clk_ops gpio_fck_ops = {
643 .recalc_rate = &omap2_clksel_recalc,
644 .get_parent = &omap2_clksel_find_parent_index,
645 .set_parent = &omap2_clksel_set_parent,
646 .init = &omap2_init_clk_clkdm,
647};
648
649static struct clk gpio0_dbclk_mux_ck;
650
651static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
652 .hw = {
653 .clk = &gpio0_dbclk_mux_ck,
654 },
655 .clkdm_name = "l4_wkup_clkdm",
656 .clksel = gpio0_dbclk_mux_sel,
657 .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
658 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
659};
660
661DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
662
663DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
664 AM33XX_CM_WKUP_GPIO0_CLKCTRL,
665 AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
666
667DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
668 AM33XX_CM_PER_GPIO1_CLKCTRL,
669 AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
670
671DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
672 AM33XX_CM_PER_GPIO2_CLKCTRL,
673 AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
674
675DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
676 AM33XX_CM_PER_GPIO3_CLKCTRL,
677 AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
678
679
680static const char *pruss_ck_parents[] = {
681 "l3_gclk", "dpll_disp_m2_ck",
682};
683
684static const struct clksel pruss_ocp_clk_mux_sel[] = {
685 { .parent = &l3_gclk, .rates = div_1_0_rates },
686 { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
687 { .parent = NULL },
688};
689
690static struct clk pruss_ocp_gclk;
691
692static struct clk_hw_omap pruss_ocp_gclk_hw = {
693 .hw = {
694 .clk = &pruss_ocp_gclk,
695 },
696 .clkdm_name = "pruss_ocp_clkdm",
697 .clksel = pruss_ocp_clk_mux_sel,
698 .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
699 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
700};
701
702DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
703
704static const char *lcd_ck_parents[] = {
705 "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
706};
707
708static const struct clksel lcd_clk_mux_sel[] = {
709 { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
710 { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
711 { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
712 { .parent = NULL },
713};
714
715static struct clk lcd_gclk;
716
717static struct clk_hw_omap lcd_gclk_hw = {
718 .hw = {
719 .clk = &lcd_gclk,
720 },
721 .clkdm_name = "lcdc_clkdm",
722 .clksel = lcd_clk_mux_sel,
723 .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
724 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
725};
726
0c3c22f9
AM		 727DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
728 gpio_fck_ops, CLK_SET_RATE_PARENT);
b4c63295
VH		 729
730DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
731
732static const char *gfx_ck_parents[] = {
733 "dpll_core_m4_ck", "dpll_per_m2_ck",
734};
735
736static const struct clksel gfx_clksel_sel[] = {
737 { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
738 { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
739 { .parent = NULL },
740};
741
742static struct clk gfx_fclk_clksel_ck;
743
744static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
745 .hw = {
746 .clk = &gfx_fclk_clksel_ck,
747 },
748 .clksel = gfx_clksel_sel,
749 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
750 .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
751};
752
753DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
754
755static const struct clk_div_table div_1_0_2_1_rates[] = {
756 { .div = 1, .val = 0, },
757 { .div = 2, .val = 1, },
758 { .div = 0 },
759};
760
761DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
762 &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
763 AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
764 0x0, div_1_0_2_1_rates, NULL);
765
766static const char *sysclkout_ck_parents[] = {
767 "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
768 "lcd_gclk",
769};
770
771static const struct clksel sysclkout_pre_sel[] = {
772 { .parent = &clk_32768_ck, .rates = div_1_0_rates },
773 { .parent = &l3_gclk, .rates = div_1_1_rates },
774 { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
775 { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
776 { .parent = &lcd_gclk, .rates = div_1_4_rates },
777 { .parent = NULL },
778};
779
780static struct clk sysclkout_pre_ck;
781
782static struct clk_hw_omap sysclkout_pre_ck_hw = {
783 .hw = {
784 .clk = &sysclkout_pre_ck,
785 },
786 .clksel = sysclkout_pre_sel,
787 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
788 .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
789};
790
791DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
792
793/* Divide by 8 clock rates with default clock is 1/1*/
794static const struct clk_div_table div8_rates[] = {
795 { .div = 1, .val = 0, },
796 { .div = 2, .val = 1, },
797 { .div = 3, .val = 2, },
798 { .div = 4, .val = 3, },
799 { .div = 5, .val = 4, },
800 { .div = 6, .val = 5, },
801 { .div = 7, .val = 6, },
802 { .div = 8, .val = 7, },
803 { .div = 0 },
804};
805
806DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
807 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
808 AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
809
810DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
811 AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
812
813static const char *wdt_ck_parents[] = {
814 "clk_rc32k_ck", "clkdiv32k_ick",
815};
816
817static const struct clksel wdt_clkmux_sel[] = {
818 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
819 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
820 { .parent = NULL },
821};
822
823static struct clk wdt1_fck;
824
825static struct clk_hw_omap wdt1_fck_hw = {
826 .hw = {
827 .clk = &wdt1_fck,
828 },
829 .clkdm_name = "l4_wkup_clkdm",
830 .clksel = wdt_clkmux_sel,
831 .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
832 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
833};
834
835DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
836
837/*
838 * clkdev
839 */
840static struct omap_clk am33xx_clks[] = {
841 CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX),
842 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX),
843 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX),
844 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX),
845 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX),
846 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX),
847 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX),
848 CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX),
849 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX),
850 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX),
851 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX),
852 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
853 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
854 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
855 CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX),
856 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
857 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
858 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
859 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX),
860 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX),
861 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX),
862 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX),
863 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX),
864 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX),
865 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX),
866 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX),
867 CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX),
868 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX),
869 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX),
870 CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX),
871 CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX),
872 CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX),
873 CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX),
874 CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX),
875 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX),
876 CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX),
877 CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX),
878 CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
879 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
880 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
881 CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
882 CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
883 CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
884 CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
885 CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
886 CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
887 CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
888 CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
889 CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
890 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
891 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX),
892 CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX),
893 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX),
894 CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX),
895 CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX),
896 CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX),
897 CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX),
898 CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX),
899 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX),
900 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX),
901 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX),
902 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX),
903 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX),
904 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX),
905 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX),
906 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX),
907 CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX),
908 CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX),
909 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX),
910 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
911 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
912 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX),
913 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
914 CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
915};
916
917
918static const char *enable_init_clks[] = {
919 "dpll_ddr_m2_ck",
920 "dpll_mpu_m2_ck",
921 "l3_gclk",
922 "l4hs_gclk",
923 "l4fw_gclk",
924 "l4ls_gclk",
925};
926
927int __init am33xx_clk_init(void)
928{
929 struct omap_clk *c;
930 u32 cpu_clkflg;
931
932 if (soc_is_am33xx()) {
933 cpu_mask = RATE_IN_AM33XX;
934 cpu_clkflg = CK_AM33XX;
935 }
936
937 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
938 if (c->cpu & cpu_clkflg) {
939 clkdev_add(&c->lk);
940 if (!__clk_init(NULL, c->lk.clk))
941 omap2_init_clk_hw_omap_clocks(c->lk.clk);
942 }
943 }
944
945 omap2_clk_disable_autoidle_all();
946
947 omap2_clk_enable_init_clocks(enable_init_clks,
948 ARRAY_SIZE(enable_init_clks));
949
950 /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
951 * physically present, in such a case HWMOD enabling of
952 * clock would be failure with default parent. And timer
953 * probe thinks clock is already enabled, this leads to
954 * crash upon accessing timer 3 & 6 registers in probe.
955 * Fix by setting parent of both these timers to master
956 * oscillator clock.
957 */
958
959 clk_set_parent(&timer3_fck, &sys_clkin_ck);
960 clk_set_parent(&timer6_fck, &sys_clkin_ck);
961
962 return 0;
963}
kernel source for telekom puls (alcatel/mediatek)