[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-omap1 / irq.c

/*
 * linux/arch/arm/mach-omap1/irq.c
 *
 * Interrupt handler for all OMAP boards
 *
 * Copyright (C) 2004 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
 *
 * Completely re-written to support various OMAP chips with bank specific
 * interrupt handlers.
 *
 * Some snippets of the code taken from the older OMAP interrupt handler
 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
 *
 * GPIO interrupt handler moved to gpio.c by Juha Yrjola
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/interrupt.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <mach/gpio.h>
#include <mach/cpu.h>

#include <asm/io.h>

#define IRQ_BANK(irq) ((irq) >> 5)
#define IRQ_BIT(irq)  ((irq) & 0x1f)

struct omap_irq_bank {
	unsigned long base_reg;
	unsigned long trigger_map;
	unsigned long wake_enable;
};

static unsigned int irq_bank_count;
static struct omap_irq_bank *irq_banks;

static inline unsigned int irq_bank_readl(int bank, int offset)
{
	return omap_readl(irq_banks[bank].base_reg + offset);
}

static inline void irq_bank_writel(unsigned long value, int bank, int offset)
{
	omap_writel(value, irq_banks[bank].base_reg + offset);
}

static void omap_ack_irq(unsigned int irq)
{
	if (irq > 31)
		omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);

	omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
}

static void omap_mask_irq(unsigned int irq)
{
	int bank = IRQ_BANK(irq);
	u32 l;

	l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
	l |= 1 << IRQ_BIT(irq);
	omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}

static void omap_unmask_irq(unsigned int irq)
{
	int bank = IRQ_BANK(irq);
	u32 l;

	l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
	l &= ~(1 << IRQ_BIT(irq));
	omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}

static void omap_mask_ack_irq(unsigned int irq)
{
	omap_mask_irq(irq);
	omap_ack_irq(irq);
}

static int omap_wake_irq(unsigned int irq, unsigned int enable)
{
	int bank = IRQ_BANK(irq);

	if (enable)
		irq_banks[bank].wake_enable |= IRQ_BIT(irq);
	else
		irq_banks[bank].wake_enable &= ~IRQ_BIT(irq);

	return 0;
}


/*
 * Allows tuning the IRQ type and priority
 *
 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
 *	 mailing list threads on FIQ handlers if you are planning to
 *	 add a FIQ handler for OMAP.
 */
static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
{
	signed int bank;
	unsigned long val, offset;

	bank = IRQ_BANK(irq);
	/* FIQ is only available on bank 0 interrupts */
	fiq = bank ? 0 : (fiq & 0x1);
	val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
	offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
	irq_bank_writel(val, bank, offset);
}

#ifdef CONFIG_ARCH_OMAP730
static struct omap_irq_bank omap730_irq_banks[] = {
	{ .base_reg = OMAP_IH1_BASE,		.trigger_map = 0xb3f8e22f },
	{ .base_reg = OMAP_IH2_BASE,		.trigger_map = 0xfdb9c1f2 },
	{ .base_reg = OMAP_IH2_BASE + 0x100,	.trigger_map = 0x800040f3 },
};
#endif

#ifdef CONFIG_ARCH_OMAP15XX
static struct omap_irq_bank omap1510_irq_banks[] = {
	{ .base_reg = OMAP_IH1_BASE,		.trigger_map = 0xb3febfff },
	{ .base_reg = OMAP_IH2_BASE,		.trigger_map = 0xffbfffed },
};
static struct omap_irq_bank omap310_irq_banks[] = {
	{ .base_reg = OMAP_IH1_BASE,		.trigger_map = 0xb3faefc3 },
	{ .base_reg = OMAP_IH2_BASE,		.trigger_map = 0x65b3c061 },
};
#endif

#if defined(CONFIG_ARCH_OMAP16XX)

static struct omap_irq_bank omap1610_irq_banks[] = {
	{ .base_reg = OMAP_IH1_BASE,		.trigger_map = 0xb3fefe8f },
	{ .base_reg = OMAP_IH2_BASE,		.trigger_map = 0xfdb7c1fd },
	{ .base_reg = OMAP_IH2_BASE + 0x100,	.trigger_map = 0xffffb7ff },
	{ .base_reg = OMAP_IH2_BASE + 0x200,	.trigger_map = 0xffffffff },
};
#endif

static struct irq_chip omap_irq_chip = {
	.name		= "MPU",
	.ack		= omap_mask_ack_irq,
	.mask		= omap_mask_irq,
	.unmask		= omap_unmask_irq,
	.set_wake	= omap_wake_irq,
};

void __init omap_init_irq(void)
{
	int i, j;

#ifdef CONFIG_ARCH_OMAP730
	if (cpu_is_omap730()) {
		irq_banks = omap730_irq_banks;
		irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
	}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
	if (cpu_is_omap1510()) {
		irq_banks = omap1510_irq_banks;
		irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
	}
	if (cpu_is_omap310()) {
		irq_banks = omap310_irq_banks;
		irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
	}
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
	if (cpu_is_omap16xx()) {
		irq_banks = omap1610_irq_banks;
		irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
	}
#endif
	printk("Total of %i interrupts in %i interrupt banks\n",
	       irq_bank_count * 32, irq_bank_count);

	/* Mask and clear all interrupts */
	for (i = 0; i < irq_bank_count; i++) {
		irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
		irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
	}

	/* Clear any pending interrupts */
	irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
	irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);

	/* Enable interrupts in global mask */
	if (cpu_is_omap730()) {
		irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
	}

	/* Install the interrupt handlers for each bank */
	for (i = 0; i < irq_bank_count; i++) {
		for (j = i * 32; j < (i + 1) * 32; j++) {
			int irq_trigger;

			irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
			omap_irq_set_cfg(j, 0, 0, irq_trigger);

			set_irq_chip(j, &omap_irq_chip);
			set_irq_handler(j, handle_level_irq);
			set_irq_flags(j, IRQF_VALID);
		}
	}

	/* Unmask level 2 handler */

	if (cpu_is_omap730())
		omap_unmask_irq(INT_730_IH2_IRQ);
	else if (cpu_is_omap15xx())
		omap_unmask_irq(INT_1510_IH2_IRQ);
	else if (cpu_is_omap16xx())
		omap_unmask_irq(INT_1610_IH2_IRQ);
}
Commit	Line	Data
1da177e4	1	/*
7c38cf02	2	* linux/arch/arm/mach-omap1/irq.c
1da177e4 LT	3	*
	4	* Interrupt handler for all OMAP boards
	5	*
	6	* Copyright (C) 2004 Nokia Corporation
	7	* Written by Tony Lindgren <tony@atomide.com>
96de0e25	8	* Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
1da177e4 LT	9	*
	10	* Completely re-written to support various OMAP chips with bank specific
	11	* interrupt handlers.
	12	*
	13	* Some snippets of the code taken from the older OMAP interrupt handler
	14	* Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
	15	*
	16	* GPIO interrupt handler moved to gpio.c by Juha Yrjola
	17	*
	18	* This program is free software; you can redistribute it and/or modify it
	19	* under the terms of the GNU General Public License as published by the
	20	* Free Software Foundation; either version 2 of the License, or (at your
	21	* option) any later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	24	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	25	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	26	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	27	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	28	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	29	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	30	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	32	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*
	34	* You should have received a copy of the GNU General Public License along
	35	* with this program; if not, write to the Free Software Foundation, Inc.,
	36	* 675 Mass Ave, Cambridge, MA 02139, USA.
	37	*/
	38
1da177e4 LT	39	#include <linux/init.h>
	40	#include <linux/module.h>
	41	#include <linux/sched.h>
	42	#include <linux/interrupt.h>
1da177e4	43
a09e64fb	44	#include <mach/hardware.h>
1da177e4 LT	45	#include <asm/irq.h>
1da177e4 LT	46	#include <asm/mach/irq.h>
a09e64fb RK	47	#include <mach/gpio.h>
a09e64fb RK	48	#include <mach/cpu.h>
1da177e4 LT	49
	50	#include <asm/io.h>
	51
	52	#define IRQ_BANK(irq) ((irq) >> 5)
	53	#define IRQ_BIT(irq) ((irq) & 0x1f)
	54
	55	struct omap_irq_bank {
	56	unsigned long base_reg;
	57	unsigned long trigger_map;
3b59b6be	58	unsigned long wake_enable;
1da177e4 LT	59	};
1da177e4 LT	60
120db2cb	61	static unsigned int irq_bank_count;
1da177e4 LT	62	static struct omap_irq_bank *irq_banks;
	63
	64	static inline unsigned int irq_bank_readl(int bank, int offset)
	65	{
	66	return omap_readl(irq_banks[bank].base_reg + offset);
	67	}
	68
	69	static inline void irq_bank_writel(unsigned long value, int bank, int offset)
	70	{
	71	omap_writel(value, irq_banks[bank].base_reg + offset);
	72	}
	73
	74	static void omap_ack_irq(unsigned int irq)
	75	{
	76	if (irq > 31)
	77	omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
	78
	79	omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
	80	}
	81
	82	static void omap_mask_irq(unsigned int irq)
	83	{
	84	int bank = IRQ_BANK(irq);
	85	u32 l;
	86
	87	l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
	88	l \|= 1 << IRQ_BIT(irq);
	89	omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
	90	}
	91
	92	static void omap_unmask_irq(unsigned int irq)
	93	{
	94	int bank = IRQ_BANK(irq);
	95	u32 l;
	96
	97	l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
	98	l &= ~(1 << IRQ_BIT(irq));
	99	omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
	100	}
	101
	102	static void omap_mask_ack_irq(unsigned int irq)
	103	{
	104	omap_mask_irq(irq);
	105	omap_ack_irq(irq);
	106	}
	107
3b59b6be TL	108	static int omap_wake_irq(unsigned int irq, unsigned int enable)
	109	{
	110	int bank = IRQ_BANK(irq);
	111
	112	if (enable)
	113	irq_banks[bank].wake_enable \|= IRQ_BIT(irq);
	114	else
	115	irq_banks[bank].wake_enable &= ~IRQ_BIT(irq);
	116
	117	return 0;
	118	}
	119
	120
1da177e4 LT	121	/*
	122	* Allows tuning the IRQ type and priority
	123	*
	124	* NOTE: There is currently no OMAP fiq handler for Linux. Read the
	125	* mailing list threads on FIQ handlers if you are planning to
	126	* add a FIQ handler for OMAP.
	127	*/
	128	static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
	129	{
	130	signed int bank;
	131	unsigned long val, offset;
	132
	133	bank = IRQ_BANK(irq);
	134	/* FIQ is only available on bank 0 interrupts */
	135	fiq = bank ? 0 : (fiq & 0x1);
	136	val = fiq \| ((priority & 0x1f) << 2) \| ((trigger & 0x1) << 1);
	137	offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
	138	irq_bank_writel(val, bank, offset);
	139	}
	140
	141	#ifdef CONFIG_ARCH_OMAP730
	142	static struct omap_irq_bank omap730_irq_banks[] = {
120db2cb TL	143	{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
120db2cb TL	144	{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
1da177e4 LT	145	{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
	146	};
	147	#endif
	148
3179a019	149	#ifdef CONFIG_ARCH_OMAP15XX
1da177e4	150	static struct omap_irq_bank omap1510_irq_banks[] = {
120db2cb TL	151	{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
120db2cb TL	152	{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
1da177e4	153	};
3179a019	154	static struct omap_irq_bank omap310_irq_banks[] = {
120db2cb TL	155	{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
120db2cb TL	156	{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
3179a019	157	};
1da177e4 LT	158	#endif
	159
	160	#if defined(CONFIG_ARCH_OMAP16XX)
	161
	162	static struct omap_irq_bank omap1610_irq_banks[] = {
120db2cb TL	163	{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
120db2cb TL	164	{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
3b59b6be	165	{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
1da177e4 LT	166	{ .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
	167	};
	168	#endif
	169
38c677cb DB	170	static struct irq_chip omap_irq_chip = {
38c677cb DB	171	.name = "MPU",
2be863c9 RK	172	.ack = omap_mask_ack_irq,
	173	.mask = omap_mask_irq,
	174	.unmask = omap_unmask_irq,
	175	.set_wake = omap_wake_irq,
1da177e4 LT	176	};
	177
	178	void __init omap_init_irq(void)
	179	{
	180	int i, j;
	181
	182	#ifdef CONFIG_ARCH_OMAP730
	183	if (cpu_is_omap730()) {
	184	irq_banks = omap730_irq_banks;
	185	irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
	186	}
	187	#endif
3179a019	188	#ifdef CONFIG_ARCH_OMAP15XX
1da177e4 LT	189	if (cpu_is_omap1510()) {
	190	irq_banks = omap1510_irq_banks;
	191	irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
	192	}
3179a019 TL	193	if (cpu_is_omap310()) {
	194	irq_banks = omap310_irq_banks;
	195	irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
	196	}
1da177e4 LT	197	#endif
	198	#if defined(CONFIG_ARCH_OMAP16XX)
	199	if (cpu_is_omap16xx()) {
	200	irq_banks = omap1610_irq_banks;
	201	irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
	202	}
	203	#endif
	204	printk("Total of %i interrupts in %i interrupt banks\n",
	205	irq_bank_count * 32, irq_bank_count);
	206
	207	/* Mask and clear all interrupts */
	208	for (i = 0; i < irq_bank_count; i++) {
	209	irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
	210	irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
	211	}
	212
	213	/* Clear any pending interrupts */
	214	irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
	215	irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
	216
	217	/* Enable interrupts in global mask */
	218	if (cpu_is_omap730()) {
	219	irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
	220	}
	221
	222	/* Install the interrupt handlers for each bank */
	223	for (i = 0; i < irq_bank_count; i++) {
	224	for (j = i * 32; j < (i + 1) * 32; j++) {
	225	int irq_trigger;
	226
	227	irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
	228	omap_irq_set_cfg(j, 0, 0, irq_trigger);
	229
	230	set_irq_chip(j, &omap_irq_chip);
10dd5ce2	231	set_irq_handler(j, handle_level_irq);
1da177e4 LT	232	set_irq_flags(j, IRQF_VALID);
	233	}
	234	}
	235
	236	/* Unmask level 2 handler */
3179a019 TL	237
3179a019 TL	238	if (cpu_is_omap730())
1da177e4	239	omap_unmask_irq(INT_730_IH2_IRQ);
ef557d76	240	else if (cpu_is_omap15xx())
3179a019 TL	241	omap_unmask_irq(INT_1510_IH2_IRQ);
	242	else if (cpu_is_omap16xx())
	243	omap_unmask_irq(INT_1610_IH2_IRQ);
1da177e4	244	}