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fd6ac7bb DT |
1 | /* |
2 | * Copyright 2006 Freescale Semiconductor, Inc. | |
3 | * Copyright 2006-2007 Motorola, Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
fd6ac7bb DT |
14 | */ |
15 | ||
16 | #ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ | |
17 | #define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ | |
18 | ||
19 | #define CKIL_CLK_FREQ 32768 | |
20 | ||
21 | #define MXC_CRM_AP_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR) | |
22 | #define MXC_CRM_COM_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR) | |
23 | #define MXC_DSM_BASE MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR) | |
24 | #define MXC_PLL0_BASE MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR) | |
25 | #define MXC_PLL1_BASE MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR) | |
26 | #define MXC_PLL2_BASE MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR) | |
27 | #define MXC_CLKCTL_BASE MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR) | |
28 | ||
29 | /* PLL Register Offsets */ | |
30 | #define MXC_PLL_DP_CTL 0x00 | |
31 | #define MXC_PLL_DP_CONFIG 0x04 | |
32 | #define MXC_PLL_DP_OP 0x08 | |
33 | #define MXC_PLL_DP_MFD 0x0C | |
34 | #define MXC_PLL_DP_MFN 0x10 | |
35 | #define MXC_PLL_DP_HFS_OP 0x1C | |
36 | #define MXC_PLL_DP_HFS_MFD 0x20 | |
37 | #define MXC_PLL_DP_HFS_MFN 0x24 | |
38 | ||
39 | /* PLL Register Bit definitions */ | |
40 | #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 | |
41 | #define MXC_PLL_DP_CTL_ADE 0x800 | |
42 | #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 | |
43 | #define MXC_PLL_DP_CTL_HFSM 0x80 | |
44 | #define MXC_PLL_DP_CTL_PRE 0x40 | |
45 | #define MXC_PLL_DP_CTL_UPEN 0x20 | |
46 | #define MXC_PLL_DP_CTL_RST 0x10 | |
47 | #define MXC_PLL_DP_CTL_RCP 0x8 | |
48 | #define MXC_PLL_DP_CTL_PLM 0x4 | |
49 | #define MXC_PLL_DP_CTL_BRM0 0x2 | |
50 | #define MXC_PLL_DP_CTL_LRF 0x1 | |
51 | ||
52 | #define MXC_PLL_DP_OP_MFI_OFFSET 4 | |
53 | #define MXC_PLL_DP_OP_MFI_MASK 0xF | |
54 | #define MXC_PLL_DP_OP_PDF_OFFSET 0 | |
55 | #define MXC_PLL_DP_OP_PDF_MASK 0xF | |
56 | ||
57 | #define MXC_PLL_DP_MFD_OFFSET 0 | |
58 | #define MXC_PLL_DP_MFD_MASK 0x7FFFFFF | |
59 | ||
60 | #define MXC_PLL_DP_MFN_OFFSET 0 | |
61 | #define MXC_PLL_DP_MFN_MASK 0x7FFFFFF | |
62 | ||
63 | /* CRM AP Register Offsets */ | |
64 | #define MXC_CRMAP_ASCSR (MXC_CRM_AP_BASE + 0x00) | |
65 | #define MXC_CRMAP_ACDR (MXC_CRM_AP_BASE + 0x04) | |
66 | #define MXC_CRMAP_ACDER1 (MXC_CRM_AP_BASE + 0x08) | |
67 | #define MXC_CRMAP_ACDER2 (MXC_CRM_AP_BASE + 0x0C) | |
68 | #define MXC_CRMAP_ACGCR (MXC_CRM_AP_BASE + 0x10) | |
69 | #define MXC_CRMAP_ACCGCR (MXC_CRM_AP_BASE + 0x14) | |
70 | #define MXC_CRMAP_AMLPMRA (MXC_CRM_AP_BASE + 0x18) | |
71 | #define MXC_CRMAP_AMLPMRB (MXC_CRM_AP_BASE + 0x1C) | |
72 | #define MXC_CRMAP_AMLPMRC (MXC_CRM_AP_BASE + 0x20) | |
73 | #define MXC_CRMAP_AMLPMRD (MXC_CRM_AP_BASE + 0x24) | |
74 | #define MXC_CRMAP_AMLPMRE1 (MXC_CRM_AP_BASE + 0x28) | |
75 | #define MXC_CRMAP_AMLPMRE2 (MXC_CRM_AP_BASE + 0x2C) | |
76 | #define MXC_CRMAP_AMLPMRF (MXC_CRM_AP_BASE + 0x30) | |
77 | #define MXC_CRMAP_AMLPMRG (MXC_CRM_AP_BASE + 0x34) | |
78 | #define MXC_CRMAP_APGCR (MXC_CRM_AP_BASE + 0x38) | |
79 | #define MXC_CRMAP_ACSR (MXC_CRM_AP_BASE + 0x3C) | |
80 | #define MXC_CRMAP_ADCR (MXC_CRM_AP_BASE + 0x40) | |
81 | #define MXC_CRMAP_ACR (MXC_CRM_AP_BASE + 0x44) | |
82 | #define MXC_CRMAP_AMCR (MXC_CRM_AP_BASE + 0x48) | |
83 | #define MXC_CRMAP_APCR (MXC_CRM_AP_BASE + 0x4C) | |
84 | #define MXC_CRMAP_AMORA (MXC_CRM_AP_BASE + 0x50) | |
85 | #define MXC_CRMAP_AMORB (MXC_CRM_AP_BASE + 0x54) | |
86 | #define MXC_CRMAP_AGPR (MXC_CRM_AP_BASE + 0x58) | |
87 | #define MXC_CRMAP_APRA (MXC_CRM_AP_BASE + 0x5C) | |
88 | #define MXC_CRMAP_APRB (MXC_CRM_AP_BASE + 0x60) | |
89 | #define MXC_CRMAP_APOR (MXC_CRM_AP_BASE + 0x64) | |
90 | #define MXC_CRMAP_ADFMR (MXC_CRM_AP_BASE + 0x68) | |
91 | ||
92 | /* CRM AP Register Bit definitions */ | |
93 | #define MXC_CRMAP_ASCSR_CRS 0x10000 | |
94 | #define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET 15 | |
95 | #define MXC_CRMAP_ASCSR_AP_PATREF_DIV2 0x8000 | |
96 | #define MXC_CRMAP_ASCSR_USBSEL_OFFSET 13 | |
97 | #define MXC_CRMAP_ASCSR_USBSEL_MASK (0x3 << 13) | |
98 | #define MXC_CRMAP_ASCSR_CSISEL_OFFSET 11 | |
99 | #define MXC_CRMAP_ASCSR_CSISEL_MASK (0x3 << 11) | |
100 | #define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET 7 | |
101 | #define MXC_CRMAP_ASCSR_SSI2SEL_MASK (0x3 << 7) | |
102 | #define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET 5 | |
103 | #define MXC_CRMAP_ASCSR_SSI1SEL_MASK (0x3 << 5) | |
104 | #define MXC_CRMAP_ASCSR_APSEL_OFFSET 3 | |
105 | #define MXC_CRMAP_ASCSR_APSEL_MASK (0x3 << 3) | |
106 | #define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET 2 | |
107 | #define MXC_CRMAP_ASCSR_AP_PATREF_DIV1 0x4 | |
108 | #define MXC_CRMAP_ASCSR_APISEL 0x1 | |
109 | ||
110 | #define MXC_CRMAP_ACDR_ARMDIV_OFFSET 8 | |
111 | #define MXC_CRMAP_ACDR_ARMDIV_MASK (0xF << 8) | |
112 | #define MXC_CRMAP_ACDR_AHBDIV_OFFSET 4 | |
113 | #define MXC_CRMAP_ACDR_AHBDIV_MASK (0xF << 4) | |
114 | #define MXC_CRMAP_ACDR_IPDIV_OFFSET 0 | |
115 | #define MXC_CRMAP_ACDR_IPDIV_MASK 0xF | |
116 | ||
117 | #define MXC_CRMAP_ACDER1_CSIEN_OFFSET 30 | |
118 | #define MXC_CRMAP_ACDER1_CSIDIV_OFFSET 24 | |
119 | #define MXC_CRMAP_ACDER1_CSIDIV_MASK (0x3F << 24) | |
120 | #define MXC_CRMAP_ACDER1_SSI2EN_OFFSET 14 | |
121 | #define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET 8 | |
122 | #define MXC_CRMAP_ACDER1_SSI2DIV_MASK (0x3F << 8) | |
123 | #define MXC_CRMAP_ACDER1_SSI1EN_OFFSET 6 | |
124 | #define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET 0 | |
125 | #define MXC_CRMAP_ACDER1_SSI1DIV_MASK 0x3F | |
126 | ||
127 | #define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET 24 | |
128 | #define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK (0x7 << 24) | |
129 | #define MXC_CRMAP_ACDER2_NFCEN_OFFSET 20 | |
130 | #define MXC_CRMAP_ACDER2_NFCDIV_OFFSET 16 | |
131 | #define MXC_CRMAP_ACDER2_NFCDIV_MASK (0xF << 16) | |
132 | #define MXC_CRMAP_ACDER2_USBEN_OFFSET 12 | |
133 | #define MXC_CRMAP_ACDER2_USBDIV_OFFSET 8 | |
134 | #define MXC_CRMAP_ACDER2_USBDIV_MASK (0xF << 8) | |
135 | #define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET 5 | |
136 | #define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK (0x3 << 5) | |
137 | #define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET 0 | |
138 | #define MXC_CRMAP_ACDER2_BAUDDIV_MASK 0xF | |
139 | ||
140 | #define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET 22 | |
141 | #define MXC_CRMAP_AMLPMRA_MLPMA7_MASK (0x7 << 22) | |
142 | #define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET 19 | |
143 | #define MXC_CRMAP_AMLPMRA_MLPMA6_MASK (0x7 << 19) | |
144 | #define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET 12 | |
145 | #define MXC_CRMAP_AMLPMRA_MLPMA4_MASK (0x7 << 12) | |
146 | #define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET 9 | |
147 | #define MXC_CRMAP_AMLPMRA_MLPMA3_MASK (0x7 << 9) | |
148 | #define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET 6 | |
149 | #define MXC_CRMAP_AMLPMRA_MLPMA2_MASK (0x7 << 6) | |
150 | #define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET 3 | |
151 | #define MXC_CRMAP_AMLPMRA_MLPMA1_MASK (0x7 << 3) | |
152 | ||
153 | #define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET 0 | |
154 | #define MXC_CRMAP_AMLPMRB_MLPMB0_MASK 0x7 | |
155 | ||
156 | #define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET 28 | |
157 | #define MXC_CRMAP_AMLPMRC_MLPMC9_MASK (0x7 << 28) | |
158 | #define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET 22 | |
159 | #define MXC_CRMAP_AMLPMRC_MLPMC7_MASK (0x7 << 22) | |
160 | #define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET 16 | |
161 | #define MXC_CRMAP_AMLPMRC_MLPMC5_MASK (0x7 << 16) | |
162 | #define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET 12 | |
163 | #define MXC_CRMAP_AMLPMRC_MLPMC4_MASK (0x7 << 12) | |
164 | #define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET 9 | |
165 | #define MXC_CRMAP_AMLPMRC_MLPMC3_MASK (0x7 << 9) | |
166 | #define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET 6 | |
167 | #define MXC_CRMAP_AMLPMRC_MLPMC2_MASK (0x7 << 6) | |
168 | #define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET 3 | |
169 | #define MXC_CRMAP_AMLPMRC_MLPMC1_MASK (0x7 << 3) | |
170 | #define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET 0 | |
171 | #define MXC_CRMAP_AMLPMRC_MLPMC0_MASK 0x7 | |
172 | ||
173 | #define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET 22 | |
174 | #define MXC_CRMAP_AMLPMRD_MLPMD7_MASK (0x7 << 22) | |
175 | #define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET 12 | |
176 | #define MXC_CRMAP_AMLPMRD_MLPMD4_MASK (0x7 << 12) | |
177 | #define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET 9 | |
178 | #define MXC_CRMAP_AMLPMRD_MLPMD3_MASK (0x7 << 9) | |
179 | #define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET 6 | |
180 | #define MXC_CRMAP_AMLPMRD_MLPMD2_MASK (0x7 << 6) | |
181 | #define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET 0 | |
182 | #define MXC_CRMAP_AMLPMRD_MLPMD0_MASK 0x7 | |
183 | ||
184 | #define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET 28 | |
185 | #define MXC_CRMAP_AMLPMRE1_MLPME9_MASK (0x7 << 28) | |
186 | #define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET 25 | |
187 | #define MXC_CRMAP_AMLPMRE1_MLPME8_MASK (0x7 << 25) | |
188 | #define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET 22 | |
189 | #define MXC_CRMAP_AMLPMRE1_MLPME7_MASK (0x7 << 22) | |
190 | #define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET 19 | |
191 | #define MXC_CRMAP_AMLPMRE1_MLPME6_MASK (0x7 << 19) | |
192 | #define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET 16 | |
193 | #define MXC_CRMAP_AMLPMRE1_MLPME5_MASK (0x7 << 16) | |
194 | #define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET 12 | |
195 | #define MXC_CRMAP_AMLPMRE1_MLPME4_MASK (0x7 << 12) | |
196 | #define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET 9 | |
197 | #define MXC_CRMAP_AMLPMRE1_MLPME3_MASK (0x7 << 9) | |
198 | #define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET 6 | |
199 | #define MXC_CRMAP_AMLPMRE1_MLPME2_MASK (0x7 << 6) | |
200 | #define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET 3 | |
201 | #define MXC_CRMAP_AMLPMRE1_MLPME1_MASK (0x7 << 3) | |
202 | #define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET 0 | |
203 | #define MXC_CRMAP_AMLPMRE1_MLPME0_MASK 0x7 | |
204 | ||
205 | #define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET 0 | |
206 | #define MXC_CRMAP_AMLPMRE2_MLPME0_MASK 0x7 | |
207 | ||
208 | #define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET 19 | |
209 | #define MXC_CRMAP_AMLPMRF_MLPMF6_MASK (0x7 << 19) | |
210 | #define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET 16 | |
211 | #define MXC_CRMAP_AMLPMRF_MLPMF5_MASK (0x7 << 16) | |
212 | #define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET 9 | |
213 | #define MXC_CRMAP_AMLPMRF_MLPMF3_MASK (0x7 << 9) | |
214 | #define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET 6 | |
215 | #define MXC_CRMAP_AMLPMRF_MLPMF2_MASK (0x7 << 6) | |
216 | #define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET 3 | |
217 | #define MXC_CRMAP_AMLPMRF_MLPMF1_MASK (0x7 << 3) | |
218 | #define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET 0 | |
219 | #define MXC_CRMAP_AMLPMRF_MLPMF0_MASK (0x7 << 0) | |
220 | ||
221 | #define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET 28 | |
222 | #define MXC_CRMAP_AMLPMRG_MLPMG9_MASK (0x7 << 28) | |
223 | #define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET 22 | |
224 | #define MXC_CRMAP_AMLPMRG_MLPMG7_MASK (0x7 << 22) | |
225 | #define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET 19 | |
226 | #define MXC_CRMAP_AMLPMRG_MLPMG6_MASK (0x7 << 19) | |
227 | #define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET 16 | |
228 | #define MXC_CRMAP_AMLPMRG_MLPMG5_MASK (0x7 << 16) | |
229 | #define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET 12 | |
230 | #define MXC_CRMAP_AMLPMRG_MLPMG4_MASK (0x7 << 12) | |
231 | #define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET 9 | |
232 | #define MXC_CRMAP_AMLPMRG_MLPMG3_MASK (0x7 << 9) | |
233 | #define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET 6 | |
234 | #define MXC_CRMAP_AMLPMRG_MLPMG2_MASK (0x7 << 6) | |
235 | #define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET 3 | |
236 | #define MXC_CRMAP_AMLPMRG_MLPMG1_MASK (0x7 << 3) | |
237 | #define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET 0 | |
238 | #define MXC_CRMAP_AMLPMRG_MLPMG0_MASK 0x7 | |
239 | ||
240 | #define MXC_CRMAP_AGPR_IPUPAD_OFFSET 20 | |
241 | #define MXC_CRMAP_AGPR_IPUPAD_MASK (0x7 << 20) | |
242 | ||
243 | #define MXC_CRMAP_APRA_EL1TEN_OFFSET 29 | |
244 | #define MXC_CRMAP_APRA_SIMEN_OFFSET 24 | |
245 | #define MXC_CRMAP_APRA_UART3DIV_OFFSET 17 | |
246 | #define MXC_CRMAP_APRA_UART3DIV_MASK (0xF << 17) | |
247 | #define MXC_CRMAP_APRA_UART3EN_OFFSET 16 | |
248 | #define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14 | |
249 | #define MXC_CRMAP_APRA_MQSPIEN_OFFSET 13 | |
250 | #define MXC_CRMAP_APRA_UART2EN_OFFSET 8 | |
251 | #define MXC_CRMAP_APRA_UART1EN_OFFSET 0 | |
252 | ||
253 | #define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET 13 | |
254 | #define MXC_CRMAP_APRB_SDHC2_ISEL_MASK (0x7 << 13) | |
255 | #define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET 9 | |
256 | #define MXC_CRMAP_APRB_SDHC2_DIV_MASK (0xF << 9) | |
257 | #define MXC_CRMAP_APRB_SDHC2EN_OFFSET 8 | |
258 | #define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET 5 | |
259 | #define MXC_CRMAP_APRB_SDHC1_ISEL_MASK (0x7 << 5) | |
260 | #define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET 1 | |
261 | #define MXC_CRMAP_APRB_SDHC1_DIV_MASK (0xF << 1) | |
262 | #define MXC_CRMAP_APRB_SDHC1EN_OFFSET 0 | |
263 | ||
264 | #define MXC_CRMAP_ACSR_ADS_OFFSET 8 | |
265 | #define MXC_CRMAP_ACSR_ADS (0x1 << 8) | |
266 | #define MXC_CRMAP_ACSR_ACS 0x1 | |
267 | ||
268 | #define MXC_CRMAP_ADCR_LFDF_0 (0x0 << 8) | |
269 | #define MXC_CRMAP_ADCR_LFDF_2 (0x1 << 8) | |
270 | #define MXC_CRMAP_ADCR_LFDF_4 (0x2 << 8) | |
271 | #define MXC_CRMAP_ADCR_LFDF_8 (0x3 << 8) | |
272 | #define MXC_CRMAP_ADCR_LFDF_OFFSET 8 | |
273 | #define MXC_CRMAP_ADCR_LFDF_MASK (0x3 << 8) | |
274 | #define MXC_CRMAP_ADCR_ALT_PLL 0x80 | |
275 | #define MXC_CRMAP_ADCR_DFS_DIVEN 0x20 | |
276 | #define MXC_CRMAP_ADCR_DIV_BYP 0x2 | |
277 | #define MXC_CRMAP_ADCR_VSTAT 0x8 | |
278 | #define MXC_CRMAP_ADCR_TSTAT 0x10 | |
279 | #define MXC_CRMAP_ADCR_DVFS_VCTRL 0x10 | |
280 | #define MXC_CRMAP_ADCR_CLK_ON 0x40 | |
281 | ||
282 | #define MXC_CRMAP_ADFMR_FC_OFFSET 16 | |
283 | #define MXC_CRMAP_ADFMR_FC_MASK (0x1F << 16) | |
284 | #define MXC_CRMAP_ADFMR_MF_OFFSET 1 | |
285 | #define MXC_CRMAP_ADFMR_MF_MASK (0x3FF << 1) | |
286 | #define MXC_CRMAP_ADFMR_DFM_CLK_READY 0x1 | |
287 | #define MXC_CRMAP_ADFMR_DFM_PWR_DOWN 0x8000 | |
288 | ||
289 | #define MXC_CRMAP_ACR_CKOHS_HIGH (1 << 18) | |
290 | #define MXC_CRMAP_ACR_CKOS_HIGH (1 << 16) | |
291 | #define MXC_CRMAP_ACR_CKOHS_MASK (0x7 << 12) | |
292 | #define MXC_CRMAP_ACR_CKOHD (1 << 11) | |
293 | #define MXC_CRMAP_ACR_CKOHDIV_MASK (0xF << 8) | |
294 | #define MXC_CRMAP_ACR_CKOHDIV_OFFSET 8 | |
295 | #define MXC_CRMAP_ACR_CKOD (1 << 7) | |
296 | #define MXC_CRMAP_ACR_CKOS_MASK (0x7 << 4) | |
297 | ||
298 | /* AP Warm reset */ | |
299 | #define MXC_CRMAP_AMCR_SW_AP (1 << 14) | |
300 | ||
301 | /* Bit definitions of ACGCR in CRM_AP for tree level clock gating */ | |
302 | #define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT 0x00000001 | |
303 | #define MXC_CRMAP_ACGCR_ACG0_STOP 0x00000003 | |
304 | #define MXC_CRMAP_ACGCR_ACG0_RUN 0x00000007 | |
305 | #define MXC_CRMAP_ACGCR_ACG0_DISABLED 0x00000000 | |
306 | ||
307 | #define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT 0x00000008 | |
308 | #define MXC_CRMAP_ACGCR_ACG1_STOP 0x00000018 | |
309 | #define MXC_CRMAP_ACGCR_ACG1_RUN 0x00000038 | |
310 | #define MXC_CRMAP_ACGCR_ACG1_DISABLED 0x00000000 | |
311 | ||
312 | #define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT 0x00000040 | |
313 | #define MXC_CRMAP_ACGCR_ACG2_STOP 0x000000C0 | |
314 | #define MXC_CRMAP_ACGCR_ACG2_RUN 0x000001C0 | |
315 | #define MXC_CRMAP_ACGCR_ACG2_DISABLED 0x00000000 | |
316 | ||
317 | #define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT 0x00000200 | |
318 | #define MXC_CRMAP_ACGCR_ACG3_STOP 0x00000600 | |
319 | #define MXC_CRMAP_ACGCR_ACG3_RUN 0x00000E00 | |
320 | #define MXC_CRMAP_ACGCR_ACG3_DISABLED 0x00000000 | |
321 | ||
322 | #define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT 0x00001000 | |
323 | #define MXC_CRMAP_ACGCR_ACG4_STOP 0x00003000 | |
324 | #define MXC_CRMAP_ACGCR_ACG4_RUN 0x00007000 | |
325 | #define MXC_CRMAP_ACGCR_ACG4_DISABLED 0x00000000 | |
326 | ||
327 | #define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT 0x00010000 | |
328 | #define MXC_CRMAP_ACGCR_ACG5_STOP 0x00030000 | |
329 | #define MXC_CRMAP_ACGCR_ACG5_RUN 0x00070000 | |
330 | #define MXC_CRMAP_ACGCR_ACG5_DISABLED 0x00000000 | |
331 | ||
332 | #define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT 0x00080000 | |
333 | #define MXC_CRMAP_ACGCR_ACG6_STOP 0x00180000 | |
334 | #define MXC_CRMAP_ACGCR_ACG6_RUN 0x00380000 | |
335 | #define MXC_CRMAP_ACGCR_ACG6_DISABLED 0x00000000 | |
336 | ||
337 | #define NUM_GATE_CTRL 6 | |
338 | ||
339 | /* CRM COM Register Offsets */ | |
340 | #define MXC_CRMCOM_CSCR (MXC_CRM_COM_BASE + 0x0C) | |
341 | #define MXC_CRMCOM_CCCR (MXC_CRM_COM_BASE + 0x10) | |
342 | ||
343 | /* CRM COM Bit Definitions */ | |
344 | #define MXC_CRMCOM_CSCR_PPD1 0x08000000 | |
345 | #define MXC_CRMCOM_CSCR_CKOHSEL (1 << 18) | |
346 | #define MXC_CRMCOM_CSCR_CKOSEL (1 << 17) | |
347 | #define MXC_CRMCOM_CCCR_CC_DIV_OFFSET 8 | |
348 | #define MXC_CRMCOM_CCCR_CC_DIV_MASK (0x1F << 8) | |
349 | #define MXC_CRMCOM_CCCR_CC_SEL_OFFSET 0 | |
350 | #define MXC_CRMCOM_CCCR_CC_SEL_MASK 0x3 | |
351 | ||
352 | /* DSM Register Offsets */ | |
353 | #define MXC_DSM_SLEEP_TIME (MXC_DSM_BASE + 0x0c) | |
354 | #define MXC_DSM_CONTROL0 (MXC_DSM_BASE + 0x20) | |
355 | #define MXC_DSM_CONTROL1 (MXC_DSM_BASE + 0x24) | |
356 | #define MXC_DSM_CTREN (MXC_DSM_BASE + 0x28) | |
357 | #define MXC_DSM_WARM_PER (MXC_DSM_BASE + 0x40) | |
358 | #define MXC_DSM_LOCK_PER (MXC_DSM_BASE + 0x44) | |
359 | #define MXC_DSM_MGPER (MXC_DSM_BASE + 0x4c) | |
360 | #define MXC_DSM_CRM_CONTROL (MXC_DSM_BASE + 0x50) | |
361 | ||
362 | /* Bit definitions of various registers in DSM */ | |
363 | #define MXC_DSM_CRM_CTRL_DVFS_BYP 0x00000008 | |
364 | #define MXC_DSM_CRM_CTRL_DVFS_VCTRL 0x00000004 | |
365 | #define MXC_DSM_CRM_CTRL_LPMD1 0x00000002 | |
366 | #define MXC_DSM_CRM_CTRL_LPMD0 0x00000001 | |
367 | #define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE 0x00000000 | |
368 | #define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE 0x00000001 | |
369 | #define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE 0x00000003 | |
370 | #define MXC_DSM_CONTROL0_STBY_COMMIT_EN 0x00000200 | |
371 | #define MXC_DSM_CONTROL0_MSTR_EN 0x00000001 | |
372 | #define MXC_DSM_CONTROL0_RESTART 0x00000010 | |
373 | /* Counter Block reset */ | |
374 | #define MXC_DSM_CONTROL1_CB_RST 0x00000002 | |
375 | /* State Machine reset */ | |
376 | #define MXC_DSM_CONTROL1_SM_RST 0x00000004 | |
377 | /* Bit needed to reset counter block */ | |
378 | #define MXC_CONTROL1_RST_CNT32 0x00000008 | |
379 | #define MXC_DSM_CONTROL1_RST_CNT32_EN 0x00000800 | |
380 | #define MXC_DSM_CONTROL1_SLEEP 0x00000100 | |
381 | #define MXC_DSM_CONTROL1_WAKEUP_DISABLE 0x00004000 | |
382 | #define MXC_DSM_CTREN_CNT32 0x00000001 | |
383 | ||
384 | /* Magic Fix enable bit */ | |
385 | #define MXC_DSM_MGPER_EN_MGFX 0x80000000 | |
386 | #define MXC_DSM_MGPER_PER_MASK 0x000003FF | |
387 | #define MXC_DSM_MGPER_PER(n) (MXC_DSM_MGPER_PER_MASK & n) | |
388 | ||
389 | /* Address offsets of the CLKCTL registers */ | |
390 | #define MXC_CLKCTL_GP_CTRL (MXC_CLKCTL_BASE + 0x00) | |
391 | #define MXC_CLKCTL_GP_SER (MXC_CLKCTL_BASE + 0x04) | |
392 | #define MXC_CLKCTL_GP_CER (MXC_CLKCTL_BASE + 0x08) | |
393 | ||
394 | #endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */ |