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a329b48c AK |
1 | /* |
2 | * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ | |
12 | #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ | |
13 | ||
14 | #define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) | |
15 | #define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) | |
16 | #define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) | |
17 | #define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR) | |
18 | #define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) | |
19 | #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) | |
20 | ||
c0abefd3 | 21 | /*MX53*/ |
644b1d58 YS |
22 | #define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR) |
23 | #define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR) | |
24 | #define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) | |
25 | #define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) | |
c0abefd3 DN |
26 | #define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) |
27 | ||
a329b48c AK |
28 | /* PLL Register Offsets */ |
29 | #define MXC_PLL_DP_CTL 0x00 | |
30 | #define MXC_PLL_DP_CONFIG 0x04 | |
31 | #define MXC_PLL_DP_OP 0x08 | |
32 | #define MXC_PLL_DP_MFD 0x0C | |
33 | #define MXC_PLL_DP_MFN 0x10 | |
34 | #define MXC_PLL_DP_MFNMINUS 0x14 | |
35 | #define MXC_PLL_DP_MFNPLUS 0x18 | |
36 | #define MXC_PLL_DP_HFS_OP 0x1C | |
37 | #define MXC_PLL_DP_HFS_MFD 0x20 | |
38 | #define MXC_PLL_DP_HFS_MFN 0x24 | |
39 | #define MXC_PLL_DP_MFN_TOGC 0x28 | |
40 | #define MXC_PLL_DP_DESTAT 0x2c | |
41 | ||
42 | /* PLL Register Bit definitions */ | |
43 | #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 | |
44 | #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 | |
45 | #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 | |
46 | #define MXC_PLL_DP_CTL_ADE 0x800 | |
47 | #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 | |
48 | #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) | |
49 | #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 | |
50 | #define MXC_PLL_DP_CTL_HFSM 0x80 | |
51 | #define MXC_PLL_DP_CTL_PRE 0x40 | |
52 | #define MXC_PLL_DP_CTL_UPEN 0x20 | |
53 | #define MXC_PLL_DP_CTL_RST 0x10 | |
54 | #define MXC_PLL_DP_CTL_RCP 0x8 | |
55 | #define MXC_PLL_DP_CTL_PLM 0x4 | |
56 | #define MXC_PLL_DP_CTL_BRM0 0x2 | |
57 | #define MXC_PLL_DP_CTL_LRF 0x1 | |
58 | ||
59 | #define MXC_PLL_DP_CONFIG_BIST 0x8 | |
60 | #define MXC_PLL_DP_CONFIG_SJC_CE 0x4 | |
61 | #define MXC_PLL_DP_CONFIG_AREN 0x2 | |
62 | #define MXC_PLL_DP_CONFIG_LDREQ 0x1 | |
63 | ||
64 | #define MXC_PLL_DP_OP_MFI_OFFSET 4 | |
65 | #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) | |
66 | #define MXC_PLL_DP_OP_PDF_OFFSET 0 | |
67 | #define MXC_PLL_DP_OP_PDF_MASK 0xF | |
68 | ||
69 | #define MXC_PLL_DP_MFD_OFFSET 0 | |
70 | #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF | |
71 | ||
72 | #define MXC_PLL_DP_MFN_OFFSET 0x0 | |
73 | #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF | |
74 | ||
75 | #define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) | |
76 | #define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) | |
77 | #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 | |
78 | #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF | |
79 | ||
80 | #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) | |
81 | #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF | |
82 | ||
83 | /* Register addresses of CCM*/ | |
84 | #define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) | |
85 | #define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) | |
86 | #define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) | |
87 | #define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) | |
88 | #define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) | |
89 | #define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) | |
90 | #define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) | |
91 | #define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) | |
92 | #define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) | |
93 | #define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) | |
94 | #define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) | |
95 | #define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) | |
96 | #define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) | |
97 | #define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) | |
98 | #define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) | |
99 | #define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) | |
100 | #define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) | |
101 | #define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) | |
102 | #define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) | |
103 | #define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) | |
104 | #define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) | |
105 | #define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) | |
106 | #define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) | |
107 | #define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) | |
108 | #define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) | |
109 | #define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) | |
110 | #define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) | |
111 | #define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) | |
112 | #define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) | |
113 | #define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) | |
114 | #define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) | |
115 | #define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) | |
116 | #define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) | |
117 | #define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) | |
118 | ||
119 | /* Define the bits in register CCR */ | |
120 | #define MXC_CCM_CCR_COSC_EN (1 << 12) | |
121 | #define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) | |
122 | #define MXC_CCM_CCR_CAMP2_EN (1 << 10) | |
123 | #define MXC_CCM_CCR_CAMP1_EN (1 << 9) | |
124 | #define MXC_CCM_CCR_FPM_EN (1 << 8) | |
125 | #define MXC_CCM_CCR_OSCNT_OFFSET (0) | |
126 | #define MXC_CCM_CCR_OSCNT_MASK (0xFF) | |
127 | ||
128 | /* Define the bits in register CCDR */ | |
129 | #define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) | |
130 | #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) | |
131 | #define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) | |
132 | ||
133 | /* Define the bits in register CSR */ | |
134 | #define MXC_CCM_CSR_COSR_READY (1 << 5) | |
135 | #define MXC_CCM_CSR_LVS_VALUE (1 << 4) | |
136 | #define MXC_CCM_CSR_CAMP2_READY (1 << 3) | |
137 | #define MXC_CCM_CSR_CAMP1_READY (1 << 2) | |
138 | #define MXC_CCM_CSR_FPM_READY (1 << 1) | |
139 | #define MXC_CCM_CSR_REF_EN_B (1 << 0) | |
140 | ||
141 | /* Define the bits in register CCSR */ | |
142 | #define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) | |
143 | #define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) | |
144 | #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) | |
145 | #define MXC_CCM_CCSR_STEP_SEL_LP_APM 0 | |
146 | #define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */ | |
147 | #define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2 | |
148 | #define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3 | |
149 | #define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) | |
150 | #define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) | |
151 | #define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) | |
152 | #define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) | |
153 | #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk, | |
154 | 1: step_clk */ | |
155 | #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) | |
156 | #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) | |
157 | ||
158 | /* Define the bits in register CACRR */ | |
159 | #define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) | |
160 | #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) | |
161 | ||
162 | /* Define the bits in register CBCDR */ | |
163 | #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) | |
164 | #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) | |
165 | #define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) | |
166 | #define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) | |
167 | #define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) | |
168 | #define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) | |
169 | #define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) | |
170 | #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) | |
171 | #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) | |
172 | #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) | |
173 | #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) | |
174 | #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) | |
175 | #define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) | |
176 | #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) | |
177 | #define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) | |
178 | #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) | |
179 | #define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) | |
180 | #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) | |
181 | #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) | |
182 | #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) | |
183 | #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) | |
184 | #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) | |
185 | #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) | |
186 | #define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) | |
187 | ||
188 | /* Define the bits in register CBCMR */ | |
189 | #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) | |
190 | #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) | |
191 | #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) | |
192 | #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) | |
193 | #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) | |
194 | #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) | |
195 | #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) | |
196 | #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) | |
197 | #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) | |
198 | #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) | |
199 | #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) | |
200 | #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) | |
201 | #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) | |
202 | #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) | |
203 | #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) | |
204 | #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) | |
205 | ||
206 | /* Define the bits in register CSCMR1 */ | |
207 | #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) | |
208 | #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) | |
209 | #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) | |
210 | #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) | |
211 | #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) | |
212 | #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) | |
213 | #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) | |
214 | #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) | |
215 | #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) | |
216 | #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) | |
217 | #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) | |
218 | #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) | |
219 | #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) | |
220 | #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) | |
221 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) | |
222 | #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) | |
223 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) | |
224 | #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) | |
225 | #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) | |
226 | #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) | |
227 | #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) | |
228 | #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) | |
229 | #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) | |
230 | #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) | |
231 | #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) | |
232 | #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) | |
233 | #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) | |
234 | #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) | |
235 | #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) | |
236 | #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) | |
237 | #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) | |
238 | #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) | |
239 | ||
240 | /* Define the bits in register CSCMR2 */ | |
241 | #define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) | |
242 | #define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) | |
243 | #define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) | |
244 | #define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) | |
245 | #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) | |
246 | #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) | |
247 | #define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) | |
248 | #define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) | |
249 | #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) | |
250 | #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) | |
251 | #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) | |
252 | #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) | |
253 | #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) | |
254 | #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) | |
255 | #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) | |
256 | #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) | |
257 | #define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) | |
258 | #define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) | |
259 | #define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) | |
260 | #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) | |
261 | #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) | |
262 | #define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) | |
263 | #define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) | |
264 | #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) | |
265 | #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) | |
266 | #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) | |
267 | #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) | |
268 | ||
269 | /* Define the bits in register CSCDR1 */ | |
270 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) | |
271 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) | |
272 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) | |
273 | #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) | |
274 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) | |
275 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) | |
276 | #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) | |
277 | #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) | |
278 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) | |
279 | #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) | |
280 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) | |
281 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) | |
282 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) | |
283 | #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) | |
284 | #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) | |
285 | #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) | |
286 | #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) | |
287 | #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) | |
288 | ||
289 | /* Define the bits in register CS1CDR and CS2CDR */ | |
290 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) | |
291 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) | |
292 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) | |
293 | #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) | |
294 | #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) | |
295 | #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) | |
296 | #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) | |
297 | #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) | |
298 | ||
299 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) | |
300 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) | |
301 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) | |
302 | #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) | |
303 | #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) | |
304 | #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) | |
305 | #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) | |
306 | #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) | |
307 | ||
308 | /* Define the bits in register CDCDR */ | |
309 | #define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) | |
310 | #define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) | |
311 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) | |
312 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) | |
313 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) | |
314 | #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) | |
315 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) | |
316 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) | |
317 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) | |
318 | #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) | |
319 | #define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) | |
320 | #define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) | |
321 | #define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) | |
322 | #define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) | |
323 | #define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) | |
324 | #define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) | |
325 | ||
326 | /* Define the bits in register CHSCCDR */ | |
327 | #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) | |
328 | #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) | |
329 | #define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) | |
330 | #define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) | |
331 | #define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) | |
332 | #define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) | |
333 | #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) | |
334 | #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) | |
335 | ||
336 | /* Define the bits in register CSCDR2 */ | |
337 | #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) | |
338 | #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) | |
339 | #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) | |
340 | #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) | |
341 | #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) | |
342 | #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) | |
343 | #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) | |
344 | #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) | |
345 | #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) | |
346 | #define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) | |
347 | #define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) | |
348 | #define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) | |
349 | ||
350 | /* Define the bits in register CSCDR3 */ | |
351 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) | |
352 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) | |
353 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) | |
354 | #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) | |
355 | #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) | |
356 | #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) | |
357 | #define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) | |
358 | #define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) | |
359 | ||
360 | /* Define the bits in register CSCDR4 */ | |
361 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) | |
362 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) | |
363 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) | |
364 | #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) | |
365 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) | |
366 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) | |
367 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) | |
368 | #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) | |
369 | ||
370 | /* Define the bits in register CDHIPR */ | |
371 | #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) | |
372 | #define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) | |
373 | #define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) | |
374 | #define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) | |
375 | #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) | |
376 | #define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) | |
377 | #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) | |
378 | #define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) | |
379 | #define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) | |
380 | #define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) | |
381 | ||
382 | /* Define the bits in register CDCR */ | |
383 | #define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) | |
384 | #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) | |
385 | #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) | |
386 | ||
387 | /* Define the bits in register CLPCR */ | |
388 | #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) | |
389 | #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) | |
c0abefd3 DN |
390 | #define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) |
391 | #define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) | |
a329b48c AK |
392 | #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) |
393 | #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) | |
394 | #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) | |
395 | #define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) | |
396 | #define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) | |
397 | #define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) | |
398 | #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) | |
399 | #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) | |
400 | #define MXC_CCM_CLPCR_VSTBY (0x1 << 8) | |
401 | #define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) | |
402 | #define MXC_CCM_CLPCR_SBYOS (0x1 << 6) | |
403 | #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) | |
404 | #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) | |
405 | #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) | |
406 | #define MXC_CCM_CLPCR_LPM_OFFSET (0) | |
407 | #define MXC_CCM_CLPCR_LPM_MASK (0x3) | |
408 | ||
409 | /* Define the bits in register CISR */ | |
410 | #define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) | |
411 | #define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) | |
412 | #define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) | |
413 | #define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) | |
414 | #define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) | |
415 | #define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) | |
416 | #define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) | |
417 | #define MXC_CCM_CISR_COSC_READY (0x1 << 6) | |
418 | #define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) | |
419 | #define MXC_CCM_CISR_CKIH_READY (0x1 << 4) | |
420 | #define MXC_CCM_CISR_FPM_READY (0x1 << 3) | |
421 | #define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) | |
422 | #define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) | |
423 | #define MXC_CCM_CISR_LRF_PLL1 (0x1) | |
424 | ||
425 | /* Define the bits in register CIMR */ | |
426 | #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) | |
427 | #define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) | |
428 | #define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) | |
429 | #define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) | |
430 | #define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) | |
431 | #define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) | |
432 | #define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) | |
433 | #define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) | |
434 | #define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) | |
435 | #define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) | |
436 | #define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) | |
437 | #define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) | |
438 | #define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) | |
439 | ||
440 | /* Define the bits in register CCOSR */ | |
441 | #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) | |
442 | #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) | |
443 | #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) | |
444 | #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) | |
445 | #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) | |
446 | #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) | |
447 | #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) | |
448 | #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) | |
449 | #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) | |
450 | #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) | |
451 | ||
452 | /* Define the bits in registers CGPR */ | |
453 | #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) | |
454 | #define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) | |
455 | #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) | |
456 | #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) | |
457 | ||
458 | /* Define the bits in registers CCGRx */ | |
459 | #define MXC_CCM_CCGRx_CG_MASK 0x3 | |
460 | #define MXC_CCM_CCGRx_MOD_OFF 0x0 | |
461 | #define MXC_CCM_CCGRx_MOD_ON 0x3 | |
462 | #define MXC_CCM_CCGRx_MOD_IDLE 0x1 | |
463 | ||
464 | #define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30) | |
465 | #define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28) | |
466 | #define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26) | |
467 | #define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24) | |
468 | #define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22) | |
469 | #define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20) | |
470 | #define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18) | |
471 | #define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16) | |
472 | #define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10) | |
473 | #define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8) | |
474 | #define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6) | |
475 | #define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4) | |
476 | #define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2) | |
477 | #define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0) | |
478 | ||
479 | #define MXC_CCM_CCGRx_CG15_OFFSET 30 | |
480 | #define MXC_CCM_CCGRx_CG14_OFFSET 28 | |
481 | #define MXC_CCM_CCGRx_CG13_OFFSET 26 | |
482 | #define MXC_CCM_CCGRx_CG12_OFFSET 24 | |
483 | #define MXC_CCM_CCGRx_CG11_OFFSET 22 | |
484 | #define MXC_CCM_CCGRx_CG10_OFFSET 20 | |
485 | #define MXC_CCM_CCGRx_CG9_OFFSET 18 | |
486 | #define MXC_CCM_CCGRx_CG8_OFFSET 16 | |
487 | #define MXC_CCM_CCGRx_CG7_OFFSET 14 | |
488 | #define MXC_CCM_CCGRx_CG6_OFFSET 12 | |
489 | #define MXC_CCM_CCGRx_CG5_OFFSET 10 | |
490 | #define MXC_CCM_CCGRx_CG4_OFFSET 8 | |
491 | #define MXC_CCM_CCGRx_CG3_OFFSET 6 | |
492 | #define MXC_CCM_CCGRx_CG2_OFFSET 4 | |
493 | #define MXC_CCM_CCGRx_CG1_OFFSET 2 | |
494 | #define MXC_CCM_CCGRx_CG0_OFFSET 0 | |
495 | ||
496 | #define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) | |
497 | #define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) | |
498 | #define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) | |
499 | #define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) | |
500 | #define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) | |
501 | #define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) | |
502 | #define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) | |
503 | #define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) | |
504 | #define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) | |
505 | #define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) | |
506 | #define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) | |
507 | #define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) | |
508 | #define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) | |
509 | ||
510 | /* CORTEXA8 platform */ | |
511 | #define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) | |
512 | #define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) | |
513 | #define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) | |
514 | #define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) | |
515 | #define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) | |
516 | #define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) | |
517 | #define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) | |
518 | #define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) | |
519 | #define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) | |
520 | ||
521 | /* DVFS CORE */ | |
522 | #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) | |
523 | #define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) | |
524 | #define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) | |
525 | #define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) | |
526 | #define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) | |
527 | #define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) | |
528 | #define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) | |
529 | #define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) | |
530 | #define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) | |
531 | #define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) | |
532 | #define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) | |
533 | #define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) | |
534 | #define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) | |
535 | #define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) | |
536 | #define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) | |
537 | #define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) | |
538 | #define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) | |
539 | ||
540 | /* GPC */ | |
541 | #define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) | |
542 | #define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) | |
543 | #define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) | |
544 | #define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) | |
545 | #define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) | |
546 | #define MXC_GPC_PGR_ARMPG_OFFSET 8 | |
547 | #define MXC_GPC_PGR_ARMPG_MASK (3 << 8) | |
548 | ||
549 | /* PGC */ | |
550 | #define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) | |
551 | #define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) | |
552 | #define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) | |
553 | #define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) | |
554 | #define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) | |
555 | #define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) | |
556 | ||
557 | #define MXC_PGCR_PCR 1 | |
558 | #define MXC_SRPGCR_PCR 1 | |
559 | #define MXC_EMPGCR_PCR 1 | |
560 | #define MXC_PGSR_PSR 1 | |
561 | ||
562 | ||
563 | #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) | |
564 | #define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) | |
565 | ||
566 | /* SRPG */ | |
567 | #define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) | |
568 | #define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) | |
569 | #define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) | |
570 | ||
571 | #define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) | |
572 | #define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) | |
573 | #define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) | |
574 | ||
575 | #define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) | |
576 | #define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) | |
577 | #define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) | |
578 | ||
579 | #define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) | |
580 | #define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) | |
581 | #define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) | |
582 | ||
583 | #define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) | |
584 | #define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) | |
585 | #define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) | |
586 | ||
587 | #define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) | |
588 | #define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) | |
589 | #define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) | |
590 | ||
591 | #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ |