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ef93f144 EB |
1 | /* |
2 | * | |
3 | * Copyright (C) 2010 Eric Bénard <eric@eukrea.com> | |
4 | * | |
5 | * based on board-mx51_babbage.c which is | |
6 | * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
7 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> | |
8 | * | |
9 | * The code contained herein is licensed under the GNU General Public | |
10 | * License. You may obtain a copy of the GNU General Public License | |
11 | * Version 2 or later at the following locations: | |
12 | * | |
13 | * http://www.opensource.org/licenses/gpl-license.html | |
14 | * http://www.gnu.org/copyleft/gpl.html | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/serial_8250.h> | |
20 | #include <linux/i2c.h> | |
21 | #include <linux/gpio.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/irq.h> | |
26 | #include <linux/fsl_devices.h> | |
27 | ||
28 | #include <mach/eukrea-baseboards.h> | |
29 | #include <mach/common.h> | |
30 | #include <mach/hardware.h> | |
ef93f144 | 31 | #include <mach/iomux-mx51.h> |
ef93f144 EB |
32 | #include <mach/mxc_ehci.h> |
33 | ||
34 | #include <asm/irq.h> | |
35 | #include <asm/setup.h> | |
36 | #include <asm/mach-types.h> | |
37 | #include <asm/mach/arch.h> | |
38 | #include <asm/mach/time.h> | |
39 | ||
04b73b15 | 40 | #include "devices-imx51.h" |
ef93f144 EB |
41 | #include "devices.h" |
42 | ||
96886c43 AP |
43 | #define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27) |
44 | #define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28) | |
45 | #define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25) | |
46 | #define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26) | |
47 | #define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27) | |
ef93f144 EB |
48 | #define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO) |
49 | #define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO) | |
50 | #define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO) | |
51 | #define CPUIMX51_QUARTD_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO) | |
52 | #define CPUIMX51_QUART_XTAL 14745600 | |
53 | #define CPUIMX51_QUART_REGSHIFT 17 | |
54 | ||
55 | /* USB_CTRL_1 */ | |
56 | #define MX51_USB_CTRL_1_OFFSET 0x10 | |
57 | #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) | |
58 | ||
59 | #define MX51_USB_PLLDIV_12_MHZ 0x00 | |
60 | #define MX51_USB_PLL_DIV_19_2_MHZ 0x01 | |
61 | #define MX51_USB_PLL_DIV_24_MHZ 0x02 | |
62 | ||
63 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) | |
64 | static struct plat_serial8250_port serial_platform_data[] = { | |
65 | { | |
66 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), | |
67 | .irq = CPUIMX51_QUARTA_IRQ, | |
68 | .irqflags = IRQF_TRIGGER_HIGH, | |
69 | .uartclk = CPUIMX51_QUART_XTAL, | |
70 | .regshift = CPUIMX51_QUART_REGSHIFT, | |
71 | .iotype = UPIO_MEM, | |
72 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, | |
73 | }, { | |
74 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000), | |
75 | .irq = CPUIMX51_QUARTB_IRQ, | |
76 | .irqflags = IRQF_TRIGGER_HIGH, | |
77 | .uartclk = CPUIMX51_QUART_XTAL, | |
78 | .regshift = CPUIMX51_QUART_REGSHIFT, | |
79 | .iotype = UPIO_MEM, | |
80 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, | |
81 | }, { | |
82 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000), | |
83 | .irq = CPUIMX51_QUARTC_IRQ, | |
84 | .irqflags = IRQF_TRIGGER_HIGH, | |
85 | .uartclk = CPUIMX51_QUART_XTAL, | |
86 | .regshift = CPUIMX51_QUART_REGSHIFT, | |
87 | .iotype = UPIO_MEM, | |
88 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, | |
89 | }, { | |
90 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000), | |
91 | .irq = CPUIMX51_QUARTD_IRQ, | |
92 | .irqflags = IRQF_TRIGGER_HIGH, | |
93 | .uartclk = CPUIMX51_QUART_XTAL, | |
94 | .regshift = CPUIMX51_QUART_REGSHIFT, | |
95 | .iotype = UPIO_MEM, | |
96 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, | |
97 | }, { | |
98 | } | |
99 | }; | |
100 | ||
101 | static struct platform_device serial_device = { | |
102 | .name = "serial8250", | |
103 | .id = 0, | |
104 | .dev = { | |
105 | .platform_data = serial_platform_data, | |
106 | }, | |
107 | }; | |
108 | #endif | |
109 | ||
110 | static struct platform_device *devices[] __initdata = { | |
ef93f144 EB |
111 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) |
112 | &serial_device, | |
113 | #endif | |
114 | }; | |
115 | ||
8f5260c8 | 116 | static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { |
ef93f144 EB |
117 | /* UART1 */ |
118 | MX51_PAD_UART1_RXD__UART1_RXD, | |
119 | MX51_PAD_UART1_TXD__UART1_TXD, | |
120 | MX51_PAD_UART1_RTS__UART1_RTS, | |
121 | MX51_PAD_UART1_CTS__UART1_CTS, | |
122 | ||
123 | /* I2C2 */ | |
ee1ae4d7 SH |
124 | MX51_PAD_GPIO1_2__I2C2_SCL, |
125 | MX51_PAD_GPIO1_3__I2C2_SDA, | |
126 | MX51_PAD_NANDF_D10__GPIO3_30, | |
ef93f144 EB |
127 | |
128 | /* QUART IRQ */ | |
ee1ae4d7 SH |
129 | MX51_PAD_NANDF_D15__GPIO3_25, |
130 | MX51_PAD_NANDF_D14__GPIO3_26, | |
131 | MX51_PAD_NANDF_D13__GPIO3_27, | |
132 | MX51_PAD_NANDF_D12__GPIO3_28, | |
ef93f144 EB |
133 | |
134 | /* USB HOST1 */ | |
135 | MX51_PAD_USBH1_CLK__USBH1_CLK, | |
136 | MX51_PAD_USBH1_DIR__USBH1_DIR, | |
137 | MX51_PAD_USBH1_NXT__USBH1_NXT, | |
138 | MX51_PAD_USBH1_DATA0__USBH1_DATA0, | |
139 | MX51_PAD_USBH1_DATA1__USBH1_DATA1, | |
140 | MX51_PAD_USBH1_DATA2__USBH1_DATA2, | |
141 | MX51_PAD_USBH1_DATA3__USBH1_DATA3, | |
142 | MX51_PAD_USBH1_DATA4__USBH1_DATA4, | |
143 | MX51_PAD_USBH1_DATA5__USBH1_DATA5, | |
144 | MX51_PAD_USBH1_DATA6__USBH1_DATA6, | |
145 | MX51_PAD_USBH1_DATA7__USBH1_DATA7, | |
146 | MX51_PAD_USBH1_STP__USBH1_STP, | |
147 | }; | |
148 | ||
a3927416 EB |
149 | static const struct mxc_nand_platform_data |
150 | eukrea_cpuimx51_nand_board_info __initconst = { | |
151 | .width = 1, | |
152 | .hw_ecc = 1, | |
153 | .flash_bbt = 1, | |
154 | }; | |
155 | ||
04b73b15 | 156 | static const struct imxuart_platform_data uart_pdata __initconst = { |
ef93f144 EB |
157 | .flags = IMXUART_HAVE_RTSCTS, |
158 | }; | |
159 | ||
44505c07 UKK |
160 | static const |
161 | struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = { | |
ef93f144 EB |
162 | .bitrate = 100000, |
163 | }; | |
164 | ||
165 | static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = { | |
166 | { | |
167 | I2C_BOARD_INFO("pcf8563", 0x51), | |
168 | }, | |
169 | }; | |
170 | ||
171 | /* This function is board specific as the bit mask for the plldiv will also | |
172 | be different for other Freescale SoCs, thus a common bitmask is not | |
173 | possible and cannot get place in /plat-mxc/ehci.c.*/ | |
174 | static int initialize_otg_port(struct platform_device *pdev) | |
175 | { | |
176 | u32 v; | |
177 | void __iomem *usb_base; | |
178 | void __iomem *usbother_base; | |
179 | ||
180 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | |
28a4f908 FE |
181 | if (!usb_base) |
182 | return -ENOMEM; | |
ef93f144 EB |
183 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
184 | ||
185 | /* Set the PHY clock to 19.2MHz */ | |
186 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); | |
187 | v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; | |
188 | v |= MX51_USB_PLL_DIV_19_2_MHZ; | |
189 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); | |
190 | iounmap(usb_base); | |
191 | return 0; | |
192 | } | |
193 | ||
194 | static int initialize_usbh1_port(struct platform_device *pdev) | |
195 | { | |
196 | u32 v; | |
197 | void __iomem *usb_base; | |
198 | void __iomem *usbother_base; | |
199 | ||
200 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | |
28a4f908 FE |
201 | if (!usb_base) |
202 | return -ENOMEM; | |
ef93f144 EB |
203 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
204 | ||
205 | /* The clock for the USBH1 ULPI port will come externally from the PHY. */ | |
206 | v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); | |
207 | __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); | |
208 | iounmap(usb_base); | |
209 | return 0; | |
210 | } | |
211 | ||
212 | static struct mxc_usbh_platform_data dr_utmi_config = { | |
213 | .init = initialize_otg_port, | |
214 | .portsc = MXC_EHCI_UTMI_16BIT, | |
215 | .flags = MXC_EHCI_INTERNAL_PHY, | |
216 | }; | |
217 | ||
218 | static struct fsl_usb2_platform_data usb_pdata = { | |
219 | .operating_mode = FSL_USB2_DR_DEVICE, | |
220 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, | |
221 | }; | |
222 | ||
223 | static struct mxc_usbh_platform_data usbh1_config = { | |
224 | .init = initialize_usbh1_port, | |
225 | .portsc = MXC_EHCI_MODE_ULPI, | |
226 | .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD), | |
227 | }; | |
228 | ||
229 | static int otg_mode_host; | |
230 | ||
231 | static int __init eukrea_cpuimx51_otg_mode(char *options) | |
232 | { | |
233 | if (!strcmp(options, "host")) | |
234 | otg_mode_host = 1; | |
235 | else if (!strcmp(options, "device")) | |
236 | otg_mode_host = 0; | |
237 | else | |
238 | pr_info("otg_mode neither \"host\" nor \"device\". " | |
239 | "Defaulting to device\n"); | |
240 | return 0; | |
241 | } | |
242 | __setup("otg_mode=", eukrea_cpuimx51_otg_mode); | |
243 | ||
244 | /* | |
245 | * Board specific initialization. | |
246 | */ | |
247 | static void __init eukrea_cpuimx51_init(void) | |
248 | { | |
249 | mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, | |
250 | ARRAY_SIZE(eukrea_cpuimx51_pads)); | |
251 | ||
04b73b15 | 252 | imx51_add_imx_uart(0, &uart_pdata); |
a3927416 EB |
253 | imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info); |
254 | ||
ef93f144 EB |
255 | gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq"); |
256 | gpio_direction_input(CPUIMX51_QUARTA_GPIO); | |
257 | gpio_free(CPUIMX51_QUARTA_GPIO); | |
258 | gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq"); | |
259 | gpio_direction_input(CPUIMX51_QUARTB_GPIO); | |
260 | gpio_free(CPUIMX51_QUARTB_GPIO); | |
261 | gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq"); | |
262 | gpio_direction_input(CPUIMX51_QUARTC_GPIO); | |
263 | gpio_free(CPUIMX51_QUARTC_GPIO); | |
264 | gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq"); | |
265 | gpio_direction_input(CPUIMX51_QUARTD_GPIO); | |
266 | gpio_free(CPUIMX51_QUARTD_GPIO); | |
267 | ||
6bd96f3c | 268 | imx51_add_fec(NULL); |
ef93f144 EB |
269 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
270 | ||
44505c07 | 271 | imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data); |
ef93f144 EB |
272 | i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices, |
273 | ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); | |
274 | ||
275 | if (otg_mode_host) | |
276 | mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); | |
277 | else { | |
278 | initialize_otg_port(NULL); | |
279 | mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); | |
280 | } | |
281 | mxc_register_device(&mxc_usbh1_device, &usbh1_config); | |
282 | ||
283 | #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD | |
284 | eukrea_mbimx51_baseboard_init(); | |
285 | #endif | |
286 | } | |
287 | ||
288 | static void __init eukrea_cpuimx51_timer_init(void) | |
289 | { | |
290 | mx51_clocks_init(32768, 24000000, 22579200, 0); | |
291 | } | |
292 | ||
293 | static struct sys_timer mxc_timer = { | |
294 | .init = eukrea_cpuimx51_timer_init, | |
295 | }; | |
296 | ||
297 | MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") | |
298 | /* Maintainer: Eric Bénard <eric@eukrea.com> */ | |
7608d7d2 | 299 | .boot_params = MX51_PHYS_OFFSET + 0x100, |
ef93f144 EB |
300 | .map_io = mx51_map_io, |
301 | .init_irq = mx51_init_irq, | |
302 | .init_machine = eukrea_cpuimx51_init, | |
303 | .timer = &mxc_timer, | |
304 | MACHINE_END |