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Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groec...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-mx3 / mach-pcm043.c
CommitLineData
54df5268
SH		 1/*
2 * Copyright (C) 2009 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
54df5268
SH		 13 */
14
15#include <linux/types.h>
16#include <linux/init.h>
17
18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
20#include <linux/mtd/plat-ram.h>
21#include <linux/memory.h>
22#include <linux/gpio.h>
23#include <linux/smc911x.h>
24#include <linux/interrupt.h>
d2831d1f 25#include <linux/delay.h>
54df5268
SH		 26#include <linux/i2c.h>
27#include <linux/i2c/at24.h>
cb2dc111
SH		 28#include <linux/usb/otg.h>
29#include <linux/usb/ulpi.h>
54df5268
SH		 30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/time.h>
34#include <asm/mach/map.h>
35
36#include <mach/hardware.h>
37#include <mach/common.h>
54df5268
SH		 38#include <mach/iomux-mx35.h>
39#include <mach/ipu.h>
40#include <mach/mx3fb.h>
cb2dc111 41#include <mach/ulpi.h>
d2831d1f 42#include <mach/audmux.h>
54df5268 43
e2611ba4 44#include "devices-imx35.h"
54df5268
SH		 45#include "devices.h"
46
47static const struct fb_videomode fb_modedb[] = {
48 {
49 /* 240x320 @ 60 Hz */
50 .name = "Sharp-LQ035Q7",
51 .refresh = 60,
52 .xres = 240,
53 .yres = 320,
54 .pixclock = 185925,
55 .left_margin = 9,
56 .right_margin = 16,
57 .upper_margin = 7,
58 .lower_margin = 9,
59 .hsync_len = 1,
60 .vsync_len = 1,
61 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
62 .vmode = FB_VMODE_NONINTERLACED,
63 .flag = 0,
64 }, {
65 /* 240x320 @ 60 Hz */
66 .name = "TX090",
67 .refresh = 60,
68 .xres = 240,
69 .yres = 320,
70 .pixclock = 38255,
71 .left_margin = 144,
72 .right_margin = 0,
73 .upper_margin = 7,
74 .lower_margin = 40,
75 .hsync_len = 96,
76 .vsync_len = 1,
77 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
78 .vmode = FB_VMODE_NONINTERLACED,
79 .flag = 0,
80 },
81};
82
83static struct ipu_platform_data mx3_ipu_data = {
84 .irq_base = MXC_IPU_IRQ_START,
85};
86
87static struct mx3fb_platform_data mx3fb_pdata = {
88 .dma_dev = &mx3_ipu.dev,
89 .name = "Sharp-LQ035Q7",
90 .mode = fb_modedb,
91 .num_modes = ARRAY_SIZE(fb_modedb),
92};
93
94static struct physmap_flash_data pcm043_flash_data = {
95 .width = 2,
96};
97
98static struct resource pcm043_flash_resource = {
99 .start = 0xa0000000,
100 .end = 0xa1ffffff,
101 .flags = IORESOURCE_MEM,
102};
103
104static struct platform_device pcm043_flash = {
105 .name = "physmap-flash",
106 .id = 0,
107 .dev = {
108 .platform_data = &pcm043_flash_data,
109 },
110 .resource = &pcm043_flash_resource,
111 .num_resources = 1,
112};
113
6eafde5f 114static const struct imxuart_platform_data uart_pdata __initconst = {
54df5268
SH		 115 .flags = IMXUART_HAVE_RTSCTS,
116};
117
118#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
7cdc8fa7 119static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
54df5268
SH		 120 .bitrate = 50000,
121};
122
123static struct at24_platform_data board_eeprom = {
124 .byte_len = 4096,
125 .page_size = 32,
126 .flags = AT24_FLAG_ADDR16,
127};
128
129static struct i2c_board_info pcm043_i2c_devices[] = {
130 {
131 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
132 .platform_data = &board_eeprom,
133 }, {
cf87a6e2 134 I2C_BOARD_INFO("pcf8563", 0x51),
54df5268
SH		 135 }
136};
137#endif
138
139static struct platform_device *devices[] __initdata = {
140 &pcm043_flash,
54df5268
SH		 141};
142
8f5260c8 143static iomux_v3_cfg_t pcm043_pads[] = {
54df5268
SH		 144 /* UART1 */
145 MX35_PAD_CTS1__UART1_CTS,
146 MX35_PAD_RTS1__UART1_RTS,
147 MX35_PAD_TXD1__UART1_TXD_MUX,
148 MX35_PAD_RXD1__UART1_RXD_MUX,
149 /* UART2 */
150 MX35_PAD_CTS2__UART2_CTS,
151 MX35_PAD_RTS2__UART2_RTS,
152 MX35_PAD_TXD2__UART2_TXD_MUX,
153 MX35_PAD_RXD2__UART2_RXD_MUX,
154 /* FEC */
155 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
156 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
157 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
158 MX35_PAD_FEC_COL__FEC_COL,
159 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
160 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
161 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
162 MX35_PAD_FEC_MDC__FEC_MDC,
163 MX35_PAD_FEC_MDIO__FEC_MDIO,
164 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
165 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
166 MX35_PAD_FEC_CRS__FEC_CRS,
167 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
168 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
169 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
170 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
171 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
172 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
173 /* I2C1 */
174 MX35_PAD_I2C1_CLK__I2C1_SCL,
175 MX35_PAD_I2C1_DAT__I2C1_SDA,
176 /* Display */
177 MX35_PAD_LD0__IPU_DISPB_DAT_0,
178 MX35_PAD_LD1__IPU_DISPB_DAT_1,
179 MX35_PAD_LD2__IPU_DISPB_DAT_2,
180 MX35_PAD_LD3__IPU_DISPB_DAT_3,
181 MX35_PAD_LD4__IPU_DISPB_DAT_4,
182 MX35_PAD_LD5__IPU_DISPB_DAT_5,
183 MX35_PAD_LD6__IPU_DISPB_DAT_6,
184 MX35_PAD_LD7__IPU_DISPB_DAT_7,
185 MX35_PAD_LD8__IPU_DISPB_DAT_8,
186 MX35_PAD_LD9__IPU_DISPB_DAT_9,
187 MX35_PAD_LD10__IPU_DISPB_DAT_10,
188 MX35_PAD_LD11__IPU_DISPB_DAT_11,
189 MX35_PAD_LD12__IPU_DISPB_DAT_12,
190 MX35_PAD_LD13__IPU_DISPB_DAT_13,
191 MX35_PAD_LD14__IPU_DISPB_DAT_14,
192 MX35_PAD_LD15__IPU_DISPB_DAT_15,
193 MX35_PAD_LD16__IPU_DISPB_DAT_16,
194 MX35_PAD_LD17__IPU_DISPB_DAT_17,
195 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
196 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
197 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
198 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
199 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
200 MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
201 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
8d5c1ed3
LF		 202 /* gpio */
203 MX35_PAD_ATA_CS0__GPIO2_6,
cb2dc111
SH		 204 /* USB host */
205 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
206 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
d2831d1f
SH		 207 /* SSI */
208 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
209 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
210 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
211 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
da92e42b
MKB		 212 /* CAN2 */
213 MX35_PAD_TX5_RX0__CAN2_TXCAN,
214 MX35_PAD_TX4_RX1__CAN2_RXCAN,
9a545943
WS		 215 /* esdhc */
216 MX35_PAD_SD1_CMD__ESDHC1_CMD,
217 MX35_PAD_SD1_CLK__ESDHC1_CLK,
218 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
219 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
220 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
221 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
d2831d1f
SH		 222};
223
224#define AC97_GPIO_TXFS (1 * 32 + 31)
225#define AC97_GPIO_TXD (1 * 32 + 28)
226#define AC97_GPIO_RESET (1 * 32 + 0)
227
228static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
229{
8f5260c8
LW		 230 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
231 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
d2831d1f
SH		 232 int ret;
233
234 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
235 if (ret) {
236 printk("failed to get GPIO_TXFS: %d\n", ret);
237 return;
238 }
239
96f3e256 240 mxc_iomux_v3_setup_pad(txfs_gpio);
d2831d1f
SH		 241
242 /* warm reset */
243 gpio_direction_output(AC97_GPIO_TXFS, 1);
244 udelay(2);
245 gpio_set_value(AC97_GPIO_TXFS, 0);
246
247 gpio_free(AC97_GPIO_TXFS);
96f3e256 248 mxc_iomux_v3_setup_pad(txfs);
d2831d1f
SH		 249}
250
251static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
252{
8f5260c8
LW		 253 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
254 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
255 iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
256 iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
257 iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
d2831d1f
SH		 258 int ret;
259
260 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
261 if (ret)
262 goto err1;
263
264 ret = gpio_request(AC97_GPIO_TXD, "SSI");
265 if (ret)
266 goto err2;
267
268 ret = gpio_request(AC97_GPIO_RESET, "SSI");
269 if (ret)
270 goto err3;
271
96f3e256
LW		 272 mxc_iomux_v3_setup_pad(txfs_gpio);
273 mxc_iomux_v3_setup_pad(txd_gpio);
274 mxc_iomux_v3_setup_pad(reset_gpio);
d2831d1f
SH		 275
276 gpio_direction_output(AC97_GPIO_TXFS, 0);
277 gpio_direction_output(AC97_GPIO_TXD, 0);
278
279 /* cold reset */
280 gpio_direction_output(AC97_GPIO_RESET, 0);
281 udelay(10);
282 gpio_direction_output(AC97_GPIO_RESET, 1);
283
96f3e256
LW		 284 mxc_iomux_v3_setup_pad(txd);
285 mxc_iomux_v3_setup_pad(txfs);
d2831d1f
SH		 286
287 gpio_free(AC97_GPIO_RESET);
288err3:
289 gpio_free(AC97_GPIO_TXD);
290err2:
291 gpio_free(AC97_GPIO_TXFS);
292err1:
293 if (ret)
294 printk("%s failed with %d\n", __func__, ret);
295 mdelay(1);
296}
297
4697bb92 298static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
d2831d1f
SH		 299 .ac97_reset = pcm043_ac97_cold_reset,
300 .ac97_warm_reset = pcm043_ac97_warm_reset,
301 .flags = IMX_SSI_USE_AC97,
54df5268
SH		 302};
303
e2611ba4
UKK		 304static const struct mxc_nand_platform_data
305pcm037_nand_board_info __initconst = {
4f43c2ed
SH		 306 .width = 1,
307 .hw_ecc = 1,
308};
309
c18e8fa5 310#if defined(CONFIG_USB_ULPI)
2d58de28 311static struct mxc_usbh_platform_data otg_pdata __initdata = {
cb2dc111
SH		 312 .portsc = MXC_EHCI_MODE_UTMI,
313 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
314};
315
2d58de28 316static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
cb2dc111
SH		 317 .portsc = MXC_EHCI_MODE_SERIAL,
318 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
319 MXC_EHCI_IPPUE_DOWN,
320};
c18e8fa5 321#endif
cb2dc111 322
9e1dde33 323static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
cb2dc111
SH		 324 .operating_mode = FSL_USB2_DR_DEVICE,
325 .phy_mode = FSL_USB2_PHY_UTMI,
326};
327
328static int otg_mode_host;
329
330static int __init pcm043_otg_mode(char *options)
331{
332 if (!strcmp(options, "host"))
333 otg_mode_host = 1;
334 else if (!strcmp(options, "device"))
335 otg_mode_host = 0;
336 else
337 pr_info("otg_mode neither \"host\" nor \"device\". "
338 "Defaulting to device\n");
339 return 0;
340}
341__setup("otg_mode=", pcm043_otg_mode);
342
54df5268
SH		 343/*
344 * Board specific initialization.
345 */
346static void __init mxc_board_init(void)
347{
348 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
349
d2831d1f
SH		 350 mxc_audmux_v2_configure_port(3,
351 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
352 MXC_AUDMUX_V2_PTCR_TFSEL(0) |
353 MXC_AUDMUX_V2_PTCR_TFSDIR,
354 MXC_AUDMUX_V2_PDCR_RXDSEL(0));
355
356 mxc_audmux_v2_configure_port(0,
357 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
358 MXC_AUDMUX_V2_PTCR_TCSEL(3) |
359 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
360 MXC_AUDMUX_V2_PDCR_RXDSEL(3));
361
6bd96f3c 362 imx35_add_fec(NULL);
54df5268 363 platform_add_devices(devices, ARRAY_SIZE(devices));
742269e2 364 imx35_add_imx2_wdt(NULL);
54df5268 365
6eafde5f 366 imx35_add_imx_uart0(&uart_pdata);
e2611ba4 367 imx35_add_mxc_nand(&pcm037_nand_board_info);
4697bb92 368 imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
54df5268 369
6eafde5f 370 imx35_add_imx_uart1(&uart_pdata);
54df5268
SH		 371
372#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
373 i2c_register_board_info(0, pcm043_i2c_devices,
374 ARRAY_SIZE(pcm043_i2c_devices));
375
7cdc8fa7 376 imx35_add_imx_i2c0(&pcm043_i2c0_data);
54df5268
SH		 377#endif
378
379 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
380 mxc_register_device(&mx3_fb, &mx3fb_pdata);
cb2dc111
SH		 381
382#if defined(CONFIG_USB_ULPI)
383 if (otg_mode_host) {
384 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
13dd0c97 385 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
cb2dc111 386
2d58de28 387 imx35_add_mxc_ehci_otg(&otg_pdata);
cb2dc111
SH		 388 }
389
2d58de28 390 imx35_add_mxc_ehci_hs(&usbh1_pdata);
cb2dc111
SH		 391#endif
392 if (!otg_mode_host)
9e1dde33 393 imx35_add_fsl_usb2_udc(&otg_device_pdata);
cb2dc111 394
da92e42b 395 imx35_add_flexcan1(NULL);
124bf94a 396 imx35_add_sdhci_esdhc_imx(0, NULL);
54df5268
SH		 397}
398
399static void __init pcm043_timer_init(void)
400{
401 mx35_clocks_init();
402}
403
404struct sys_timer pcm043_timer = {
405 .init = pcm043_timer_init,
406};
407
408MACHINE_START(PCM043, "Phytec Phycore pcm043")
409 /* Maintainer: Pengutronix */
34101237 410 .boot_params = MX3x_PHYS_OFFSET + 0x100,
cd4a05f9 411 .map_io = mx35_map_io,
c5aa0ad0 412 .init_irq = mx35_init_irq,
54df5268
SH		 413 .init_machine = mxc_board_init,
414 .timer = &pcm043_timer,
415MACHINE_END
416
kernel source for telekom puls (alcatel/mediatek)