[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-mv78xx0 / irq.c

/*
 * arch/arm/mach-mv78xx0/irq.c
 *
 * MV78xx0 IRQ handling.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <asm/gpio.h>
#include <mach/bridge-regs.h>
#include <plat/irq.h>
#include "common.h"

static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31);

	orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3);
}

void __init mv78xx0_init_irq(void)
{
	int i;

	/* Initialize gpiolib. */
	orion_gpio_init();

	orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
	orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
	orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));

	/*
	 * Mask and clear GPIO IRQ interrupts.
	 */
	writel(0, GPIO_LEVEL_MASK(0));
	writel(0, GPIO_EDGE_MASK(0));
	writel(0, GPIO_EDGE_CAUSE(0));

	for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
		set_irq_chip(i, &orion_gpio_irq_chip);
		set_irq_handler(i, handle_level_irq);
		irq_desc[i].status |= IRQ_LEVEL;
		set_irq_flags(i, IRQF_VALID);
	}
	set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
	set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
	set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
	set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
}
Commit	Line	Data
794d15b2 SS	1	/*
	2	* arch/arm/mach-mv78xx0/irq.c
	3	*
	4	* MV78xx0 IRQ handling.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/pci.h>
b95a13d7 LB	14	#include <linux/irq.h>
b95a13d7 LB	15	#include <asm/gpio.h>
fdd8b079	16	#include <mach/bridge-regs.h>
6f088f1d	17	#include <plat/irq.h>
794d15b2 SS	18	#include "common.h"
794d15b2 SS	19
b95a13d7 LB	20	static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
	21	{
	22	BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 \|\| irq > IRQ_MV78XX0_GPIO_24_31);
	23
	24	orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3);
	25	}
	26
794d15b2 SS	27	void __init mv78xx0_init_irq(void)
794d15b2 SS	28	{
b95a13d7 LB	29	int i;
b95a13d7 LB	30
a8865655 EB	31	/* Initialize gpiolib. */
	32	orion_gpio_init();
	33
794d15b2 SS	34	orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
794d15b2 SS	35	orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
1f8081f5	36	orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
b95a13d7 LB	37
	38	/*
	39	* Mask and clear GPIO IRQ interrupts.
	40	*/
	41	writel(0, GPIO_LEVEL_MASK(0));
	42	writel(0, GPIO_EDGE_MASK(0));
	43	writel(0, GPIO_EDGE_CAUSE(0));
	44
	45	for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
fd4b9b36	46	set_irq_chip(i, &orion_gpio_irq_chip);
b95a13d7 LB	47	set_irq_handler(i, handle_level_irq);
	48	irq_desc[i].status \|= IRQ_LEVEL;
	49	set_irq_flags(i, IRQF_VALID);
	50	}
	51	set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
	52	set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
	53	set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
	54	set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
794d15b2	55	}