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d9c8279b SM |
1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
15 | * 02110-1301, USA. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/bootmem.h> | |
21 | ||
22 | #include <mach/msm_iomap-8x60.h> | |
23 | #include <mach/irqs-8x60.h> | |
24 | #include <mach/iommu.h> | |
25 | ||
26 | static struct resource msm_iommu_jpegd_resources[] = { | |
27 | { | |
28 | .start = MSM_IOMMU_JPEGD_PHYS, | |
29 | .end = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1, | |
30 | .name = "physbase", | |
31 | .flags = IORESOURCE_MEM, | |
32 | }, | |
33 | { | |
34 | .name = "nonsecure_irq", | |
35 | .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, | |
36 | .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, | |
37 | .flags = IORESOURCE_IRQ, | |
38 | }, | |
39 | { | |
40 | .name = "secure_irq", | |
41 | .start = SMMU_JPEGD_CB_SC_SECURE_IRQ, | |
42 | .end = SMMU_JPEGD_CB_SC_SECURE_IRQ, | |
43 | .flags = IORESOURCE_IRQ, | |
44 | }, | |
45 | }; | |
46 | ||
47 | static struct resource msm_iommu_vpe_resources[] = { | |
48 | { | |
49 | .start = MSM_IOMMU_VPE_PHYS, | |
50 | .end = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1, | |
51 | .name = "physbase", | |
52 | .flags = IORESOURCE_MEM, | |
53 | }, | |
54 | { | |
55 | .name = "nonsecure_irq", | |
56 | .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ, | |
57 | .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ, | |
58 | .flags = IORESOURCE_IRQ, | |
59 | }, | |
60 | { | |
61 | .name = "secure_irq", | |
62 | .start = SMMU_VPE_CB_SC_SECURE_IRQ, | |
63 | .end = SMMU_VPE_CB_SC_SECURE_IRQ, | |
64 | .flags = IORESOURCE_IRQ, | |
65 | }, | |
66 | }; | |
67 | ||
68 | static struct resource msm_iommu_mdp0_resources[] = { | |
69 | { | |
70 | .start = MSM_IOMMU_MDP0_PHYS, | |
71 | .end = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1, | |
72 | .name = "physbase", | |
73 | .flags = IORESOURCE_MEM, | |
74 | }, | |
75 | { | |
76 | .name = "nonsecure_irq", | |
77 | .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, | |
78 | .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, | |
79 | .flags = IORESOURCE_IRQ, | |
80 | }, | |
81 | { | |
82 | .name = "secure_irq", | |
83 | .start = SMMU_MDP0_CB_SC_SECURE_IRQ, | |
84 | .end = SMMU_MDP0_CB_SC_SECURE_IRQ, | |
85 | .flags = IORESOURCE_IRQ, | |
86 | }, | |
87 | }; | |
88 | ||
89 | static struct resource msm_iommu_mdp1_resources[] = { | |
90 | { | |
91 | .start = MSM_IOMMU_MDP1_PHYS, | |
92 | .end = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1, | |
93 | .name = "physbase", | |
94 | .flags = IORESOURCE_MEM, | |
95 | }, | |
96 | { | |
97 | .name = "nonsecure_irq", | |
98 | .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, | |
99 | .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, | |
100 | .flags = IORESOURCE_IRQ, | |
101 | }, | |
102 | { | |
103 | .name = "secure_irq", | |
104 | .start = SMMU_MDP1_CB_SC_SECURE_IRQ, | |
105 | .end = SMMU_MDP1_CB_SC_SECURE_IRQ, | |
106 | .flags = IORESOURCE_IRQ, | |
107 | }, | |
108 | }; | |
109 | ||
110 | static struct resource msm_iommu_rot_resources[] = { | |
111 | { | |
112 | .start = MSM_IOMMU_ROT_PHYS, | |
113 | .end = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1, | |
114 | .name = "physbase", | |
115 | .flags = IORESOURCE_MEM, | |
116 | }, | |
117 | { | |
118 | .name = "nonsecure_irq", | |
119 | .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ, | |
120 | .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ, | |
121 | .flags = IORESOURCE_IRQ, | |
122 | }, | |
123 | { | |
124 | .name = "secure_irq", | |
125 | .start = SMMU_ROT_CB_SC_SECURE_IRQ, | |
126 | .end = SMMU_ROT_CB_SC_SECURE_IRQ, | |
127 | .flags = IORESOURCE_IRQ, | |
128 | }, | |
129 | }; | |
130 | ||
131 | static struct resource msm_iommu_ijpeg_resources[] = { | |
132 | { | |
133 | .start = MSM_IOMMU_IJPEG_PHYS, | |
134 | .end = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1, | |
135 | .name = "physbase", | |
136 | .flags = IORESOURCE_MEM, | |
137 | }, | |
138 | { | |
139 | .name = "nonsecure_irq", | |
140 | .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, | |
141 | .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, | |
142 | .flags = IORESOURCE_IRQ, | |
143 | }, | |
144 | { | |
145 | .name = "secure_irq", | |
146 | .start = SMMU_IJPEG_CB_SC_SECURE_IRQ, | |
147 | .end = SMMU_IJPEG_CB_SC_SECURE_IRQ, | |
148 | .flags = IORESOURCE_IRQ, | |
149 | }, | |
150 | }; | |
151 | ||
152 | static struct resource msm_iommu_vfe_resources[] = { | |
153 | { | |
154 | .start = MSM_IOMMU_VFE_PHYS, | |
155 | .end = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1, | |
156 | .name = "physbase", | |
157 | .flags = IORESOURCE_MEM, | |
158 | }, | |
159 | { | |
160 | .name = "nonsecure_irq", | |
161 | .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ, | |
162 | .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ, | |
163 | .flags = IORESOURCE_IRQ, | |
164 | }, | |
165 | { | |
166 | .name = "secure_irq", | |
167 | .start = SMMU_VFE_CB_SC_SECURE_IRQ, | |
168 | .end = SMMU_VFE_CB_SC_SECURE_IRQ, | |
169 | .flags = IORESOURCE_IRQ, | |
170 | }, | |
171 | }; | |
172 | ||
173 | static struct resource msm_iommu_vcodec_a_resources[] = { | |
174 | { | |
175 | .start = MSM_IOMMU_VCODEC_A_PHYS, | |
176 | .end = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1, | |
177 | .name = "physbase", | |
178 | .flags = IORESOURCE_MEM, | |
179 | }, | |
180 | { | |
181 | .name = "nonsecure_irq", | |
182 | .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, | |
183 | .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, | |
184 | .flags = IORESOURCE_IRQ, | |
185 | }, | |
186 | { | |
187 | .name = "secure_irq", | |
188 | .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, | |
189 | .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, | |
190 | .flags = IORESOURCE_IRQ, | |
191 | }, | |
192 | }; | |
193 | ||
194 | static struct resource msm_iommu_vcodec_b_resources[] = { | |
195 | { | |
196 | .start = MSM_IOMMU_VCODEC_B_PHYS, | |
197 | .end = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1, | |
198 | .name = "physbase", | |
199 | .flags = IORESOURCE_MEM, | |
200 | }, | |
201 | { | |
202 | .name = "nonsecure_irq", | |
203 | .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, | |
204 | .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, | |
205 | .flags = IORESOURCE_IRQ, | |
206 | }, | |
207 | { | |
208 | .name = "secure_irq", | |
209 | .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, | |
210 | .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, | |
211 | .flags = IORESOURCE_IRQ, | |
212 | }, | |
213 | }; | |
214 | ||
215 | static struct resource msm_iommu_gfx3d_resources[] = { | |
216 | { | |
217 | .start = MSM_IOMMU_GFX3D_PHYS, | |
218 | .end = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1, | |
219 | .name = "physbase", | |
220 | .flags = IORESOURCE_MEM, | |
221 | }, | |
222 | { | |
223 | .name = "nonsecure_irq", | |
224 | .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, | |
225 | .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, | |
226 | .flags = IORESOURCE_IRQ, | |
227 | }, | |
228 | { | |
229 | .name = "secure_irq", | |
230 | .start = SMMU_GFX3D_CB_SC_SECURE_IRQ, | |
231 | .end = SMMU_GFX3D_CB_SC_SECURE_IRQ, | |
232 | .flags = IORESOURCE_IRQ, | |
233 | }, | |
234 | }; | |
235 | ||
236 | static struct resource msm_iommu_gfx2d0_resources[] = { | |
237 | { | |
238 | .start = MSM_IOMMU_GFX2D0_PHYS, | |
239 | .end = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1, | |
240 | .name = "physbase", | |
241 | .flags = IORESOURCE_MEM, | |
242 | }, | |
243 | { | |
244 | .name = "nonsecure_irq", | |
245 | .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, | |
246 | .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, | |
247 | .flags = IORESOURCE_IRQ, | |
248 | }, | |
249 | { | |
250 | .name = "secure_irq", | |
251 | .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ, | |
252 | .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ, | |
253 | .flags = IORESOURCE_IRQ, | |
254 | }, | |
255 | }; | |
256 | ||
e8952e3b SM |
257 | static struct resource msm_iommu_gfx2d1_resources[] = { |
258 | { | |
259 | .start = MSM_IOMMU_GFX2D1_PHYS, | |
260 | .end = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1, | |
261 | .name = "physbase", | |
262 | .flags = IORESOURCE_MEM, | |
263 | }, | |
264 | { | |
265 | .name = "nonsecure_irq", | |
266 | .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, | |
267 | .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, | |
268 | .flags = IORESOURCE_IRQ, | |
269 | }, | |
270 | { | |
271 | .name = "secure_irq", | |
272 | .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ, | |
273 | .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ, | |
274 | .flags = IORESOURCE_IRQ, | |
275 | }, | |
276 | }; | |
277 | ||
d9c8279b SM |
278 | static struct platform_device msm_root_iommu_dev = { |
279 | .name = "msm_iommu", | |
280 | .id = -1, | |
281 | }; | |
282 | ||
12943325 | 283 | static struct msm_iommu_dev jpegd_iommu = { |
d9c8279b SM |
284 | .name = "jpegd", |
285 | .clk_rate = -1 | |
286 | }; | |
287 | ||
12943325 | 288 | static struct msm_iommu_dev vpe_iommu = { |
d9c8279b SM |
289 | .name = "vpe" |
290 | }; | |
291 | ||
12943325 | 292 | static struct msm_iommu_dev mdp0_iommu = { |
d9c8279b SM |
293 | .name = "mdp0" |
294 | }; | |
295 | ||
12943325 | 296 | static struct msm_iommu_dev mdp1_iommu = { |
d9c8279b SM |
297 | .name = "mdp1" |
298 | }; | |
299 | ||
12943325 | 300 | static struct msm_iommu_dev rot_iommu = { |
d9c8279b SM |
301 | .name = "rot" |
302 | }; | |
303 | ||
12943325 | 304 | static struct msm_iommu_dev ijpeg_iommu = { |
d9c8279b SM |
305 | .name = "ijpeg" |
306 | }; | |
307 | ||
12943325 | 308 | static struct msm_iommu_dev vfe_iommu = { |
d9c8279b SM |
309 | .name = "vfe", |
310 | .clk_rate = -1 | |
311 | }; | |
312 | ||
12943325 | 313 | static struct msm_iommu_dev vcodec_a_iommu = { |
d9c8279b SM |
314 | .name = "vcodec_a" |
315 | }; | |
316 | ||
12943325 | 317 | static struct msm_iommu_dev vcodec_b_iommu = { |
d9c8279b SM |
318 | .name = "vcodec_b" |
319 | }; | |
320 | ||
12943325 | 321 | static struct msm_iommu_dev gfx3d_iommu = { |
d9c8279b SM |
322 | .name = "gfx3d", |
323 | .clk_rate = 27000000 | |
324 | }; | |
325 | ||
12943325 | 326 | static struct msm_iommu_dev gfx2d0_iommu = { |
d9c8279b SM |
327 | .name = "gfx2d0", |
328 | .clk_rate = 27000000 | |
329 | }; | |
330 | ||
e8952e3b SM |
331 | static struct msm_iommu_dev gfx2d1_iommu = { |
332 | .name = "gfx2d1", | |
333 | .clk_rate = 27000000 | |
334 | }; | |
335 | ||
12943325 | 336 | static struct platform_device msm_device_iommu_jpegd = { |
d9c8279b SM |
337 | .name = "msm_iommu", |
338 | .id = 0, | |
339 | .dev = { | |
340 | .parent = &msm_root_iommu_dev.dev, | |
341 | }, | |
342 | .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources), | |
343 | .resource = msm_iommu_jpegd_resources, | |
344 | }; | |
345 | ||
12943325 | 346 | static struct platform_device msm_device_iommu_vpe = { |
d9c8279b SM |
347 | .name = "msm_iommu", |
348 | .id = 1, | |
349 | .dev = { | |
350 | .parent = &msm_root_iommu_dev.dev, | |
351 | }, | |
352 | .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources), | |
353 | .resource = msm_iommu_vpe_resources, | |
354 | }; | |
355 | ||
12943325 | 356 | static struct platform_device msm_device_iommu_mdp0 = { |
d9c8279b SM |
357 | .name = "msm_iommu", |
358 | .id = 2, | |
359 | .dev = { | |
360 | .parent = &msm_root_iommu_dev.dev, | |
361 | }, | |
362 | .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources), | |
363 | .resource = msm_iommu_mdp0_resources, | |
364 | }; | |
365 | ||
12943325 | 366 | static struct platform_device msm_device_iommu_mdp1 = { |
d9c8279b SM |
367 | .name = "msm_iommu", |
368 | .id = 3, | |
369 | .dev = { | |
370 | .parent = &msm_root_iommu_dev.dev, | |
371 | }, | |
372 | .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources), | |
373 | .resource = msm_iommu_mdp1_resources, | |
374 | }; | |
375 | ||
12943325 | 376 | static struct platform_device msm_device_iommu_rot = { |
d9c8279b SM |
377 | .name = "msm_iommu", |
378 | .id = 4, | |
379 | .dev = { | |
380 | .parent = &msm_root_iommu_dev.dev, | |
381 | }, | |
382 | .num_resources = ARRAY_SIZE(msm_iommu_rot_resources), | |
383 | .resource = msm_iommu_rot_resources, | |
384 | }; | |
385 | ||
12943325 | 386 | static struct platform_device msm_device_iommu_ijpeg = { |
d9c8279b SM |
387 | .name = "msm_iommu", |
388 | .id = 5, | |
389 | .dev = { | |
390 | .parent = &msm_root_iommu_dev.dev, | |
391 | }, | |
392 | .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources), | |
393 | .resource = msm_iommu_ijpeg_resources, | |
394 | }; | |
395 | ||
12943325 | 396 | static struct platform_device msm_device_iommu_vfe = { |
d9c8279b SM |
397 | .name = "msm_iommu", |
398 | .id = 6, | |
399 | .dev = { | |
400 | .parent = &msm_root_iommu_dev.dev, | |
401 | }, | |
402 | .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources), | |
403 | .resource = msm_iommu_vfe_resources, | |
404 | }; | |
405 | ||
12943325 | 406 | static struct platform_device msm_device_iommu_vcodec_a = { |
d9c8279b SM |
407 | .name = "msm_iommu", |
408 | .id = 7, | |
409 | .dev = { | |
410 | .parent = &msm_root_iommu_dev.dev, | |
411 | }, | |
412 | .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources), | |
413 | .resource = msm_iommu_vcodec_a_resources, | |
414 | }; | |
415 | ||
12943325 | 416 | static struct platform_device msm_device_iommu_vcodec_b = { |
d9c8279b SM |
417 | .name = "msm_iommu", |
418 | .id = 8, | |
419 | .dev = { | |
420 | .parent = &msm_root_iommu_dev.dev, | |
421 | }, | |
422 | .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources), | |
423 | .resource = msm_iommu_vcodec_b_resources, | |
424 | }; | |
425 | ||
12943325 | 426 | static struct platform_device msm_device_iommu_gfx3d = { |
d9c8279b SM |
427 | .name = "msm_iommu", |
428 | .id = 9, | |
429 | .dev = { | |
430 | .parent = &msm_root_iommu_dev.dev, | |
431 | }, | |
432 | .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources), | |
433 | .resource = msm_iommu_gfx3d_resources, | |
434 | }; | |
435 | ||
12943325 | 436 | static struct platform_device msm_device_iommu_gfx2d0 = { |
d9c8279b SM |
437 | .name = "msm_iommu", |
438 | .id = 10, | |
439 | .dev = { | |
440 | .parent = &msm_root_iommu_dev.dev, | |
441 | }, | |
442 | .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources), | |
443 | .resource = msm_iommu_gfx2d0_resources, | |
444 | }; | |
445 | ||
e8952e3b SM |
446 | struct platform_device msm_device_iommu_gfx2d1 = { |
447 | .name = "msm_iommu", | |
448 | .id = 11, | |
449 | .dev = { | |
450 | .parent = &msm_root_iommu_dev.dev, | |
451 | }, | |
452 | .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources), | |
453 | .resource = msm_iommu_gfx2d1_resources, | |
454 | }; | |
455 | ||
d9c8279b SM |
456 | static struct msm_iommu_ctx_dev jpegd_src_ctx = { |
457 | .name = "jpegd_src", | |
458 | .num = 0, | |
459 | .mids = {0, -1} | |
460 | }; | |
461 | ||
462 | static struct msm_iommu_ctx_dev jpegd_dst_ctx = { | |
463 | .name = "jpegd_dst", | |
464 | .num = 1, | |
465 | .mids = {1, -1} | |
466 | }; | |
467 | ||
468 | static struct msm_iommu_ctx_dev vpe_src_ctx = { | |
469 | .name = "vpe_src", | |
470 | .num = 0, | |
471 | .mids = {0, -1} | |
472 | }; | |
473 | ||
474 | static struct msm_iommu_ctx_dev vpe_dst_ctx = { | |
475 | .name = "vpe_dst", | |
476 | .num = 1, | |
477 | .mids = {1, -1} | |
478 | }; | |
479 | ||
480 | static struct msm_iommu_ctx_dev mdp_vg1_ctx = { | |
481 | .name = "mdp_vg1", | |
482 | .num = 0, | |
483 | .mids = {0, 2, -1} | |
484 | }; | |
485 | ||
486 | static struct msm_iommu_ctx_dev mdp_rgb1_ctx = { | |
487 | .name = "mdp_rgb1", | |
488 | .num = 1, | |
489 | .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} | |
490 | }; | |
491 | ||
492 | static struct msm_iommu_ctx_dev mdp_vg2_ctx = { | |
493 | .name = "mdp_vg2", | |
494 | .num = 0, | |
495 | .mids = {0, 2, -1} | |
496 | }; | |
497 | ||
498 | static struct msm_iommu_ctx_dev mdp_rgb2_ctx = { | |
499 | .name = "mdp_rgb2", | |
500 | .num = 1, | |
501 | .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} | |
502 | }; | |
503 | ||
504 | static struct msm_iommu_ctx_dev rot_src_ctx = { | |
505 | .name = "rot_src", | |
506 | .num = 0, | |
507 | .mids = {0, -1} | |
508 | }; | |
509 | ||
510 | static struct msm_iommu_ctx_dev rot_dst_ctx = { | |
511 | .name = "rot_dst", | |
512 | .num = 1, | |
513 | .mids = {1, -1} | |
514 | }; | |
515 | ||
516 | static struct msm_iommu_ctx_dev ijpeg_src_ctx = { | |
517 | .name = "ijpeg_src", | |
518 | .num = 0, | |
519 | .mids = {0, -1} | |
520 | }; | |
521 | ||
522 | static struct msm_iommu_ctx_dev ijpeg_dst_ctx = { | |
523 | .name = "ijpeg_dst", | |
524 | .num = 1, | |
525 | .mids = {1, -1} | |
526 | }; | |
527 | ||
528 | static struct msm_iommu_ctx_dev vfe_imgwr_ctx = { | |
529 | .name = "vfe_imgwr", | |
530 | .num = 0, | |
531 | .mids = {2, 3, 4, 5, 6, 7, 8, -1} | |
532 | }; | |
533 | ||
534 | static struct msm_iommu_ctx_dev vfe_misc_ctx = { | |
535 | .name = "vfe_misc", | |
536 | .num = 1, | |
537 | .mids = {0, 1, 9, -1} | |
538 | }; | |
539 | ||
540 | static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = { | |
541 | .name = "vcodec_a_stream", | |
542 | .num = 0, | |
543 | .mids = {2, 5, -1} | |
544 | }; | |
545 | ||
546 | static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = { | |
547 | .name = "vcodec_a_mm1", | |
548 | .num = 1, | |
549 | .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} | |
550 | }; | |
551 | ||
552 | static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = { | |
553 | .name = "vcodec_b_mm2", | |
554 | .num = 0, | |
555 | .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} | |
556 | }; | |
557 | ||
a5fcd5f5 SM |
558 | static struct msm_iommu_ctx_dev gfx3d_user_ctx = { |
559 | .name = "gfx3d_user", | |
d9c8279b | 560 | .num = 0, |
a5fcd5f5 | 561 | .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} |
d9c8279b SM |
562 | }; |
563 | ||
a5fcd5f5 SM |
564 | static struct msm_iommu_ctx_dev gfx3d_priv_ctx = { |
565 | .name = "gfx3d_priv", | |
d9c8279b | 566 | .num = 1, |
a5fcd5f5 SM |
567 | .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, |
568 | 31, -1} | |
d9c8279b SM |
569 | }; |
570 | ||
ff25ff84 SM |
571 | static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = { |
572 | .name = "gfx2d0_2d0", | |
d9c8279b | 573 | .num = 0, |
ff25ff84 | 574 | .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} |
d9c8279b SM |
575 | }; |
576 | ||
e8952e3b SM |
577 | static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = { |
578 | .name = "gfx2d1_2d1", | |
579 | .num = 0, | |
580 | .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} | |
581 | }; | |
582 | ||
d9c8279b SM |
583 | static struct platform_device msm_device_jpegd_src_ctx = { |
584 | .name = "msm_iommu_ctx", | |
585 | .id = 0, | |
586 | .dev = { | |
12943325 | 587 | .parent = &msm_device_iommu_jpegd.dev, |
d9c8279b SM |
588 | }, |
589 | }; | |
590 | ||
591 | static struct platform_device msm_device_jpegd_dst_ctx = { | |
592 | .name = "msm_iommu_ctx", | |
593 | .id = 1, | |
594 | .dev = { | |
12943325 | 595 | .parent = &msm_device_iommu_jpegd.dev, |
d9c8279b SM |
596 | }, |
597 | }; | |
598 | ||
599 | static struct platform_device msm_device_vpe_src_ctx = { | |
600 | .name = "msm_iommu_ctx", | |
601 | .id = 2, | |
602 | .dev = { | |
12943325 | 603 | .parent = &msm_device_iommu_vpe.dev, |
d9c8279b SM |
604 | }, |
605 | }; | |
606 | ||
607 | static struct platform_device msm_device_vpe_dst_ctx = { | |
608 | .name = "msm_iommu_ctx", | |
609 | .id = 3, | |
610 | .dev = { | |
12943325 | 611 | .parent = &msm_device_iommu_vpe.dev, |
d9c8279b SM |
612 | }, |
613 | }; | |
614 | ||
615 | static struct platform_device msm_device_mdp_vg1_ctx = { | |
616 | .name = "msm_iommu_ctx", | |
617 | .id = 4, | |
618 | .dev = { | |
12943325 | 619 | .parent = &msm_device_iommu_mdp0.dev, |
d9c8279b SM |
620 | }, |
621 | }; | |
622 | ||
623 | static struct platform_device msm_device_mdp_rgb1_ctx = { | |
624 | .name = "msm_iommu_ctx", | |
625 | .id = 5, | |
626 | .dev = { | |
12943325 | 627 | .parent = &msm_device_iommu_mdp0.dev, |
d9c8279b SM |
628 | }, |
629 | }; | |
630 | ||
631 | static struct platform_device msm_device_mdp_vg2_ctx = { | |
632 | .name = "msm_iommu_ctx", | |
633 | .id = 6, | |
634 | .dev = { | |
12943325 | 635 | .parent = &msm_device_iommu_mdp1.dev, |
d9c8279b SM |
636 | }, |
637 | }; | |
638 | ||
639 | static struct platform_device msm_device_mdp_rgb2_ctx = { | |
640 | .name = "msm_iommu_ctx", | |
641 | .id = 7, | |
642 | .dev = { | |
12943325 | 643 | .parent = &msm_device_iommu_mdp1.dev, |
d9c8279b SM |
644 | }, |
645 | }; | |
646 | ||
647 | static struct platform_device msm_device_rot_src_ctx = { | |
648 | .name = "msm_iommu_ctx", | |
649 | .id = 8, | |
650 | .dev = { | |
12943325 | 651 | .parent = &msm_device_iommu_rot.dev, |
d9c8279b SM |
652 | }, |
653 | }; | |
654 | ||
655 | static struct platform_device msm_device_rot_dst_ctx = { | |
656 | .name = "msm_iommu_ctx", | |
657 | .id = 9, | |
658 | .dev = { | |
12943325 | 659 | .parent = &msm_device_iommu_rot.dev, |
d9c8279b SM |
660 | }, |
661 | }; | |
662 | ||
663 | static struct platform_device msm_device_ijpeg_src_ctx = { | |
664 | .name = "msm_iommu_ctx", | |
665 | .id = 10, | |
666 | .dev = { | |
12943325 | 667 | .parent = &msm_device_iommu_ijpeg.dev, |
d9c8279b SM |
668 | }, |
669 | }; | |
670 | ||
671 | static struct platform_device msm_device_ijpeg_dst_ctx = { | |
672 | .name = "msm_iommu_ctx", | |
673 | .id = 11, | |
674 | .dev = { | |
12943325 | 675 | .parent = &msm_device_iommu_ijpeg.dev, |
d9c8279b SM |
676 | }, |
677 | }; | |
678 | ||
679 | static struct platform_device msm_device_vfe_imgwr_ctx = { | |
680 | .name = "msm_iommu_ctx", | |
681 | .id = 12, | |
682 | .dev = { | |
12943325 | 683 | .parent = &msm_device_iommu_vfe.dev, |
d9c8279b SM |
684 | }, |
685 | }; | |
686 | ||
687 | static struct platform_device msm_device_vfe_misc_ctx = { | |
688 | .name = "msm_iommu_ctx", | |
689 | .id = 13, | |
690 | .dev = { | |
12943325 | 691 | .parent = &msm_device_iommu_vfe.dev, |
d9c8279b SM |
692 | }, |
693 | }; | |
694 | ||
695 | static struct platform_device msm_device_vcodec_a_stream_ctx = { | |
696 | .name = "msm_iommu_ctx", | |
697 | .id = 14, | |
698 | .dev = { | |
12943325 | 699 | .parent = &msm_device_iommu_vcodec_a.dev, |
d9c8279b SM |
700 | }, |
701 | }; | |
702 | ||
703 | static struct platform_device msm_device_vcodec_a_mm1_ctx = { | |
704 | .name = "msm_iommu_ctx", | |
705 | .id = 15, | |
706 | .dev = { | |
12943325 | 707 | .parent = &msm_device_iommu_vcodec_a.dev, |
d9c8279b SM |
708 | }, |
709 | }; | |
710 | ||
711 | static struct platform_device msm_device_vcodec_b_mm2_ctx = { | |
712 | .name = "msm_iommu_ctx", | |
713 | .id = 16, | |
714 | .dev = { | |
12943325 | 715 | .parent = &msm_device_iommu_vcodec_b.dev, |
d9c8279b SM |
716 | }, |
717 | }; | |
718 | ||
a5fcd5f5 | 719 | static struct platform_device msm_device_gfx3d_user_ctx = { |
d9c8279b SM |
720 | .name = "msm_iommu_ctx", |
721 | .id = 17, | |
722 | .dev = { | |
12943325 | 723 | .parent = &msm_device_iommu_gfx3d.dev, |
d9c8279b SM |
724 | }, |
725 | }; | |
726 | ||
a5fcd5f5 | 727 | static struct platform_device msm_device_gfx3d_priv_ctx = { |
d9c8279b SM |
728 | .name = "msm_iommu_ctx", |
729 | .id = 18, | |
730 | .dev = { | |
12943325 | 731 | .parent = &msm_device_iommu_gfx3d.dev, |
d9c8279b SM |
732 | }, |
733 | }; | |
734 | ||
ff25ff84 | 735 | static struct platform_device msm_device_gfx2d0_2d0_ctx = { |
d9c8279b | 736 | .name = "msm_iommu_ctx", |
a5fcd5f5 | 737 | .id = 19, |
d9c8279b | 738 | .dev = { |
12943325 | 739 | .parent = &msm_device_iommu_gfx2d0.dev, |
d9c8279b SM |
740 | }, |
741 | }; | |
742 | ||
e8952e3b SM |
743 | static struct platform_device msm_device_gfx2d1_2d1_ctx = { |
744 | .name = "msm_iommu_ctx", | |
745 | .id = 20, | |
746 | .dev = { | |
747 | .parent = &msm_device_iommu_gfx2d1.dev, | |
748 | }, | |
749 | }; | |
750 | ||
d9c8279b | 751 | static struct platform_device *msm_iommu_devs[] = { |
12943325 SM |
752 | &msm_device_iommu_jpegd, |
753 | &msm_device_iommu_vpe, | |
754 | &msm_device_iommu_mdp0, | |
755 | &msm_device_iommu_mdp1, | |
756 | &msm_device_iommu_rot, | |
757 | &msm_device_iommu_ijpeg, | |
758 | &msm_device_iommu_vfe, | |
759 | &msm_device_iommu_vcodec_a, | |
760 | &msm_device_iommu_vcodec_b, | |
761 | &msm_device_iommu_gfx3d, | |
762 | &msm_device_iommu_gfx2d0, | |
e8952e3b | 763 | &msm_device_iommu_gfx2d1, |
d9c8279b SM |
764 | }; |
765 | ||
766 | static struct msm_iommu_dev *msm_iommu_data[] = { | |
12943325 SM |
767 | &jpegd_iommu, |
768 | &vpe_iommu, | |
769 | &mdp0_iommu, | |
770 | &mdp1_iommu, | |
771 | &rot_iommu, | |
772 | &ijpeg_iommu, | |
773 | &vfe_iommu, | |
774 | &vcodec_a_iommu, | |
775 | &vcodec_b_iommu, | |
776 | &gfx3d_iommu, | |
777 | &gfx2d0_iommu, | |
e8952e3b | 778 | &gfx2d1_iommu, |
d9c8279b SM |
779 | }; |
780 | ||
781 | static struct platform_device *msm_iommu_ctx_devs[] = { | |
782 | &msm_device_jpegd_src_ctx, | |
783 | &msm_device_jpegd_dst_ctx, | |
784 | &msm_device_vpe_src_ctx, | |
785 | &msm_device_vpe_dst_ctx, | |
786 | &msm_device_mdp_vg1_ctx, | |
787 | &msm_device_mdp_rgb1_ctx, | |
788 | &msm_device_mdp_vg2_ctx, | |
789 | &msm_device_mdp_rgb2_ctx, | |
790 | &msm_device_rot_src_ctx, | |
791 | &msm_device_rot_dst_ctx, | |
792 | &msm_device_ijpeg_src_ctx, | |
793 | &msm_device_ijpeg_dst_ctx, | |
794 | &msm_device_vfe_imgwr_ctx, | |
795 | &msm_device_vfe_misc_ctx, | |
796 | &msm_device_vcodec_a_stream_ctx, | |
797 | &msm_device_vcodec_a_mm1_ctx, | |
798 | &msm_device_vcodec_b_mm2_ctx, | |
a5fcd5f5 SM |
799 | &msm_device_gfx3d_user_ctx, |
800 | &msm_device_gfx3d_priv_ctx, | |
ff25ff84 | 801 | &msm_device_gfx2d0_2d0_ctx, |
e8952e3b | 802 | &msm_device_gfx2d1_2d1_ctx, |
d9c8279b SM |
803 | }; |
804 | ||
805 | static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { | |
806 | &jpegd_src_ctx, | |
807 | &jpegd_dst_ctx, | |
808 | &vpe_src_ctx, | |
809 | &vpe_dst_ctx, | |
810 | &mdp_vg1_ctx, | |
811 | &mdp_rgb1_ctx, | |
812 | &mdp_vg2_ctx, | |
813 | &mdp_rgb2_ctx, | |
814 | &rot_src_ctx, | |
815 | &rot_dst_ctx, | |
816 | &ijpeg_src_ctx, | |
817 | &ijpeg_dst_ctx, | |
818 | &vfe_imgwr_ctx, | |
819 | &vfe_misc_ctx, | |
820 | &vcodec_a_stream_ctx, | |
821 | &vcodec_a_mm1_ctx, | |
822 | &vcodec_b_mm2_ctx, | |
a5fcd5f5 SM |
823 | &gfx3d_user_ctx, |
824 | &gfx3d_priv_ctx, | |
ff25ff84 | 825 | &gfx2d0_2d0_ctx, |
e8952e3b | 826 | &gfx2d1_2d1_ctx, |
d9c8279b SM |
827 | }; |
828 | ||
516cbc79 | 829 | static int __init msm8x60_iommu_init(void) |
d9c8279b SM |
830 | { |
831 | int ret, i; | |
832 | ||
833 | ret = platform_device_register(&msm_root_iommu_dev); | |
834 | if (ret != 0) { | |
835 | pr_err("Failed to register root IOMMU device!\n"); | |
836 | goto failure; | |
837 | } | |
838 | ||
839 | for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) { | |
840 | ret = platform_device_add_data(msm_iommu_devs[i], | |
841 | msm_iommu_data[i], | |
842 | sizeof(struct msm_iommu_dev)); | |
843 | if (ret != 0) { | |
844 | pr_err("platform_device_add_data failed, " | |
845 | "i = %d\n", i); | |
846 | goto failure_unwind; | |
847 | } | |
848 | ||
849 | ret = platform_device_register(msm_iommu_devs[i]); | |
850 | ||
851 | if (ret != 0) { | |
12943325 | 852 | pr_err("platform_device_register iommu failed, " |
d9c8279b SM |
853 | "i = %d\n", i); |
854 | goto failure_unwind; | |
855 | } | |
856 | } | |
857 | ||
858 | for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) { | |
859 | ret = platform_device_add_data(msm_iommu_ctx_devs[i], | |
860 | msm_iommu_ctx_data[i], | |
861 | sizeof(*msm_iommu_ctx_devs[i])); | |
862 | if (ret != 0) { | |
12943325 | 863 | pr_err("platform_device_add_data iommu failed, " |
d9c8279b SM |
864 | "i = %d\n", i); |
865 | goto failure_unwind2; | |
866 | } | |
867 | ||
868 | ret = platform_device_register(msm_iommu_ctx_devs[i]); | |
869 | if (ret != 0) { | |
870 | pr_err("platform_device_register ctx failed, " | |
871 | "i = %d\n", i); | |
872 | goto failure_unwind2; | |
873 | } | |
874 | } | |
875 | return 0; | |
876 | ||
877 | failure_unwind2: | |
878 | while (--i >= 0) | |
879 | platform_device_unregister(msm_iommu_ctx_devs[i]); | |
880 | failure_unwind: | |
881 | while (--i >= 0) | |
882 | platform_device_unregister(msm_iommu_devs[i]); | |
883 | ||
884 | platform_device_unregister(&msm_root_iommu_dev); | |
885 | failure: | |
886 | return ret; | |
887 | } | |
888 | ||
516cbc79 | 889 | static void __exit msm8x60_iommu_exit(void) |
d9c8279b SM |
890 | { |
891 | int i; | |
892 | ||
893 | for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) | |
894 | platform_device_unregister(msm_iommu_ctx_devs[i]); | |
895 | ||
896 | for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i) | |
897 | platform_device_unregister(msm_iommu_devs[i]); | |
898 | ||
899 | platform_device_unregister(&msm_root_iommu_dev); | |
900 | } | |
901 | ||
902 | subsys_initcall(msm8x60_iommu_init); | |
903 | module_exit(msm8x60_iommu_exit); | |
904 | ||
905 | MODULE_LICENSE("GPL v2"); | |
906 | MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>"); |