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bcc0f6af BS |
1 | /* linux/arch/arm/mach-msm/devices.c |
2 | * | |
3 | * Copyright (C) 2008 Google, Inc. | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/platform_device.h> | |
bd32344a | 18 | #include <linux/clkdev.h> |
bcc0f6af | 19 | |
80b02c17 | 20 | #include <mach/irqs.h> |
bcc0f6af BS |
21 | #include <mach/msm_iomap.h> |
22 | #include "devices.h" | |
23 | ||
24 | #include <asm/mach/flash.h> | |
25 | #include <linux/mtd/nand.h> | |
26 | #include <linux/mtd/partitions.h> | |
27 | ||
5e96da5d | 28 | #include "clock.h" |
ce1c80fb | 29 | #include "clock-pcom.h" |
1ef21f63 | 30 | #include <linux/platform_data/mmc-msm_sdcc.h> |
5d4f77ff | 31 | |
7bce696b SB |
32 | static struct resource msm_gpio_resources[] = { |
33 | { | |
34 | .start = 32 + 0, | |
35 | .end = 32 + 0, | |
36 | .flags = IORESOURCE_IRQ, | |
37 | }, | |
38 | { | |
39 | .start = 32 + 1, | |
40 | .end = 32 + 1, | |
41 | .flags = IORESOURCE_IRQ, | |
42 | }, | |
43 | { | |
44 | .start = 0xa9200800, | |
45 | .end = 0xa9200800 + SZ_4K - 1, | |
46 | .flags = IORESOURCE_MEM, | |
47 | .name = "gpio1" | |
48 | }, | |
49 | { | |
50 | .start = 0xa9300C00, | |
51 | .end = 0xa9300C00 + SZ_4K - 1, | |
52 | .flags = IORESOURCE_MEM, | |
53 | .name = "gpio2" | |
54 | }, | |
55 | }; | |
56 | ||
57 | struct platform_device msm_device_gpio_7201 = { | |
58 | .name = "gpio-msm-7201", | |
59 | .num_resources = ARRAY_SIZE(msm_gpio_resources), | |
60 | .resource = msm_gpio_resources, | |
61 | }; | |
62 | ||
bcc0f6af BS |
63 | static struct resource resources_uart1[] = { |
64 | { | |
65 | .start = INT_UART1, | |
66 | .end = INT_UART1, | |
67 | .flags = IORESOURCE_IRQ, | |
68 | }, | |
69 | { | |
70 | .start = MSM_UART1_PHYS, | |
71 | .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1, | |
72 | .flags = IORESOURCE_MEM, | |
d41cb8c9 | 73 | .name = "uart_resource" |
bcc0f6af BS |
74 | }, |
75 | }; | |
76 | ||
77 | static struct resource resources_uart2[] = { | |
78 | { | |
79 | .start = INT_UART2, | |
80 | .end = INT_UART2, | |
81 | .flags = IORESOURCE_IRQ, | |
82 | }, | |
83 | { | |
84 | .start = MSM_UART2_PHYS, | |
85 | .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, | |
86 | .flags = IORESOURCE_MEM, | |
d41cb8c9 | 87 | .name = "uart_resource" |
bcc0f6af BS |
88 | }, |
89 | }; | |
90 | ||
91 | static struct resource resources_uart3[] = { | |
92 | { | |
93 | .start = INT_UART3, | |
94 | .end = INT_UART3, | |
95 | .flags = IORESOURCE_IRQ, | |
96 | }, | |
97 | { | |
98 | .start = MSM_UART3_PHYS, | |
99 | .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, | |
100 | .flags = IORESOURCE_MEM, | |
d41cb8c9 | 101 | .name = "uart_resource" |
bcc0f6af BS |
102 | }, |
103 | }; | |
104 | ||
105 | struct platform_device msm_device_uart1 = { | |
106 | .name = "msm_serial", | |
107 | .id = 0, | |
108 | .num_resources = ARRAY_SIZE(resources_uart1), | |
109 | .resource = resources_uart1, | |
110 | }; | |
111 | ||
112 | struct platform_device msm_device_uart2 = { | |
113 | .name = "msm_serial", | |
114 | .id = 1, | |
115 | .num_resources = ARRAY_SIZE(resources_uart2), | |
116 | .resource = resources_uart2, | |
117 | }; | |
118 | ||
119 | struct platform_device msm_device_uart3 = { | |
120 | .name = "msm_serial", | |
121 | .id = 2, | |
122 | .num_resources = ARRAY_SIZE(resources_uart3), | |
123 | .resource = resources_uart3, | |
124 | }; | |
125 | ||
126 | static struct resource resources_i2c[] = { | |
127 | { | |
128 | .start = MSM_I2C_PHYS, | |
129 | .end = MSM_I2C_PHYS + MSM_I2C_SIZE - 1, | |
130 | .flags = IORESOURCE_MEM, | |
131 | }, | |
132 | { | |
133 | .start = INT_PWB_I2C, | |
134 | .end = INT_PWB_I2C, | |
135 | .flags = IORESOURCE_IRQ, | |
136 | }, | |
137 | }; | |
138 | ||
139 | struct platform_device msm_device_i2c = { | |
140 | .name = "msm_i2c", | |
141 | .id = 0, | |
142 | .num_resources = ARRAY_SIZE(resources_i2c), | |
143 | .resource = resources_i2c, | |
144 | }; | |
145 | ||
146 | static struct resource resources_hsusb[] = { | |
147 | { | |
148 | .start = MSM_HSUSB_PHYS, | |
149 | .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, | |
150 | .flags = IORESOURCE_MEM, | |
151 | }, | |
152 | { | |
153 | .start = INT_USB_HS, | |
154 | .end = INT_USB_HS, | |
155 | .flags = IORESOURCE_IRQ, | |
156 | }, | |
157 | }; | |
158 | ||
159 | struct platform_device msm_device_hsusb = { | |
160 | .name = "msm_hsusb", | |
161 | .id = -1, | |
162 | .num_resources = ARRAY_SIZE(resources_hsusb), | |
163 | .resource = resources_hsusb, | |
164 | .dev = { | |
165 | .coherent_dma_mask = 0xffffffff, | |
166 | }, | |
167 | }; | |
168 | ||
169 | struct flash_platform_data msm_nand_data = { | |
170 | .parts = NULL, | |
171 | .nr_parts = 0, | |
172 | }; | |
173 | ||
174 | static struct resource resources_nand[] = { | |
175 | [0] = { | |
176 | .start = 7, | |
177 | .end = 7, | |
178 | .flags = IORESOURCE_DMA, | |
179 | }, | |
180 | }; | |
181 | ||
182 | struct platform_device msm_device_nand = { | |
183 | .name = "msm_nand", | |
184 | .id = -1, | |
185 | .num_resources = ARRAY_SIZE(resources_nand), | |
186 | .resource = resources_nand, | |
187 | .dev = { | |
188 | .platform_data = &msm_nand_data, | |
189 | }, | |
190 | }; | |
191 | ||
192 | struct platform_device msm_device_smd = { | |
193 | .name = "msm_smd", | |
194 | .id = -1, | |
195 | }; | |
196 | ||
197 | static struct resource resources_sdc1[] = { | |
198 | { | |
199 | .start = MSM_SDC1_PHYS, | |
200 | .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1, | |
201 | .flags = IORESOURCE_MEM, | |
202 | }, | |
203 | { | |
204 | .start = INT_SDC1_0, | |
830d843b DZ |
205 | .end = INT_SDC1_0, |
206 | .flags = IORESOURCE_IRQ, | |
207 | .name = "cmd_irq", | |
208 | }, | |
830d843b DZ |
209 | { |
210 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | |
211 | .name = "status_irq" | |
bcc0f6af BS |
212 | }, |
213 | { | |
214 | .start = 8, | |
215 | .end = 8, | |
216 | .flags = IORESOURCE_DMA, | |
217 | }, | |
218 | }; | |
219 | ||
220 | static struct resource resources_sdc2[] = { | |
221 | { | |
222 | .start = MSM_SDC2_PHYS, | |
223 | .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1, | |
224 | .flags = IORESOURCE_MEM, | |
225 | }, | |
226 | { | |
227 | .start = INT_SDC2_0, | |
830d843b DZ |
228 | .end = INT_SDC2_0, |
229 | .flags = IORESOURCE_IRQ, | |
230 | .name = "cmd_irq", | |
830d843b DZ |
231 | }, |
232 | { | |
233 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | |
234 | .name = "status_irq" | |
bcc0f6af BS |
235 | }, |
236 | { | |
237 | .start = 8, | |
238 | .end = 8, | |
239 | .flags = IORESOURCE_DMA, | |
240 | }, | |
241 | }; | |
242 | ||
243 | static struct resource resources_sdc3[] = { | |
244 | { | |
245 | .start = MSM_SDC3_PHYS, | |
246 | .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1, | |
247 | .flags = IORESOURCE_MEM, | |
248 | }, | |
249 | { | |
250 | .start = INT_SDC3_0, | |
830d843b DZ |
251 | .end = INT_SDC3_0, |
252 | .flags = IORESOURCE_IRQ, | |
253 | .name = "cmd_irq", | |
830d843b DZ |
254 | }, |
255 | { | |
256 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | |
257 | .name = "status_irq" | |
bcc0f6af BS |
258 | }, |
259 | { | |
260 | .start = 8, | |
261 | .end = 8, | |
262 | .flags = IORESOURCE_DMA, | |
263 | }, | |
264 | }; | |
265 | ||
266 | static struct resource resources_sdc4[] = { | |
267 | { | |
268 | .start = MSM_SDC4_PHYS, | |
269 | .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1, | |
270 | .flags = IORESOURCE_MEM, | |
271 | }, | |
272 | { | |
273 | .start = INT_SDC4_0, | |
830d843b DZ |
274 | .end = INT_SDC4_0, |
275 | .flags = IORESOURCE_IRQ, | |
276 | .name = "cmd_irq", | |
830d843b DZ |
277 | }, |
278 | { | |
279 | .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED, | |
280 | .name = "status_irq" | |
bcc0f6af BS |
281 | }, |
282 | { | |
283 | .start = 8, | |
284 | .end = 8, | |
285 | .flags = IORESOURCE_DMA, | |
286 | }, | |
287 | }; | |
288 | ||
289 | struct platform_device msm_device_sdc1 = { | |
290 | .name = "msm_sdcc", | |
291 | .id = 1, | |
292 | .num_resources = ARRAY_SIZE(resources_sdc1), | |
293 | .resource = resources_sdc1, | |
294 | .dev = { | |
295 | .coherent_dma_mask = 0xffffffff, | |
296 | }, | |
297 | }; | |
298 | ||
299 | struct platform_device msm_device_sdc2 = { | |
300 | .name = "msm_sdcc", | |
301 | .id = 2, | |
302 | .num_resources = ARRAY_SIZE(resources_sdc2), | |
303 | .resource = resources_sdc2, | |
304 | .dev = { | |
305 | .coherent_dma_mask = 0xffffffff, | |
306 | }, | |
307 | }; | |
308 | ||
309 | struct platform_device msm_device_sdc3 = { | |
310 | .name = "msm_sdcc", | |
311 | .id = 3, | |
312 | .num_resources = ARRAY_SIZE(resources_sdc3), | |
313 | .resource = resources_sdc3, | |
314 | .dev = { | |
315 | .coherent_dma_mask = 0xffffffff, | |
316 | }, | |
317 | }; | |
318 | ||
319 | struct platform_device msm_device_sdc4 = { | |
320 | .name = "msm_sdcc", | |
321 | .id = 4, | |
322 | .num_resources = ARRAY_SIZE(resources_sdc4), | |
323 | .resource = resources_sdc4, | |
324 | .dev = { | |
325 | .coherent_dma_mask = 0xffffffff, | |
326 | }, | |
327 | }; | |
5d4f77ff SM |
328 | |
329 | static struct platform_device *msm_sdcc_devices[] __initdata = { | |
330 | &msm_device_sdc1, | |
331 | &msm_device_sdc2, | |
332 | &msm_device_sdc3, | |
333 | &msm_device_sdc4, | |
334 | }; | |
335 | ||
b5d643de ST |
336 | int __init msm_add_sdcc(unsigned int controller, |
337 | struct msm_mmc_platform_data *plat, | |
830d843b | 338 | unsigned int stat_irq, unsigned long stat_irq_flags) |
5d4f77ff SM |
339 | { |
340 | struct platform_device *pdev; | |
830d843b | 341 | struct resource *res; |
5d4f77ff SM |
342 | |
343 | if (controller < 1 || controller > 4) | |
344 | return -EINVAL; | |
345 | ||
346 | pdev = msm_sdcc_devices[controller-1]; | |
347 | pdev->dev.platform_data = plat; | |
830d843b DZ |
348 | |
349 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq"); | |
350 | if (!res) | |
351 | return -EINVAL; | |
352 | else if (stat_irq) { | |
353 | res->start = res->end = stat_irq; | |
354 | res->flags &= ~IORESOURCE_DISABLED; | |
355 | res->flags |= stat_irq_flags; | |
356 | } | |
357 | ||
5d4f77ff SM |
358 | return platform_device_register(pdev); |
359 | } | |
360 | ||
50bc0ef4 DW |
361 | static struct resource resources_mddi0[] = { |
362 | { | |
363 | .start = MSM_PMDH_PHYS, | |
364 | .end = MSM_PMDH_PHYS + MSM_PMDH_SIZE - 1, | |
365 | .flags = IORESOURCE_MEM, | |
366 | }, | |
367 | { | |
368 | .start = INT_MDDI_PRI, | |
369 | .end = INT_MDDI_PRI, | |
370 | .flags = IORESOURCE_IRQ, | |
371 | }, | |
372 | }; | |
373 | ||
374 | static struct resource resources_mddi1[] = { | |
375 | { | |
376 | .start = MSM_EMDH_PHYS, | |
377 | .end = MSM_EMDH_PHYS + MSM_EMDH_SIZE - 1, | |
378 | .flags = IORESOURCE_MEM, | |
379 | }, | |
380 | { | |
381 | .start = INT_MDDI_EXT, | |
382 | .end = INT_MDDI_EXT, | |
383 | .flags = IORESOURCE_IRQ, | |
384 | }, | |
385 | }; | |
386 | ||
387 | struct platform_device msm_device_mddi0 = { | |
388 | .name = "msm_mddi", | |
389 | .id = 0, | |
390 | .num_resources = ARRAY_SIZE(resources_mddi0), | |
391 | .resource = resources_mddi0, | |
392 | .dev = { | |
393 | .coherent_dma_mask = 0xffffffff, | |
394 | }, | |
395 | }; | |
396 | ||
397 | struct platform_device msm_device_mddi1 = { | |
398 | .name = "msm_mddi", | |
399 | .id = 1, | |
400 | .num_resources = ARRAY_SIZE(resources_mddi1), | |
401 | .resource = resources_mddi1, | |
402 | .dev = { | |
403 | .coherent_dma_mask = 0xffffffff, | |
404 | }, | |
405 | }; | |
406 | ||
407 | static struct resource resources_mdp[] = { | |
408 | { | |
409 | .start = MSM_MDP_PHYS, | |
410 | .end = MSM_MDP_PHYS + MSM_MDP_SIZE - 1, | |
411 | .name = "mdp", | |
412 | .flags = IORESOURCE_MEM | |
413 | }, | |
414 | { | |
415 | .start = INT_MDP, | |
416 | .end = INT_MDP, | |
417 | .flags = IORESOURCE_IRQ, | |
418 | }, | |
419 | }; | |
420 | ||
421 | struct platform_device msm_device_mdp = { | |
422 | .name = "msm_mdp", | |
423 | .id = 0, | |
424 | .num_resources = ARRAY_SIZE(resources_mdp), | |
425 | .resource = resources_mdp, | |
426 | }; | |
427 | ||
bd32344a | 428 | struct clk_lookup msm_clocks_7x01a[] = { |
5e96da5d DW |
429 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), |
430 | CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), | |
431 | CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, 0), | |
432 | CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0), | |
433 | CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0), | |
434 | CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF), | |
435 | CLK_PCOM("gp_clk", GP_CLK, NULL, 0), | |
436 | CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, OFF), | |
bd32344a | 437 | CLK_PCOM("i2c_clk", I2C_CLK, "msm_i2c.0", 0), |
5e96da5d DW |
438 | CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), |
439 | CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), | |
440 | CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF), | |
441 | CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0), | |
442 | CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF), | |
443 | CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0), | |
444 | CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), | |
304a09c3 | 445 | CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), |
5e96da5d | 446 | CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), |
bd32344a SB |
447 | CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF), |
448 | CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF), | |
449 | CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF), | |
450 | CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF), | |
451 | CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF), | |
452 | CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF), | |
453 | CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF), | |
454 | CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF), | |
5e96da5d DW |
455 | CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), |
456 | CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), | |
457 | CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), | |
458 | CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), | |
bd32344a SB |
459 | CLK_PCOM("uart_clk", UART1_CLK, "msm_serial.0", OFF), |
460 | CLK_PCOM("uart_clk", UART2_CLK, "msm_serial.1", 0), | |
461 | CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF), | |
5e96da5d DW |
462 | CLK_PCOM("uart1dm_clk", UART1DM_CLK, NULL, OFF), |
463 | CLK_PCOM("uart2dm_clk", UART2DM_CLK, NULL, 0), | |
bd32344a SB |
464 | CLK_PCOM("usb_hs_clk", USB_HS_CLK, "msm_hsusb", OFF), |
465 | CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, "msm_hsusb", OFF), | |
5e96da5d DW |
466 | CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0), |
467 | CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF ), | |
468 | CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF), | |
469 | CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF), | |
470 | }; | |
471 | ||
472 | unsigned msm_num_clocks_7x01a = ARRAY_SIZE(msm_clocks_7x01a); |