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1 | /* Copyright (c) 2009, Code Aurora Forum. All rights reserved. |
2 | * | |
3 | * Redistribution and use in source and binary forms, with or without | |
4 | * modification, are permitted provided that the following conditions are | |
5 | * met: | |
6 | * * Redistributions of source code must retain the above copyright | |
7 | * notice, this list of conditions and the following disclaimer. | |
8 | * * Redistributions in binary form must reproduce the above | |
9 | * copyright notice, this list of conditions and the following | |
10 | * disclaimer in the documentation and/or other materials provided | |
11 | * with the distribution. | |
12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its | |
13 | * contributors may be used to endorse or promote products derived | |
14 | * from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS | |
20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | |
23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | |
24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | |
25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | |
26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
27 | * | |
28 | */ | |
29 | ||
30 | #ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H | |
31 | #define __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H | |
32 | ||
33 | /* clock IDs used by the modem processor */ | |
34 | ||
35 | #define P_ACPU_CLK 0 /* Applications processor clock */ | |
36 | #define P_ADM_CLK 1 /* Applications data mover clock */ | |
37 | #define P_ADSP_CLK 2 /* ADSP clock */ | |
38 | #define P_EBI1_CLK 3 /* External bus interface 1 clock */ | |
39 | #define P_EBI2_CLK 4 /* External bus interface 2 clock */ | |
40 | #define P_ECODEC_CLK 5 /* External CODEC clock */ | |
41 | #define P_EMDH_CLK 6 /* External MDDI host clock */ | |
42 | #define P_GP_CLK 7 /* General purpose clock */ | |
43 | #define P_GRP_3D_CLK 8 /* Graphics clock */ | |
44 | #define P_I2C_CLK 9 /* I2C clock */ | |
45 | #define P_ICODEC_RX_CLK 10 /* Internal CODEX RX clock */ | |
46 | #define P_ICODEC_TX_CLK 11 /* Internal CODEX TX clock */ | |
47 | #define P_IMEM_CLK 12 /* Internal graphics memory clock */ | |
48 | #define P_MDC_CLK 13 /* MDDI client clock */ | |
49 | #define P_MDP_CLK 14 /* Mobile display processor clock */ | |
50 | #define P_PBUS_CLK 15 /* Peripheral bus clock */ | |
51 | #define P_PCM_CLK 16 /* PCM clock */ | |
52 | #define P_PMDH_CLK 17 /* Primary MDDI host clock */ | |
53 | #define P_SDAC_CLK 18 /* Stereo DAC clock */ | |
54 | #define P_SDC1_CLK 19 /* Secure Digital Card clocks */ | |
55 | #define P_SDC1_P_CLK 20 | |
56 | #define P_SDC2_CLK 21 | |
57 | #define P_SDC2_P_CLK 22 | |
58 | #define P_SDC3_CLK 23 | |
59 | #define P_SDC3_P_CLK 24 | |
60 | #define P_SDC4_CLK 25 | |
61 | #define P_SDC4_P_CLK 26 | |
62 | #define P_TSIF_CLK 27 /* Transport Stream Interface clocks */ | |
63 | #define P_TSIF_REF_CLK 28 | |
64 | #define P_TV_DAC_CLK 29 /* TV clocks */ | |
65 | #define P_TV_ENC_CLK 30 | |
66 | #define P_UART1_CLK 31 /* UART clocks */ | |
67 | #define P_UART2_CLK 32 | |
68 | #define P_UART3_CLK 33 | |
69 | #define P_UART1DM_CLK 34 | |
70 | #define P_UART2DM_CLK 35 | |
71 | #define P_USB_HS_CLK 36 /* High speed USB core clock */ | |
72 | #define P_USB_HS_P_CLK 37 /* High speed USB pbus clock */ | |
73 | #define P_USB_OTG_CLK 38 /* Full speed USB clock */ | |
74 | #define P_VDC_CLK 39 /* Video controller clock */ | |
75 | #define P_VFE_MDC_CLK 40 /* Camera / Video Front End clock */ | |
76 | #define P_VFE_CLK 41 /* VFE MDDI client clock */ | |
77 | #define P_MDP_LCDC_PCLK_CLK 42 | |
78 | #define P_MDP_LCDC_PAD_PCLK_CLK 43 | |
79 | #define P_MDP_VSYNC_CLK 44 | |
80 | #define P_SPI_CLK 45 | |
81 | #define P_VFE_AXI_CLK 46 | |
82 | #define P_USB_HS2_CLK 47 /* High speed USB 2 core clock */ | |
83 | #define P_USB_HS2_P_CLK 48 /* High speed USB 2 pbus clock */ | |
84 | #define P_USB_HS3_CLK 49 /* High speed USB 3 core clock */ | |
85 | #define P_USB_HS3_P_CLK 50 /* High speed USB 3 pbus clock */ | |
86 | #define P_GRP_3D_P_CLK 51 /* Graphics pbus clock */ | |
87 | #define P_USB_PHY_CLK 52 /* USB PHY clock */ | |
88 | #define P_USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */ | |
89 | #define P_USB_HS2_CORE_CLK 54 /* High speed USB 2 core clock */ | |
90 | #define P_USB_HS3_CORE_CLK 55 /* High speed USB 3 core clock */ | |
91 | #define P_CAM_M_CLK 56 | |
92 | #define P_CAMIF_PAD_P_CLK 57 | |
93 | #define P_GRP_2D_CLK 58 | |
94 | #define P_GRP_2D_P_CLK 59 | |
95 | #define P_I2S_CLK 60 | |
96 | #define P_JPEG_CLK 61 | |
97 | #define P_JPEG_P_CLK 62 | |
98 | #define P_LPA_CODEC_CLK 63 | |
99 | #define P_LPA_CORE_CLK 64 | |
100 | #define P_LPA_P_CLK 65 | |
101 | #define P_MDC_IO_CLK 66 | |
102 | #define P_MDC_P_CLK 67 | |
103 | #define P_MFC_CLK 68 | |
104 | #define P_MFC_DIV2_CLK 69 | |
105 | #define P_MFC_P_CLK 70 | |
106 | #define P_QUP_I2C_CLK 71 | |
107 | #define P_ROTATOR_IMEM_CLK 72 | |
108 | #define P_ROTATOR_P_CLK 73 | |
109 | #define P_VFE_CAMIF_CLK 74 | |
110 | #define P_VFE_P_CLK 75 | |
111 | #define P_VPE_CLK 76 | |
112 | #define P_I2C_2_CLK 77 | |
113 | #define P_MI2S_CODEC_RX_S_CLK 78 | |
114 | #define P_MI2S_CODEC_RX_M_CLK 79 | |
115 | #define P_MI2S_CODEC_TX_S_CLK 80 | |
116 | #define P_MI2S_CODEC_TX_M_CLK 81 | |
117 | #define P_PMDH_P_CLK 82 | |
118 | #define P_EMDH_P_CLK 83 | |
119 | #define P_SPI_P_CLK 84 | |
120 | #define P_TSIF_P_CLK 85 | |
121 | #define P_MDP_P_CLK 86 | |
122 | #define P_SDAC_M_CLK 87 | |
123 | #define P_MI2S_S_CLK 88 | |
124 | #define P_MI2S_M_CLK 89 | |
125 | #define P_AXI_ROTATOR_CLK 90 | |
126 | #define P_HDMI_CLK 91 | |
127 | #define P_CSI0_CLK 92 | |
128 | #define P_CSI0_VFE_CLK 93 | |
129 | #define P_CSI0_P_CLK 94 | |
130 | #define P_CSI1_CLK 95 | |
131 | #define P_CSI1_VFE_CLK 96 | |
132 | #define P_CSI1_P_CLK 97 | |
133 | #define P_GSBI_CLK 98 | |
134 | #define P_GSBI_P_CLK 99 | |
135 | ||
136 | #define P_NR_CLKS 100 | |
137 | ||
138 | struct clk_ops; | |
139 | extern struct clk_ops clk_ops_pcom; | |
140 | ||
141 | int pc_clk_reset(unsigned id, enum clk_reset_action action); | |
142 | ||
143 | #define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \ | |
144 | .name = clk_name, \ | |
145 | .id = P_##clk_id, \ | |
146 | .remote_id = P_##clk_id, \ | |
147 | .ops = &clk_ops_pcom, \ | |
148 | .flags = clk_flags, \ | |
149 | .dev = clk_dev, \ | |
150 | .dbg_name = #clk_id, \ | |
151 | } | |
152 | ||
153 | #endif |