[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-lh7a40x / arch-lpd7a40x.c

/* arch/arm/mach-lh7a40x/arch-lpd7a40x.c
 *
 *  Copyright (C) 2004 Logic Product Development
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  version 2 as published by the Free Software Foundation.
 *
 */

#include <linux/tty.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>

#include "common.h"

#define CPLD_INT_NETHERNET	(1<<0)
#define CPLD_INTMASK_ETHERNET	(1<<2)
#if defined (CONFIG_MACH_LPD7A400)
# define CPLD_INT_NTOUCH		(1<<1)
# define CPLD_INTMASK_TOUCH	(1<<3)
# define CPLD_INT_PEN		(1<<4)
# define CPLD_INTMASK_PEN	(1<<4)
# define CPLD_INT_PIRQ		(1<<4)
#endif
#define CPLD_INTMASK_CPLD	(1<<7)
#define CPLD_INT_CPLD		(1<<6)

#define CPLD_CONTROL_SWINT		(1<<7) /* Disable all CPLD IRQs */
#define CPLD_CONTROL_OCMSK		(1<<6) /* Mask USB1 connect IRQ */
#define CPLD_CONTROL_PDRV		(1<<5) /* PCC_nDRV high */
#define CPLD_CONTROL_USB1C		(1<<4) /* USB1 connect IRQ active */
#define CPLD_CONTROL_USB1P		(1<<3) /* USB1 power disable */
#define CPLD_CONTROL_AWKP		(1<<2) /* Auto-wakeup disabled  */
#define CPLD_CONTROL_LCD_ENABLE		(1<<1) /* LCD Vee enable */
#define CPLD_CONTROL_WRLAN_NENABLE	(1<<0) /* SMC91x power disable */


static struct resource smc91x_resources[] = {
	[0] = {
		.start	= CPLD00_PHYS,
		.end	= CPLD00_PHYS + CPLD00_SIZE - 1, /* Only needs 16B */
		.flags	= IORESOURCE_MEM,
	},

	[1] = {
		.start	= IRQ_LPD7A40X_ETH_INT,
		.end	= IRQ_LPD7A40X_ETH_INT,
		.flags	= IORESOURCE_IRQ,
	},

};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
};

static struct resource lh7a40x_usbclient_resources[] = {
	[0] = {
		.start	= USB_PHYS,
		.end	= (USB_PHYS + PAGE_SIZE),
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_USB,
		.end	= IRQ_USB,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 lh7a40x_usbclient_dma_mask = 0xffffffffUL;

static struct platform_device lh7a40x_usbclient_device = {
//	.name		= "lh7a40x_udc",
	.name		= "lh7-udc",
	.id		= 0,
	.dev		= {
		.dma_mask = &lh7a40x_usbclient_dma_mask,
		.coherent_dma_mask = 0xffffffffUL,
	},
	.num_resources	= ARRAY_SIZE (lh7a40x_usbclient_resources),
	.resource	= lh7a40x_usbclient_resources,
};

#if defined (CONFIG_ARCH_LH7A404)

static struct resource lh7a404_usbhost_resources [] = {
	[0] = {
		.start	= USBH_PHYS,
		.end	= (USBH_PHYS + 0xFF),
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_USHINTR,
		.end	= IRQ_USHINTR,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 lh7a404_usbhost_dma_mask = 0xffffffffUL;

static struct platform_device lh7a404_usbhost_device = {
	.name		= "lh7a404-ohci",
	.id		= 0,
	.dev		= {
		.dma_mask = &lh7a404_usbhost_dma_mask,
		.coherent_dma_mask = 0xffffffffUL,
	},
	.num_resources	= ARRAY_SIZE (lh7a404_usbhost_resources),
	.resource	= lh7a404_usbhost_resources,
};

#endif

static struct platform_device* lpd7a40x_devs[] __initdata = {
	&smc91x_device,
	&lh7a40x_usbclient_device,
#if defined (CONFIG_ARCH_LH7A404)
	&lh7a404_usbhost_device,
#endif
};

extern void lpd7a400_map_io (void);

static void __init lpd7a40x_init (void)
{
#if defined (CONFIG_MACH_LPD7A400)
	CPLD_CONTROL |= 0
		| CPLD_CONTROL_SWINT /* Disable software interrupt */
		| CPLD_CONTROL_OCMSK; /* Mask USB1 connection IRQ */
	CPLD_CONTROL &= ~(0
			  | CPLD_CONTROL_LCD_ENABLE	/* Disable LCD */
			  | CPLD_CONTROL_WRLAN_NENABLE	/* Enable SMC91x */
		);
#endif

#if defined (CONFIG_MACH_LPD7A404)
	CPLD_CONTROL &= ~(0
			  | CPLD_CONTROL_WRLAN_NENABLE	/* Enable SMC91x */
		);
#endif

	platform_add_devices (lpd7a40x_devs, ARRAY_SIZE (lpd7a40x_devs));
#if defined (CONFIG_FB_ARMCLCD)
        lh7a40x_clcd_init ();
#endif
}

static void lh7a40x_ack_cpld_irq(struct irq_data *d)
{
	/* CPLD doesn't have ack capability, but some devices may */

#if defined (CPLD_INTMASK_TOUCH)
	/* The touch control *must* mask the interrupt because the
	 * interrupt bit is read by the driver to determine if the pen
	 * is still down. */
	if (d->irq == IRQ_TOUCH)
		CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
#endif
}

static void lh7a40x_mask_cpld_irq(struct irq_data *d)
{
	switch (d->irq) {
	case IRQ_LPD7A40X_ETH_INT:
		CPLD_INTERRUPTS |= CPLD_INTMASK_ETHERNET;
		break;
#if defined (IRQ_TOUCH)
	case IRQ_TOUCH:
		CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
		break;
#endif
	}
}

static void lh7a40x_unmask_cpld_irq(struct irq_data *d)
{
	switch (d->irq) {
	case IRQ_LPD7A40X_ETH_INT:
		CPLD_INTERRUPTS &= ~CPLD_INTMASK_ETHERNET;
		break;
#if defined (IRQ_TOUCH)
	case IRQ_TOUCH:
		CPLD_INTERRUPTS &= ~CPLD_INTMASK_TOUCH;
		break;
#endif
	}
}

static struct irq_chip lpd7a40x_cpld_chip = {
	.name		= "CPLD",
	.irq_ack	= lh7a40x_ack_cpld_irq,
	.irq_mask	= lh7a40x_mask_cpld_irq,
	.irq_unmask	= lh7a40x_unmask_cpld_irq,
};

static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
{
	unsigned int mask = CPLD_INTERRUPTS;

	desc->irq_data.chip->irq_ack(&desc->irq_data);

	if ((mask & (1<<0)) == 0)	/* WLAN */
		generic_handle_irq(IRQ_LPD7A40X_ETH_INT);

#if defined (IRQ_TOUCH)
	if ((mask & (1<<1)) == 0)	/* Touch */
		generic_handle_irq(IRQ_TOUCH);
#endif

	/* Level-triggered need this */
	desc->irq_data.chip->irq_unmask(&desc->irq_data);
}


void __init lh7a40x_init_board_irq (void)
{
	int irq;

		/* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs.
		                 PF7 supports the CPLD.
		   Rev B (v3.4): PF0, PF1, and PF2 are available IRQs.
		                 PF3 supports the CPLD.
		   (Some) LPD7A404 prerelease boards report a version
		   number of 0x16, but we force an override since the
		   hardware is of the newer variety.
		*/

	unsigned char cpld_version = CPLD_REVISION;
	int pinCPLD = (cpld_version == 0x28) ? 7 : 3;

#if defined CONFIG_MACH_LPD7A404
	cpld_version = 0x34;	/* Coerce LPD7A404 to RevB */
#endif

		/* First, configure user controlled GPIOF interrupts  */

	GPIO_PFDD	&= ~0x0f; /* PF0-3 are inputs */
	GPIO_INTTYPE1	&= ~0x0f; /* PF0-3 are level triggered */
	GPIO_INTTYPE2	&= ~0x0f; /* PF0-3 are active low */
	barrier ();
	GPIO_GPIOFINTEN |=  0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */

		/* Then, configure CPLD interrupt */

			/* Disable all CPLD interrupts */
#if defined (CONFIG_MACH_LPD7A400)
	CPLD_INTERRUPTS	= CPLD_INTMASK_TOUCH | CPLD_INTMASK_PEN
		| CPLD_INTMASK_ETHERNET;
	/* *** FIXME: don't know why we need 7 and 4. 7 is way wrong
               and 4 is uncefined. */
	// (1<<7)|(1<<4)|(1<<3)|(1<<2);
#endif
#if defined (CONFIG_MACH_LPD7A404)
	CPLD_INTERRUPTS	= CPLD_INTMASK_ETHERNET;
	/* *** FIXME: don't know why we need 6 and 5, neither is defined. */
	// (1<<6)|(1<<5)|(1<<3);
#endif
	GPIO_PFDD	&= ~(1 << pinCPLD); /* Make input */
	GPIO_INTTYPE1	&= ~(1 << pinCPLD); /* Level triggered */
	GPIO_INTTYPE2	&= ~(1 << pinCPLD); /* Active low */
	barrier ();
	GPIO_GPIOFINTEN |=  (1 << pinCPLD); /* Enable */

		/* Cascade CPLD interrupts */

	for (irq = IRQ_BOARD_START;
	     irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
		set_irq_chip (irq, &lpd7a40x_cpld_chip);
		set_irq_handler (irq, handle_level_irq);
		set_irq_flags (irq, IRQF_VALID);
	}

	set_irq_chained_handler ((cpld_version == 0x28)
				 ? IRQ_CPLD_V28
				 : IRQ_CPLD_V34,
				 lpd7a40x_cpld_handler);
}

static struct map_desc lpd7a40x_io_desc[] __initdata = {
	{
		.virtual	= IO_VIRT,
		.pfn		= __phys_to_pfn(IO_PHYS),
		.length		= IO_SIZE,
		.type		= MT_DEVICE
	},
	{	/* Mapping added to work around chip select problems */
		.virtual	= IOBARRIER_VIRT,
		.pfn		= __phys_to_pfn(IOBARRIER_PHYS),
		.length		= IOBARRIER_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CF_VIRT,
		.pfn		= __phys_to_pfn(CF_PHYS),
		.length		= CF_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD02_VIRT,
		.pfn		= __phys_to_pfn(CPLD02_PHYS),
		.length		= CPLD02_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD06_VIRT,
		.pfn		= __phys_to_pfn(CPLD06_PHYS),
		.length		= CPLD06_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD08_VIRT,
		.pfn		= __phys_to_pfn(CPLD08_PHYS),
		.length		= CPLD08_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD08_VIRT,
		.pfn		= __phys_to_pfn(CPLD08_PHYS),
		.length		= CPLD08_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD0A_VIRT,
		.pfn		= __phys_to_pfn(CPLD0A_PHYS),
		.length		= CPLD0A_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD0C_VIRT,
		.pfn		= __phys_to_pfn(CPLD0C_PHYS),
		.length		= CPLD0C_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD0E_VIRT,
		.pfn		= __phys_to_pfn(CPLD0E_PHYS),
		.length		= CPLD0E_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD10_VIRT,
		.pfn		= __phys_to_pfn(CPLD10_PHYS),
		.length		= CPLD10_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD12_VIRT,
		.pfn		= __phys_to_pfn(CPLD12_PHYS),
		.length		= CPLD12_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD14_VIRT,
		.pfn		= __phys_to_pfn(CPLD14_PHYS),
		.length		= CPLD14_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD16_VIRT,
		.pfn		= __phys_to_pfn(CPLD16_PHYS),
		.length		= CPLD16_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD18_VIRT,
		.pfn		= __phys_to_pfn(CPLD18_PHYS),
		.length		= CPLD18_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= CPLD1A_VIRT,
		.pfn		= __phys_to_pfn(CPLD1A_PHYS),
		.length		= CPLD1A_SIZE,
		.type		= MT_DEVICE
	},
};

void __init
lpd7a40x_map_io(void)
{
	iotable_init (lpd7a40x_io_desc, ARRAY_SIZE (lpd7a40x_io_desc));
}

#ifdef CONFIG_MACH_LPD7A400

MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10")
	/* Maintainer: Marc Singer */
	.boot_params	= 0xc0000100,
	.map_io		= lpd7a40x_map_io,
	.init_irq	= lh7a400_init_irq,
	.timer		= &lh7a40x_timer,
	.init_machine	= lpd7a40x_init,
MACHINE_END

#endif

#ifdef CONFIG_MACH_LPD7A404

MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10")
	/* Maintainer: Marc Singer */
	.boot_params	= 0xc0000100,
	.map_io		= lpd7a40x_map_io,
	.init_irq	= lh7a404_init_irq,
	.timer		= &lh7a40x_timer,
	.init_machine	= lpd7a40x_init,
MACHINE_END

#endif
Commit	Line	Data
1da177e4 LT	1	/* arch/arm/mach-lh7a40x/arch-lpd7a40x.c
	2	*
	3	* Copyright (C) 2004 Logic Product Development
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* version 2 as published by the Free Software Foundation.
	8	*
	9	*/
	10
	11	#include <linux/tty.h>
	12	#include <linux/init.h>
d052d1be	13	#include <linux/platform_device.h>
1da177e4	14	#include <linux/interrupt.h>
c75c625d	15	#include <linux/irq.h>
1da177e4	16
a09e64fb	17	#include <mach/hardware.h>
1da177e4 LT	18	#include <asm/setup.h>
	19	#include <asm/mach-types.h>
	20	#include <asm/mach/arch.h>
	21	#include <asm/irq.h>
	22	#include <asm/mach/irq.h>
	23	#include <asm/mach/map.h>
	24
	25	#include "common.h"
	26
638b2666 MS	27	#define CPLD_INT_NETHERNET (1<<0)
	28	#define CPLD_INTMASK_ETHERNET (1<<2)
	29	#if defined (CONFIG_MACH_LPD7A400)
	30	# define CPLD_INT_NTOUCH (1<<1)
	31	# define CPLD_INTMASK_TOUCH (1<<3)
	32	# define CPLD_INT_PEN (1<<4)
	33	# define CPLD_INTMASK_PEN (1<<4)
	34	# define CPLD_INT_PIRQ (1<<4)
	35	#endif
	36	#define CPLD_INTMASK_CPLD (1<<7)
	37	#define CPLD_INT_CPLD (1<<6)
	38
	39	#define CPLD_CONTROL_SWINT (1<<7) /* Disable all CPLD IRQs */
	40	#define CPLD_CONTROL_OCMSK (1<<6) /* Mask USB1 connect IRQ */
	41	#define CPLD_CONTROL_PDRV (1<<5) /* PCC_nDRV high */
	42	#define CPLD_CONTROL_USB1C (1<<4) /* USB1 connect IRQ active */
	43	#define CPLD_CONTROL_USB1P (1<<3) /* USB1 power disable */
	44	#define CPLD_CONTROL_AWKP (1<<2) /* Auto-wakeup disabled */
	45	#define CPLD_CONTROL_LCD_ENABLE (1<<1) /* LCD Vee enable */
	46	#define CPLD_CONTROL_WRLAN_NENABLE (1<<0) /* SMC91x power disable */
	47
	48
1da177e4 LT	49	static struct resource smc91x_resources[] = {
	50	[0] = {
	51	.start = CPLD00_PHYS,
	52	.end = CPLD00_PHYS + CPLD00_SIZE - 1, /* Only needs 16B */
	53	.flags = IORESOURCE_MEM,
	54	},
	55
	56	[1] = {
	57	.start = IRQ_LPD7A40X_ETH_INT,
	58	.end = IRQ_LPD7A40X_ETH_INT,
	59	.flags = IORESOURCE_IRQ,
	60	},
	61
	62	};
	63
	64	static struct platform_device smc91x_device = {
	65	.name = "smc91x",
	66	.id = 0,
	67	.num_resources = ARRAY_SIZE(smc91x_resources),
	68	.resource = smc91x_resources,
	69	};
	70
	71	static struct resource lh7a40x_usbclient_resources[] = {
	72	[0] = {
	73	.start = USB_PHYS,
638b2666	74	.end = (USB_PHYS + PAGE_SIZE),
1da177e4 LT	75	.flags = IORESOURCE_MEM,
	76	},
	77	[1] = {
638b2666 MS	78	.start = IRQ_USB,
638b2666 MS	79	.end = IRQ_USB,
1da177e4 LT	80	.flags = IORESOURCE_IRQ,
	81	},
	82	};
	83
	84	static u64 lh7a40x_usbclient_dma_mask = 0xffffffffUL;
	85
	86	static struct platform_device lh7a40x_usbclient_device = {
638b2666 MS	87	// .name = "lh7a40x_udc",
638b2666 MS	88	.name = "lh7-udc",
1da177e4 LT	89	.id = 0,
	90	.dev = {
	91	.dma_mask = &lh7a40x_usbclient_dma_mask,
	92	.coherent_dma_mask = 0xffffffffUL,
	93	},
	94	.num_resources = ARRAY_SIZE (lh7a40x_usbclient_resources),
	95	.resource = lh7a40x_usbclient_resources,
	96	};
	97
	98	#if defined (CONFIG_ARCH_LH7A404)
	99
	100	static struct resource lh7a404_usbhost_resources [] = {
	101	[0] = {
	102	.start = USBH_PHYS,
	103	.end = (USBH_PHYS + 0xFF),
	104	.flags = IORESOURCE_MEM,
	105	},
	106	[1] = {
	107	.start = IRQ_USHINTR,
	108	.end = IRQ_USHINTR,
	109	.flags = IORESOURCE_IRQ,
	110	},
	111	};
	112
	113	static u64 lh7a404_usbhost_dma_mask = 0xffffffffUL;
	114
	115	static struct platform_device lh7a404_usbhost_device = {
	116	.name = "lh7a404-ohci",
	117	.id = 0,
	118	.dev = {
	119	.dma_mask = &lh7a404_usbhost_dma_mask,
	120	.coherent_dma_mask = 0xffffffffUL,
	121	},
	122	.num_resources = ARRAY_SIZE (lh7a404_usbhost_resources),
	123	.resource = lh7a404_usbhost_resources,
	124	};
	125
	126	#endif
	127
638b2666	128	static struct platform_device* lpd7a40x_devs[] __initdata = {
1da177e4 LT	129	&smc91x_device,
	130	&lh7a40x_usbclient_device,
	131	#if defined (CONFIG_ARCH_LH7A404)
	132	&lh7a404_usbhost_device,
	133	#endif
	134	};
	135
	136	extern void lpd7a400_map_io (void);
	137
	138	static void __init lpd7a40x_init (void)
	139	{
638b2666 MS	140	#if defined (CONFIG_MACH_LPD7A400)
	141	CPLD_CONTROL \|= 0
	142	\| CPLD_CONTROL_SWINT /* Disable software interrupt */
	143	\| CPLD_CONTROL_OCMSK; /* Mask USB1 connection IRQ */
1da177e4	144	CPLD_CONTROL &= ~(0
638b2666 MS	145	\| CPLD_CONTROL_LCD_ENABLE /* Disable LCD */
638b2666 MS	146	\| CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */
1da177e4	147	);
638b2666 MS	148	#endif
	149
	150	#if defined (CONFIG_MACH_LPD7A404)
	151	CPLD_CONTROL &= ~(0
	152	\| CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */
	153	);
	154	#endif
1da177e4 LT	155
1da177e4 LT	156	platform_add_devices (lpd7a40x_devs, ARRAY_SIZE (lpd7a40x_devs));
638b2666 MS	157	#if defined (CONFIG_FB_ARMCLCD)
	158	lh7a40x_clcd_init ();
	159	#endif
1da177e4 LT	160	}
1da177e4 LT	161
3b7cff66	162	static void lh7a40x_ack_cpld_irq(struct irq_data *d)
1da177e4	163	{
638b2666 MS	164	/* CPLD doesn't have ack capability, but some devices may */
	165
	166	#if defined (CPLD_INTMASK_TOUCH)
4b3f686d	167	/* The touch control must mask the interrupt because the
638b2666 MS	168	* interrupt bit is read by the driver to determine if the pen
638b2666 MS	169	* is still down. */
3b7cff66	170	if (d->irq == IRQ_TOUCH)
638b2666 MS	171	CPLD_INTERRUPTS \|= CPLD_INTMASK_TOUCH;
638b2666 MS	172	#endif
1da177e4 LT	173	}
1da177e4 LT	174
3b7cff66	175	static void lh7a40x_mask_cpld_irq(struct irq_data *d)
1da177e4	176	{
3b7cff66	177	switch (d->irq) {
1da177e4	178	case IRQ_LPD7A40X_ETH_INT:
638b2666	179	CPLD_INTERRUPTS \|= CPLD_INTMASK_ETHERNET;
1da177e4	180	break;
638b2666 MS	181	#if defined (IRQ_TOUCH)
	182	case IRQ_TOUCH:
	183	CPLD_INTERRUPTS \|= CPLD_INTMASK_TOUCH;
1da177e4	184	break;
638b2666	185	#endif
1da177e4 LT	186	}
	187	}
	188
3b7cff66	189	static void lh7a40x_unmask_cpld_irq(struct irq_data *d)
1da177e4	190	{
3b7cff66	191	switch (d->irq) {
1da177e4	192	case IRQ_LPD7A40X_ETH_INT:
638b2666	193	CPLD_INTERRUPTS &= ~CPLD_INTMASK_ETHERNET;
1da177e4	194	break;
638b2666 MS	195	#if defined (IRQ_TOUCH)
	196	case IRQ_TOUCH:
	197	CPLD_INTERRUPTS &= ~CPLD_INTMASK_TOUCH;
1da177e4	198	break;
638b2666	199	#endif
1da177e4 LT	200	}
	201	}
	202
38c677cb	203	static struct irq_chip lpd7a40x_cpld_chip = {
3b7cff66 LB	204	.name = "CPLD",
	205	.irq_ack = lh7a40x_ack_cpld_irq,
	206	.irq_mask = lh7a40x_mask_cpld_irq,
	207	.irq_unmask = lh7a40x_unmask_cpld_irq,
1da177e4 LT	208	};
1da177e4 LT	209
10dd5ce2	210	static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
1da177e4 LT	211	{
	212	unsigned int mask = CPLD_INTERRUPTS;
	213
3b7cff66	214	desc->irq_data.chip->irq_ack(&desc->irq_data);
1da177e4	215
638b2666	216	if ((mask & (1<<0)) == 0) /* WLAN */
d8aa0251	217	generic_handle_irq(IRQ_LPD7A40X_ETH_INT);
1da177e4	218
638b2666 MS	219	#if defined (IRQ_TOUCH)
638b2666 MS	220	if ((mask & (1<<1)) == 0) /* Touch */
d8aa0251	221	generic_handle_irq(IRQ_TOUCH);
638b2666	222	#endif
1da177e4	223
3b7cff66 LB	224	/* Level-triggered need this */
3b7cff66 LB	225	desc->irq_data.chip->irq_unmask(&desc->irq_data);
1da177e4 LT	226	}
	227
	228
	229	void __init lh7a40x_init_board_irq (void)
	230	{
	231	int irq;
	232
	233	/* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs.
	234	PF7 supports the CPLD.
	235	Rev B (v3.4): PF0, PF1, and PF2 are available IRQs.
	236	PF3 supports the CPLD.
	237	(Some) LPD7A404 prerelease boards report a version
	238	number of 0x16, but we force an override since the
	239	hardware is of the newer variety.
	240	*/
	241
	242	unsigned char cpld_version = CPLD_REVISION;
	243	int pinCPLD = (cpld_version == 0x28) ? 7 : 3;
	244
	245	#if defined CONFIG_MACH_LPD7A404
	246	cpld_version = 0x34; /* Coerce LPD7A404 to RevB */
	247	#endif
	248
	249	/* First, configure user controlled GPIOF interrupts */
	250
	251	GPIO_PFDD &= ~0x0f; /* PF0-3 are inputs */
	252	GPIO_INTTYPE1 &= ~0x0f; /* PF0-3 are level triggered */
	253	GPIO_INTTYPE2 &= ~0x0f; /* PF0-3 are active low */
	254	barrier ();
	255	GPIO_GPIOFINTEN \|= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */
	256
	257	/* Then, configure CPLD interrupt */
	258
638b2666 MS	259	/* Disable all CPLD interrupts */
	260	#if defined (CONFIG_MACH_LPD7A400)
	261	CPLD_INTERRUPTS = CPLD_INTMASK_TOUCH \| CPLD_INTMASK_PEN
	262	\| CPLD_INTMASK_ETHERNET;
	263	/* *** FIXME: don't know why we need 7 and 4. 7 is way wrong
	264	and 4 is uncefined. */
	265	// (1<<7)\|(1<<4)\|(1<<3)\|(1<<2);
	266	#endif
	267	#if defined (CONFIG_MACH_LPD7A404)
	268	CPLD_INTERRUPTS = CPLD_INTMASK_ETHERNET;
	269	/* *** FIXME: don't know why we need 6 and 5, neither is defined. */
	270	// (1<<6)\|(1<<5)\|(1<<3);
	271	#endif
1da177e4	272	GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */
638b2666	273	GPIO_INTTYPE1 &= ~(1 << pinCPLD); /* Level triggered */
1da177e4 LT	274	GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */
	275	barrier ();
	276	GPIO_GPIOFINTEN \|= (1 << pinCPLD); /* Enable */
	277
	278	/* Cascade CPLD interrupts */
	279
	280	for (irq = IRQ_BOARD_START;
	281	irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
	282	set_irq_chip (irq, &lpd7a40x_cpld_chip);
10dd5ce2	283	set_irq_handler (irq, handle_level_irq);
1da177e4 LT	284	set_irq_flags (irq, IRQF_VALID);
	285	}
	286
	287	set_irq_chained_handler ((cpld_version == 0x28)
	288	? IRQ_CPLD_V28
	289	: IRQ_CPLD_V34,
	290	lpd7a40x_cpld_handler);
	291	}
	292
638b2666	293	static struct map_desc lpd7a40x_io_desc[] __initdata = {
36d28c03	294	{
638b2666	295	.virtual = IO_VIRT,
36d28c03	296	.pfn = __phys_to_pfn(IO_PHYS),
638b2666	297	.length = IO_SIZE,
36d28c03	298	.type = MT_DEVICE
638b2666 MS	299	},
638b2666 MS	300	{ /* Mapping added to work around chip select problems */
36d28c03 DS	301	.virtual = IOBARRIER_VIRT,
	302	.pfn = __phys_to_pfn(IOBARRIER_PHYS),
	303	.length = IOBARRIER_SIZE,
	304	.type = MT_DEVICE
638b2666 MS	305	},
638b2666 MS	306	{
36d28c03 DS	307	.virtual = CF_VIRT,
36d28c03 DS	308	.pfn = __phys_to_pfn(CF_PHYS),
638b2666	309	.length = CF_SIZE,
36d28c03	310	.type = MT_DEVICE
638b2666 MS	311	},
638b2666 MS	312	{
36d28c03 DS	313	.virtual = CPLD02_VIRT,
36d28c03 DS	314	.pfn = __phys_to_pfn(CPLD02_PHYS),
638b2666	315	.length = CPLD02_SIZE,
36d28c03	316	.type = MT_DEVICE
638b2666 MS	317	},
638b2666 MS	318	{
36d28c03 DS	319	.virtual = CPLD06_VIRT,
36d28c03 DS	320	.pfn = __phys_to_pfn(CPLD06_PHYS),
638b2666 MS	321	.length = CPLD06_SIZE,
	322	.type = MT_DEVICE
	323	},
	324	{
	325	.virtual = CPLD08_VIRT,
	326	.pfn = __phys_to_pfn(CPLD08_PHYS),
	327	.length = CPLD08_SIZE,
36d28c03	328	.type = MT_DEVICE
638b2666 MS	329	},
638b2666 MS	330	{
36d28c03 DS	331	.virtual = CPLD08_VIRT,
36d28c03 DS	332	.pfn = __phys_to_pfn(CPLD08_PHYS),
638b2666	333	.length = CPLD08_SIZE,
36d28c03	334	.type = MT_DEVICE
638b2666 MS	335	},
	336	{
	337	.virtual = CPLD0A_VIRT,
	338	.pfn = __phys_to_pfn(CPLD0A_PHYS),
	339	.length = CPLD0A_SIZE,
	340	.type = MT_DEVICE
	341	},
	342	{
36d28c03 DS	343	.virtual = CPLD0C_VIRT,
36d28c03 DS	344	.pfn = __phys_to_pfn(CPLD0C_PHYS),
638b2666	345	.length = CPLD0C_SIZE,
36d28c03	346	.type = MT_DEVICE
638b2666 MS	347	},
638b2666 MS	348	{
36d28c03 DS	349	.virtual = CPLD0E_VIRT,
36d28c03 DS	350	.pfn = __phys_to_pfn(CPLD0E_PHYS),
638b2666	351	.length = CPLD0E_SIZE,
36d28c03	352	.type = MT_DEVICE
638b2666 MS	353	},
638b2666 MS	354	{
36d28c03 DS	355	.virtual = CPLD10_VIRT,
36d28c03 DS	356	.pfn = __phys_to_pfn(CPLD10_PHYS),
638b2666	357	.length = CPLD10_SIZE,
36d28c03	358	.type = MT_DEVICE
638b2666 MS	359	},
638b2666 MS	360	{
36d28c03 DS	361	.virtual = CPLD12_VIRT,
36d28c03 DS	362	.pfn = __phys_to_pfn(CPLD12_PHYS),
638b2666	363	.length = CPLD12_SIZE,
36d28c03	364	.type = MT_DEVICE
638b2666 MS	365	},
638b2666 MS	366	{
36d28c03 DS	367	.virtual = CPLD14_VIRT,
36d28c03 DS	368	.pfn = __phys_to_pfn(CPLD14_PHYS),
638b2666	369	.length = CPLD14_SIZE,
36d28c03	370	.type = MT_DEVICE
638b2666 MS	371	},
638b2666 MS	372	{
36d28c03 DS	373	.virtual = CPLD16_VIRT,
36d28c03 DS	374	.pfn = __phys_to_pfn(CPLD16_PHYS),
638b2666	375	.length = CPLD16_SIZE,
36d28c03	376	.type = MT_DEVICE
638b2666 MS	377	},
638b2666 MS	378	{
36d28c03 DS	379	.virtual = CPLD18_VIRT,
36d28c03 DS	380	.pfn = __phys_to_pfn(CPLD18_PHYS),
638b2666	381	.length = CPLD18_SIZE,
36d28c03	382	.type = MT_DEVICE
638b2666 MS	383	},
638b2666 MS	384	{
36d28c03 DS	385	.virtual = CPLD1A_VIRT,
36d28c03 DS	386	.pfn = __phys_to_pfn(CPLD1A_PHYS),
638b2666	387	.length = CPLD1A_SIZE,
36d28c03 DS	388	.type = MT_DEVICE
36d28c03 DS	389	},
1da177e4 LT	390	};
	391
	392	void __init
638b2666	393	lpd7a40x_map_io(void)
1da177e4	394	{
638b2666	395	iotable_init (lpd7a40x_io_desc, ARRAY_SIZE (lpd7a40x_io_desc));
1da177e4 LT	396	}
	397
	398	#ifdef CONFIG_MACH_LPD7A400
	399
	400	MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10")
e9dea0c6	401	/* Maintainer: Marc Singer */
e9dea0c6	402	.boot_params = 0xc0000100,
638b2666	403	.map_io = lpd7a40x_map_io,
e9dea0c6	404	.init_irq = lh7a400_init_irq,
1da177e4	405	.timer = &lh7a40x_timer,
e9dea0c6	406	.init_machine = lpd7a40x_init,
1da177e4 LT	407	MACHINE_END
	408
	409	#endif
	410
	411	#ifdef CONFIG_MACH_LPD7A404
	412
	413	MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10")
e9dea0c6	414	/* Maintainer: Marc Singer */
e9dea0c6	415	.boot_params = 0xc0000100,
638b2666	416	.map_io = lpd7a40x_map_io,
e9dea0c6	417	.init_irq = lh7a404_init_irq,
1da177e4	418	.timer = &lh7a40x_timer,
e9dea0c6	419	.init_machine = lpd7a40x_init,
1da177e4 LT	420	MACHINE_END
	421
	422	#endif