ARM: 6742/1: pmu: avoid setting IRQ affinity on UP systems
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-lh7a40x / arch-kev7a400.c
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1/* arch/arm/mach-lh7a40x/arch-kev7a400.c
2 *
3 * Copyright (C) 2004 Logic Product Development
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/tty.h>
12#include <linux/init.h>
13#include <linux/device.h>
14#include <linux/interrupt.h>
15
a09e64fb 16#include <mach/hardware.h>
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17#include <asm/setup.h>
18#include <asm/mach-types.h>
19#include <asm/mach/arch.h>
20#include <asm/irq.h>
21#include <asm/mach/irq.h>
22#include <asm/mach/map.h>
23
24#include "common.h"
25
26 /* This function calls the board specific IRQ initialization function. */
27
28static struct map_desc kev7a400_io_desc[] __initdata = {
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29 {
30 .virtual = IO_VIRT,
31 .pfn = __phys_to_pfn(IO_PHYS),
32 .length = IO_SIZE,
33 .type = MT_DEVICE
34 }, {
35 .virtual = CPLD_VIRT,
36 .pfn = __phys_to_pfn(CPLD_PHYS),
37 .length = CPLD_SIZE,
38 .type = MT_DEVICE
39 }
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40};
41
42void __init kev7a400_map_io(void)
43{
44 iotable_init (kev7a400_io_desc, ARRAY_SIZE (kev7a400_io_desc));
45}
46
47static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */
48
3b7cff66 49static void kev7a400_ack_cpld_irq(struct irq_data *d)
1da177e4 50{
3b7cff66 51 CPLD_CL_INT = 1 << (d->irq - IRQ_KEV7A400_CPLD);
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52}
53
3b7cff66 54static void kev7a400_mask_cpld_irq(struct irq_data *d)
1da177e4 55{
3b7cff66 56 CPLD_IRQ_mask &= ~(1 << (d->irq - IRQ_KEV7A400_CPLD));
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57 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
58}
59
3b7cff66 60static void kev7a400_unmask_cpld_irq(struct irq_data *d)
1da177e4 61{
3b7cff66 62 CPLD_IRQ_mask |= 1 << (d->irq - IRQ_KEV7A400_CPLD);
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63 CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask;
64}
65
38c677cb 66static struct irq_chip kev7a400_cpld_chip = {
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67 .name = "CPLD",
68 .irq_ack = kev7a400_ack_cpld_irq,
69 .irq_mask = kev7a400_mask_cpld_irq,
70 .irq_unmask = kev7a400_unmask_cpld_irq,
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71};
72
73
10dd5ce2 74static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
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75{
76 u32 mask = CPLD_LATCHED_INTS;
77 irq = IRQ_KEV7A400_CPLD;
d8d9075c 78 for (; mask; mask >>= 1, ++irq)
1da177e4 79 if (mask & 1)
d8aa0251 80 generic_handle_irq(irq);
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81}
82
83void __init lh7a40x_init_board_irq (void)
84{
85 int irq;
86
87 for (irq = IRQ_KEV7A400_CPLD;
88 irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) {
89 set_irq_chip (irq, &kev7a400_cpld_chip);
10dd5ce2 90 set_irq_handler (irq, handle_edge_irq);
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91 set_irq_flags (irq, IRQF_VALID);
92 }
93 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
94
95 /* Clear all CPLD interrupts */
96 CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */
97
98 GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */
99 barrier();
100
101#if 0
102 GPIO_INTTYPE1
103 = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */
104 GPIO_INTTYPE2 = 0; /* Falling edge & low-level */
105 GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */
106 GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */
107
108 init_FIQ();
109#endif
110}
111
112MACHINE_START (KEV7A400, "Sharp KEV7a400")
e9dea0c6 113 /* Maintainer: Marc Singer */
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114 .boot_params = 0xc0000100,
115 .map_io = kev7a400_map_io,
116 .init_irq = lh7a400_init_irq,
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117 .timer = &lh7a40x_timer,
118MACHINE_END