[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-kirkwood / pcie.c

/*
 * arch/arm/mach-kirkwood/pcie.c
 *
 * PCIe functions for Marvell Kirkwood SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <mach/bridge-regs.h>
#include "common.h"

static void kirkwood_enable_pcie_clk(const char *port)
{
	struct clk *clk;

	clk = clk_get_sys("pcie", port);
	if (IS_ERR(clk)) {
		pr_err("PCIE clock %s missing\n", port);
		return;
	}
	clk_prepare_enable(clk);
	clk_put(clk);
}

/* This function is called very early in the boot when probing the
   hardware to determine what we actually are, and what rate tclk is
   ticking at. Hence calling kirkwood_enable_pcie_clk() is not
   possible since the clk tree has not been created yet. */
void kirkwood_enable_pcie(void)
{
	u32 curr = readl(CLOCK_GATING_CTRL);
	if (!(curr & CGC_PEX0))
		writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
}

void kirkwood_pcie_id(u32 *dev, u32 *rev)
{
	kirkwood_enable_pcie();
	*dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
	*rev = orion_pcie_rev(PCIE_VIRT_BASE);
}

struct pcie_port {
	u8			root_bus_nr;
	void __iomem		*base;
	spinlock_t		conf_lock;
	int			irq;
	struct resource		res;
};

static int pcie_port_map[2];
static int num_pcie_ports;

static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
	/*
	 * Don't go out when trying to access --
	 * 1. nonexisting device on local bus
	 * 2. where there's no device connected (no link)
	 */
	if (bus == pp->root_bus_nr && dev == 0)
		return 1;

	if (!orion_pcie_link_up(pp->base))
		return 0;

	if (bus == pp->root_bus_nr && dev != 1)
		return 0;

	return 1;
}


/*
 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	struct pci_sys_data *sys = bus->sysdata;
	struct pcie_port *pp = sys->private_data;
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	struct pci_sys_data *sys = bus->sysdata;
	struct pcie_port *pp = sys->private_data;
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};

static void __init pcie0_ioresources_init(struct pcie_port *pp)
{
	pp->base = PCIE_VIRT_BASE;
	pp->irq	= IRQ_KIRKWOOD_PCIE;

	/*
	 * IORESOURCE_MEM
	 */
	pp->res.name = "PCIe 0 MEM";
	pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
	pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
	pp->res.flags = IORESOURCE_MEM;
}

static void __init pcie1_ioresources_init(struct pcie_port *pp)
{
	pp->base = PCIE1_VIRT_BASE;
	pp->irq	= IRQ_KIRKWOOD_PCIE1;

	/*
	 * IORESOURCE_MEM
	 */
	pp->res.name = "PCIe 1 MEM";
	pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
	pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
	pp->res.flags = IORESOURCE_MEM;
}

static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
{
	struct pcie_port *pp;
	int index;

	if (nr >= num_pcie_ports)
		return 0;

	index = pcie_port_map[nr];
	pr_info("PCI: bus%d uses PCIe port %d\n", sys->busnr, index);

	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
	if (!pp)
		panic("PCIe: failed to allocate pcie_port data");
	sys->private_data = pp;
	pp->root_bus_nr = sys->busnr;
	spin_lock_init(&pp->conf_lock);

	switch (index) {
	case 0:
		kirkwood_enable_pcie_clk("0");
		pcie0_ioresources_init(pp);
		pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
		break;
	case 1:
		kirkwood_enable_pcie_clk("1");
		pcie1_ioresources_init(pp);
		pci_ioremap_io(SZ_64K * sys->busnr,
			       KIRKWOOD_PCIE1_IO_PHYS_BASE);
		break;
	default:
		panic("PCIe setup: invalid controller %d", index);
	}

	if (request_resource(&iomem_resource, &pp->res))
		panic("Request PCIe%d Memory resource failed\n", index);

	pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);

	orion_pcie_setup(pp->base);

	return 1;
}

/*
 * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
 * is operating as a root complex this needs to be switched to
 * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
 * the device. Decoding setup is handled by the orion code.
 */
static void rc_pci_fixup(struct pci_dev *dev)
{
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		dev->class &= 0xff;
		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
	u8 pin)
{
	struct pci_sys_data *sys = dev->sysdata;
	struct pcie_port *pp = sys->private_data;

	return pp->irq;
}

static struct hw_pci kirkwood_pci __initdata = {
	.setup		= kirkwood_pcie_setup,
	.map_irq	= kirkwood_pcie_map_irq,
	.ops            = &pcie_ops,
};

static void __init add_pcie_port(int index, void __iomem *base)
{
	pcie_port_map[num_pcie_ports++] = index;
	pr_info("Kirkwood PCIe port %d: link %s\n", index,
		orion_pcie_link_up(base) ? "up" : "down");
}

void __init kirkwood_pcie_init(unsigned int portmask)
{
	vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;

	if (portmask & KW_PCIE0)
		add_pcie_port(0, PCIE_VIRT_BASE);

	if (portmask & KW_PCIE1)
		add_pcie_port(1, PCIE1_VIRT_BASE);

	kirkwood_pci.nr_controllers = num_pcie_ports;
	pci_common_init(&kirkwood_pci);
}
Commit	Line	Data
651c74c7 SB	1	/*
	2	* arch/arm/mach-kirkwood/pcie.c
	3	*
	4	* PCIe functions for Marvell Kirkwood SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/pci.h>
5a0e3ad6	13	#include <linux/slab.h>
27e53cfb	14	#include <linux/clk.h>
cc22b4c1	15	#include <video/vga.h>
6e5c11a1	16	#include <asm/irq.h>
651c74c7	17	#include <asm/mach/pci.h>
6f088f1d	18	#include <plat/pcie.h>
e8b2b7ba	19	#include <mach/bridge-regs.h>
651c74c7 SB	20	#include "common.h"
651c74c7 SB	21
27e53cfb AL	22	static void kirkwood_enable_pcie_clk(const char *port)
	23	{
	24	struct clk *clk;
	25
	26	clk = clk_get_sys("pcie", port);
	27	if (IS_ERR(clk)) {
98adf932	28	pr_err("PCIE clock %s missing\n", port);
27e53cfb AL	29	return;
	30	}
	31	clk_prepare_enable(clk);
	32	clk_put(clk);
	33	}
	34
	35	/* This function is called very early in the boot when probing the
	36	hardware to determine what we actually are, and what rate tclk is
	37	ticking at. Hence calling kirkwood_enable_pcie_clk() is not
	38	possible since the clk tree has not been created yet. */
0e0cdd37 EC	39	void kirkwood_enable_pcie(void)
	40	{
	41	u32 curr = readl(CLOCK_GATING_CTRL);
	42	if (!(curr & CGC_PEX0))
	43	writel(curr \| CGC_PEX0, CLOCK_GATING_CTRL);
	44	}
	45
98d9986c	46	void kirkwood_pcie_id(u32 dev, u32 rev)
ffd58bd2	47	{
0e0cdd37	48	kirkwood_enable_pcie();
060f3d19 TP	49	*dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
060f3d19 TP	50	*rev = orion_pcie_rev(PCIE_VIRT_BASE);
ffd58bd2	51	}
651c74c7	52
ffd58bd2 SB	53	struct pcie_port {
	54	u8 root_bus_nr;
	55	void __iomem *base;
	56	spinlock_t conf_lock;
	57	int irq;
2bb08085	58	struct resource res;
ffd58bd2	59	};
651c74c7	60
ffd58bd2 SB	61	static int pcie_port_map[2];
	62	static int num_pcie_ports;
	63
ffd58bd2	64	static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
651c74c7 SB	65	{
	66	/*
	67	* Don't go out when trying to access --
	68	* 1. nonexisting device on local bus
	69	* 2. where there's no device connected (no link)
	70	*/
ffd58bd2	71	if (bus == pp->root_bus_nr && dev == 0)
651c74c7 SB	72	return 1;
651c74c7 SB	73
ffd58bd2	74	if (!orion_pcie_link_up(pp->base))
651c74c7 SB	75	return 0;
651c74c7 SB	76
ffd58bd2	77	if (bus == pp->root_bus_nr && dev != 1)
651c74c7 SB	78	return 0;
	79
	80	return 1;
	81	}
	82
	83
	84	/*
	85	* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
	86	* and then reading the PCIE_CONF_DATA register. Need to make sure these
	87	* transactions are atomic.
	88	*/
651c74c7 SB	89
	90	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	91	int size, u32 *val)
	92	{
43ba990b RK	93	struct pci_sys_data *sys = bus->sysdata;
43ba990b RK	94	struct pcie_port *pp = sys->private_data;
651c74c7 SB	95	unsigned long flags;
	96	int ret;
	97
ffd58bd2	98	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
651c74c7 SB	99	*val = 0xffffffff;
	100	return PCIBIOS_DEVICE_NOT_FOUND;
	101	}
	102
ffd58bd2 SB	103	spin_lock_irqsave(&pp->conf_lock, flags);
	104	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	105	spin_unlock_irqrestore(&pp->conf_lock, flags);
651c74c7 SB	106
	107	return ret;
	108	}
	109
	110	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
	111	int where, int size, u32 val)
	112	{
43ba990b RK	113	struct pci_sys_data *sys = bus->sysdata;
43ba990b RK	114	struct pcie_port *pp = sys->private_data;
651c74c7 SB	115	unsigned long flags;
	116	int ret;
	117
ffd58bd2	118	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
651c74c7 SB	119	return PCIBIOS_DEVICE_NOT_FOUND;
651c74c7 SB	120
ffd58bd2 SB	121	spin_lock_irqsave(&pp->conf_lock, flags);
	122	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	123	spin_unlock_irqrestore(&pp->conf_lock, flags);
651c74c7 SB	124
	125	return ret;
	126	}
	127
	128	static struct pci_ops pcie_ops = {
	129	.read = pcie_rd_conf,
	130	.write = pcie_wr_conf,
	131	};
	132
a87182b3	133	static void __init pcie0_ioresources_init(struct pcie_port *pp)
651c74c7	134	{
060f3d19	135	pp->base = PCIE_VIRT_BASE;
a87182b3	136	pp->irq = IRQ_KIRKWOOD_PCIE;
651c74c7	137
651c74c7	138	/*
ffd58bd2	139	* IORESOURCE_MEM
651c74c7	140	*/
2bb08085 RH	141	pp->res.name = "PCIe 0 MEM";
	142	pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
	143	pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
	144	pp->res.flags = IORESOURCE_MEM;
ffd58bd2 SB	145	}
ffd58bd2 SB	146
a87182b3	147	static void __init pcie1_ioresources_init(struct pcie_port *pp)
ffd58bd2	148	{
060f3d19	149	pp->base = PCIE1_VIRT_BASE;
a87182b3	150	pp->irq = IRQ_KIRKWOOD_PCIE1;
651c74c7	151
651c74c7 SB	152	/*
	153	* IORESOURCE_MEM
	154	*/
2bb08085 RH	155	pp->res.name = "PCIe 1 MEM";
	156	pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
	157	pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
	158	pp->res.flags = IORESOURCE_MEM;
ffd58bd2 SB	159	}
	160
	161	static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
	162	{
ffd58bd2 SB	163	struct pcie_port *pp;
	164	int index;
	165
	166	if (nr >= num_pcie_ports)
	167	return 0;
	168
	169	index = pcie_port_map[nr];
98adf932	170	pr_info("PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
ffd58bd2 SB	171
	172	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
	173	if (!pp)
	174	panic("PCIe: failed to allocate pcie_port data");
	175	sys->private_data = pp;
	176	pp->root_bus_nr = sys->busnr;
	177	spin_lock_init(&pp->conf_lock);
	178
	179	switch (index) {
	180	case 0:
27e53cfb	181	kirkwood_enable_pcie_clk("0");
a87182b3	182	pcie0_ioresources_init(pp);
2bb08085	183	pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
ffd58bd2 SB	184	break;
ffd58bd2 SB	185	case 1:
27e53cfb	186	kirkwood_enable_pcie_clk("1");
a87182b3	187	pcie1_ioresources_init(pp);
98adf932 AL	188	pci_ioremap_io(SZ_64K * sys->busnr,
98adf932 AL	189	KIRKWOOD_PCIE1_IO_PHYS_BASE);
ffd58bd2 SB	190	break;
ffd58bd2 SB	191	default:
a87182b3	192	panic("PCIe setup: invalid controller %d", index);
ffd58bd2 SB	193	}
ffd58bd2 SB	194
2bb08085	195	if (request_resource(&iomem_resource, &pp->res))
a87182b3 NP	196	panic("Request PCIe%d Memory resource failed\n", index);
a87182b3 NP	197
2bb08085	198	pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
a87182b3	199
ffd58bd2 SB	200	/*
	201	* Generic PCIe unit setup.
	202	*/
	203	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
	204
63a9332b	205	orion_pcie_setup(pp->base);
e8b2b7ba	206
651c74c7 SB	207	return 1;
	208	}
	209
1dc831bf JG	210	/*
	211	* The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
	212	* is operating as a root complex this needs to be switched to
	213	* PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
	214	* the device. Decoding setup is handled by the orion code.
	215	*/
351a102d	216	static void rc_pci_fixup(struct pci_dev *dev)
651c74c7	217	{
651c74c7 SB	218	if (dev->bus->parent == NULL && dev->devfn == 0) {
	219	int i;
	220
1dc831bf JG	221	dev->class &= 0xff;
1dc831bf JG	222	dev->class \|= PCI_CLASS_BRIDGE_HOST << 8;
651c74c7 SB	223	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	224	dev->resource[i].start = 0;
	225	dev->resource[i].end = 0;
	226	dev->resource[i].flags = 0;
	227	}
	228	}
	229	}
	230	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
	231
d5341942 RB	232	static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
d5341942 RB	233	u8 pin)
651c74c7	234	{
43ba990b RK	235	struct pci_sys_data *sys = dev->sysdata;
43ba990b RK	236	struct pcie_port *pp = sys->private_data;
ffd58bd2 SB	237
ffd58bd2 SB	238	return pp->irq;
651c74c7 SB	239	}
	240
	241	static struct hw_pci kirkwood_pci __initdata = {
651c74c7	242	.setup = kirkwood_pcie_setup,
651c74c7	243	.map_irq = kirkwood_pcie_map_irq,
4a9329a0	244	.ops = &pcie_ops,
651c74c7 SB	245	};
651c74c7 SB	246
060f3d19	247	static void __init add_pcie_port(int index, void __iomem *base)
ffd58bd2	248	{
b73690c8 JG	249	pcie_port_map[num_pcie_ports++] = index;
	250	pr_info("Kirkwood PCIe port %d: link %s\n", index,
	251	orion_pcie_link_up(base) ? "up" : "down");
ffd58bd2 SB	252	}
	253
	254	void __init kirkwood_pcie_init(unsigned int portmask)
651c74c7	255	{
cc22b4c1 RH	256	vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
cc22b4c1 RH	257
ffd58bd2 SB	258	if (portmask & KW_PCIE0)
	259	add_pcie_port(0, PCIE_VIRT_BASE);
	260
	261	if (portmask & KW_PCIE1)
	262	add_pcie_port(1, PCIE1_VIRT_BASE);
	263
	264	kirkwood_pci.nr_controllers = num_pcie_ports;
651c74c7 SB	265	pci_common_init(&kirkwood_pci);
651c74c7 SB	266	}