[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-ixp4xx / ixp4xx_qmgr.c

/*
 * Intel IXP4xx Queue Manager driver for Linux
 *
 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 */

#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <mach/qmgr.h>

struct qmgr_regs __iomem *qmgr_regs;
static struct resource *mem_res;
static spinlock_t qmgr_lock;
static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
static void (*irq_handlers[HALF_QUEUES])(void *pdev);
static void *irq_pdevs[HALF_QUEUES];

#if DEBUG_QMGR
char qmgr_queue_descs[QUEUES][32];
#endif

void qmgr_set_irq(unsigned int queue, int src,
		  void (*handler)(void *pdev), void *pdev)
{
	u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */
	int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
	unsigned long flags;

	src &= 7;
	spin_lock_irqsave(&qmgr_lock, flags);
	__raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg);
	irq_handlers[queue] = handler;
	irq_pdevs[queue] = pdev;
	spin_unlock_irqrestore(&qmgr_lock, flags);
}


static irqreturn_t qmgr_irq1(int irq, void *pdev)
{
	int i;
	u32 val = __raw_readl(&qmgr_regs->irqstat[0]);
	__raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */

	for (i = 0; i < HALF_QUEUES; i++)
		if (val & (1 << i))
			irq_handlers[i](irq_pdevs[i]);

	return val ? IRQ_HANDLED : 0;
}


void qmgr_enable_irq(unsigned int queue)
{
	unsigned long flags;

	spin_lock_irqsave(&qmgr_lock, flags);
	__raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue),
		     &qmgr_regs->irqen[0]);
	spin_unlock_irqrestore(&qmgr_lock, flags);
}

void qmgr_disable_irq(unsigned int queue)
{
	unsigned long flags;

	spin_lock_irqsave(&qmgr_lock, flags);
	__raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
		     &qmgr_regs->irqen[0]);
	__raw_writel(1 << queue, &qmgr_regs->irqstat[0]); /* clear */
	spin_unlock_irqrestore(&qmgr_lock, flags);
}

static inline void shift_mask(u32 *mask)
{
	mask[3] = mask[3] << 1 | mask[2] >> 31;
	mask[2] = mask[2] << 1 | mask[1] >> 31;
	mask[1] = mask[1] << 1 | mask[0] >> 31;
	mask[0] <<= 1;
}

#if DEBUG_QMGR
int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
		       unsigned int nearly_empty_watermark,
		       unsigned int nearly_full_watermark,
		       const char *desc_format, const char* name)
#else
int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
			 unsigned int nearly_empty_watermark,
			 unsigned int nearly_full_watermark)
#endif
{
	u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
	int err;

	if (queue >= HALF_QUEUES)
		return -ERANGE;

	if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
		return -EINVAL;

	switch (len) {
	case  16:
		cfg = 0 << 24;
		mask[0] = 0x1;
		break;
	case  32:
		cfg = 1 << 24;
		mask[0] = 0x3;
		break;
	case  64:
		cfg = 2 << 24;
		mask[0] = 0xF;
		break;
	case 128:
		cfg = 3 << 24;
		mask[0] = 0xFF;
		break;
	default:
		return -EINVAL;
	}

	cfg |= nearly_empty_watermark << 26;
	cfg |= nearly_full_watermark << 29;
	len /= 16;		/* in 16-dwords: 1, 2, 4 or 8 */
	mask[1] = mask[2] = mask[3] = 0;

	if (!try_module_get(THIS_MODULE))
		return -ENODEV;

	spin_lock_irq(&qmgr_lock);
	if (__raw_readl(&qmgr_regs->sram[queue])) {
		err = -EBUSY;
		goto err;
	}

	while (1) {
		if (!(used_sram_bitmap[0] & mask[0]) &&
		    !(used_sram_bitmap[1] & mask[1]) &&
		    !(used_sram_bitmap[2] & mask[2]) &&
		    !(used_sram_bitmap[3] & mask[3]))
			break; /* found free space */

		addr++;
		shift_mask(mask);
		if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
			printk(KERN_ERR "qmgr: no free SRAM space for"
			       " queue %i\n", queue);
			err = -ENOMEM;
			goto err;
		}
	}

	used_sram_bitmap[0] |= mask[0];
	used_sram_bitmap[1] |= mask[1];
	used_sram_bitmap[2] |= mask[2];
	used_sram_bitmap[3] |= mask[3];
	__raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
#if DEBUG_QMGR
	snprintf(qmgr_queue_descs[queue], sizeof(qmgr_queue_descs[0]),
		 desc_format, name);
	printk(KERN_DEBUG "qmgr: requested queue %s(%i) addr = 0x%02X\n",
	       qmgr_queue_descs[queue], queue, addr);
#endif
	spin_unlock_irq(&qmgr_lock);
	return 0;

err:
	spin_unlock_irq(&qmgr_lock);
	module_put(THIS_MODULE);
	return err;
}

void qmgr_release_queue(unsigned int queue)
{
	u32 cfg, addr, mask[4];

	BUG_ON(queue >= HALF_QUEUES); /* not in valid range */

	spin_lock_irq(&qmgr_lock);
	cfg = __raw_readl(&qmgr_regs->sram[queue]);
	addr = (cfg >> 14) & 0xFF;

	BUG_ON(!addr);		/* not requested */

	switch ((cfg >> 24) & 3) {
	case 0: mask[0] = 0x1; break;
	case 1: mask[0] = 0x3; break;
	case 2: mask[0] = 0xF; break;
	case 3: mask[0] = 0xFF; break;
	}

	mask[1] = mask[2] = mask[3] = 0;

	while (addr--)
		shift_mask(mask);

#if DEBUG_QMGR
	printk(KERN_DEBUG "qmgr: releasing queue %s(%i)\n",
	       qmgr_queue_descs[queue], queue);
	qmgr_queue_descs[queue][0] = '\x0';
#endif
	__raw_writel(0, &qmgr_regs->sram[queue]);

	used_sram_bitmap[0] &= ~mask[0];
	used_sram_bitmap[1] &= ~mask[1];
	used_sram_bitmap[2] &= ~mask[2];
	used_sram_bitmap[3] &= ~mask[3];
	irq_handlers[queue] = NULL; /* catch IRQ bugs */
	spin_unlock_irq(&qmgr_lock);

	module_put(THIS_MODULE);

	while ((addr = qmgr_get_entry(queue)))
		printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n",
		       queue, addr);
}

static int qmgr_init(void)
{
	int i, err;
	mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
				     IXP4XX_QMGR_REGION_SIZE,
				     "IXP4xx Queue Manager");
	if (mem_res == NULL)
		return -EBUSY;

	qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
	if (qmgr_regs == NULL) {
		err = -ENOMEM;
		goto error_map;
	}

	/* reset qmgr registers */
	for (i = 0; i < 4; i++) {
		__raw_writel(0x33333333, &qmgr_regs->stat1[i]);
		__raw_writel(0, &qmgr_regs->irqsrc[i]);
	}
	for (i = 0; i < 2; i++) {
		__raw_writel(0, &qmgr_regs->stat2[i]);
		__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
		__raw_writel(0, &qmgr_regs->irqen[i]);
	}

	for (i = 0; i < QUEUES; i++)
		__raw_writel(0, &qmgr_regs->sram[i]);

	err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0,
			  "IXP4xx Queue Manager", NULL);
	if (err) {
		printk(KERN_ERR "qmgr: failed to request IRQ%i\n",
		       IRQ_IXP4XX_QM1);
		goto error_irq;
	}

	used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
	spin_lock_init(&qmgr_lock);

	printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
	return 0;

error_irq:
	iounmap(qmgr_regs);
error_map:
	release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
	return err;
}

static void qmgr_remove(void)
{
	free_irq(IRQ_IXP4XX_QM1, NULL);
	synchronize_irq(IRQ_IXP4XX_QM1);
	iounmap(qmgr_regs);
	release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
}

module_init(qmgr_init);
module_exit(qmgr_remove);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Krzysztof Halasa");

EXPORT_SYMBOL(qmgr_regs);
EXPORT_SYMBOL(qmgr_set_irq);
EXPORT_SYMBOL(qmgr_enable_irq);
EXPORT_SYMBOL(qmgr_disable_irq);
#if DEBUG_QMGR
EXPORT_SYMBOL(qmgr_queue_descs);
EXPORT_SYMBOL(qmgr_request_queue);
#else
EXPORT_SYMBOL(__qmgr_request_queue);
#endif
EXPORT_SYMBOL(qmgr_release_queue);
Commit	Line	Data
82a96f57 KH	1	/*
	2	* Intel IXP4xx Queue Manager driver for Linux
	3	*
	4	* Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of version 2 of the GNU General Public License
	8	* as published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/ioport.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
a09e64fb	15	#include <mach/qmgr.h>
82a96f57	16
82a96f57 KH	17	struct qmgr_regs __iomem *qmgr_regs;
	18	static struct resource *mem_res;
	19	static spinlock_t qmgr_lock;
	20	static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
	21	static void (irq_handlers[HALF_QUEUES])(void pdev);
	22	static void *irq_pdevs[HALF_QUEUES];
	23
e6da96ac KH	24	#if DEBUG_QMGR
	25	char qmgr_queue_descs[QUEUES][32];
	26	#endif
	27
82a96f57 KH	28	void qmgr_set_irq(unsigned int queue, int src,
	29	void (handler)(void pdev), void *pdev)
	30	{
	31	u32 __iomem reg = &qmgr_regs->irqsrc[queue / 8]; / 8 queues / u32 */
	32	int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
	33	unsigned long flags;
	34
	35	src &= 7;
	36	spin_lock_irqsave(&qmgr_lock, flags);
	37	__raw_writel((__raw_readl(reg) & ~(7 << bit)) \| (src << bit), reg);
	38	irq_handlers[queue] = handler;
	39	irq_pdevs[queue] = pdev;
	40	spin_unlock_irqrestore(&qmgr_lock, flags);
	41	}
	42
	43
	44	static irqreturn_t qmgr_irq1(int irq, void *pdev)
	45	{
	46	int i;
	47	u32 val = __raw_readl(&qmgr_regs->irqstat[0]);
	48	__raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */
	49
	50	for (i = 0; i < HALF_QUEUES; i++)
	51	if (val & (1 << i))
	52	irq_handlers[i](irq_pdevs[i]);
	53
	54	return val ? IRQ_HANDLED : 0;
	55	}
	56
	57
	58	void qmgr_enable_irq(unsigned int queue)
	59	{
	60	unsigned long flags;
	61
	62	spin_lock_irqsave(&qmgr_lock, flags);
	63	__raw_writel(__raw_readl(&qmgr_regs->irqen[0]) \| (1 << queue),
	64	&qmgr_regs->irqen[0]);
	65	spin_unlock_irqrestore(&qmgr_lock, flags);
	66	}
	67
	68	void qmgr_disable_irq(unsigned int queue)
	69	{
	70	unsigned long flags;
	71
	72	spin_lock_irqsave(&qmgr_lock, flags);
	73	__raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
	74	&qmgr_regs->irqen[0]);
ae2754a9	75	__raw_writel(1 << queue, &qmgr_regs->irqstat[0]); /* clear */
82a96f57 KH	76	spin_unlock_irqrestore(&qmgr_lock, flags);
	77	}
	78
	79	static inline void shift_mask(u32 *mask)
	80	{
	81	mask[3] = mask[3] << 1 \| mask[2] >> 31;
	82	mask[2] = mask[2] << 1 \| mask[1] >> 31;
	83	mask[1] = mask[1] << 1 \| mask[0] >> 31;
	84	mask[0] <<= 1;
	85	}
	86
e6da96ac	87	#if DEBUG_QMGR
82a96f57 KH	88	int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
82a96f57 KH	89	unsigned int nearly_empty_watermark,
e6da96ac KH	90	unsigned int nearly_full_watermark,
	91	const char desc_format, const char name)
	92	#else
	93	int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
	94	unsigned int nearly_empty_watermark,
	95	unsigned int nearly_full_watermark)
	96	#endif
82a96f57 KH	97	{
	98	u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
	99	int err;
	100
	101	if (queue >= HALF_QUEUES)
	102	return -ERANGE;
	103
	104	if ((nearly_empty_watermark \| nearly_full_watermark) & ~7)
	105	return -EINVAL;
	106
	107	switch (len) {
	108	case 16:
	109	cfg = 0 << 24;
	110	mask[0] = 0x1;
	111	break;
	112	case 32:
	113	cfg = 1 << 24;
	114	mask[0] = 0x3;
	115	break;
	116	case 64:
	117	cfg = 2 << 24;
	118	mask[0] = 0xF;
	119	break;
	120	case 128:
	121	cfg = 3 << 24;
	122	mask[0] = 0xFF;
	123	break;
	124	default:
	125	return -EINVAL;
	126	}
	127
	128	cfg \|= nearly_empty_watermark << 26;
	129	cfg \|= nearly_full_watermark << 29;
	130	len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
	131	mask[1] = mask[2] = mask[3] = 0;
	132
	133	if (!try_module_get(THIS_MODULE))
	134	return -ENODEV;
	135
	136	spin_lock_irq(&qmgr_lock);
	137	if (__raw_readl(&qmgr_regs->sram[queue])) {
	138	err = -EBUSY;
	139	goto err;
	140	}
	141
	142	while (1) {
	143	if (!(used_sram_bitmap[0] & mask[0]) &&
	144	!(used_sram_bitmap[1] & mask[1]) &&
	145	!(used_sram_bitmap[2] & mask[2]) &&
	146	!(used_sram_bitmap[3] & mask[3]))
	147	break; /* found free space */
	148
	149	addr++;
	150	shift_mask(mask);
	151	if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
	152	printk(KERN_ERR "qmgr: no free SRAM space for"
	153	" queue %i\n", queue);
	154	err = -ENOMEM;
	155	goto err;
	156	}
	157	}
	158
	159	used_sram_bitmap[0] \|= mask[0];
	160	used_sram_bitmap[1] \|= mask[1];
161	used_sram_bitmap[2] \|= mask[2];
162	used_sram_bitmap[3] \|= mask[3];
163	__raw_writel(cfg \| (addr << 14), &qmgr_regs->sram[queue]);
e6da96ac KH	164	#if DEBUG_QMGR
	165	snprintf(qmgr_queue_descs[queue], sizeof(qmgr_queue_descs[0]),
	166	desc_format, name);
	167	printk(KERN_DEBUG "qmgr: requested queue %s(%i) addr = 0x%02X\n",
	168	qmgr_queue_descs[queue], queue, addr);
82a96f57	169	#endif
e6da96ac	170	spin_unlock_irq(&qmgr_lock);
82a96f57 KH	171	return 0;
	172
	173	err:
	174	spin_unlock_irq(&qmgr_lock);
	175	module_put(THIS_MODULE);
	176	return err;
	177	}
	178
	179	void qmgr_release_queue(unsigned int queue)
	180	{
	181	u32 cfg, addr, mask[4];
	182
	183	BUG_ON(queue >= HALF_QUEUES); /* not in valid range */
	184
	185	spin_lock_irq(&qmgr_lock);
	186	cfg = __raw_readl(&qmgr_regs->sram[queue]);
	187	addr = (cfg >> 14) & 0xFF;
	188
	189	BUG_ON(!addr); /* not requested */
	190
	191	switch ((cfg >> 24) & 3) {
	192	case 0: mask[0] = 0x1; break;
	193	case 1: mask[0] = 0x3; break;
	194	case 2: mask[0] = 0xF; break;
	195	case 3: mask[0] = 0xFF; break;
	196	}
	197
dac2f83f KH	198	mask[1] = mask[2] = mask[3] = 0;
dac2f83f KH	199
82a96f57 KH	200	while (addr--)
	201	shift_mask(mask);
	202
e6da96ac KH	203	#if DEBUG_QMGR
	204	printk(KERN_DEBUG "qmgr: releasing queue %s(%i)\n",
	205	qmgr_queue_descs[queue], queue);
	206	qmgr_queue_descs[queue][0] = '\x0';
	207	#endif
82a96f57 KH	208	__raw_writel(0, &qmgr_regs->sram[queue]);
	209
	210	used_sram_bitmap[0] &= ~mask[0];
	211	used_sram_bitmap[1] &= ~mask[1];
	212	used_sram_bitmap[2] &= ~mask[2];
	213	used_sram_bitmap[3] &= ~mask[3];
	214	irq_handlers[queue] = NULL; /* catch IRQ bugs */
	215	spin_unlock_irq(&qmgr_lock);
	216
	217	module_put(THIS_MODULE);
3edcfb29 KH	218
3edcfb29 KH	219	while ((addr = qmgr_get_entry(queue)))
e6da96ac	220	printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n",
3edcfb29	221	queue, addr);
82a96f57 KH	222	}
	223
	224	static int qmgr_init(void)
	225	{
	226	int i, err;
	227	mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
	228	IXP4XX_QMGR_REGION_SIZE,
	229	"IXP4xx Queue Manager");
	230	if (mem_res == NULL)
	231	return -EBUSY;
	232
	233	qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
	234	if (qmgr_regs == NULL) {
	235	err = -ENOMEM;
	236	goto error_map;
	237	}
	238
	239	/* reset qmgr registers */
	240	for (i = 0; i < 4; i++) {
	241	__raw_writel(0x33333333, &qmgr_regs->stat1[i]);
	242	__raw_writel(0, &qmgr_regs->irqsrc[i]);
	243	}
	244	for (i = 0; i < 2; i++) {
	245	__raw_writel(0, &qmgr_regs->stat2[i]);
	246	__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
	247	__raw_writel(0, &qmgr_regs->irqen[i]);
	248	}
	249
	250	for (i = 0; i < QUEUES; i++)
	251	__raw_writel(0, &qmgr_regs->sram[i]);
	252
	253	err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0,
	254	"IXP4xx Queue Manager", NULL);
	255	if (err) {
	256	printk(KERN_ERR "qmgr: failed to request IRQ%i\n",
	257	IRQ_IXP4XX_QM1);
	258	goto error_irq;
	259	}
	260
	261	used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
	262	spin_lock_init(&qmgr_lock);
	263
	264	printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
	265	return 0;
	266
	267	error_irq:
	268	iounmap(qmgr_regs);
	269	error_map:
	270	release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
	271	return err;
	272	}
	273
	274	static void qmgr_remove(void)
	275	{
	276	free_irq(IRQ_IXP4XX_QM1, NULL);
	277	synchronize_irq(IRQ_IXP4XX_QM1);
	278	iounmap(qmgr_regs);
	279	release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
	280	}
	281
	282	module_init(qmgr_init);
	283	module_exit(qmgr_remove);
	284
	285	MODULE_LICENSE("GPL v2");
286	MODULE_AUTHOR("Krzysztof Halasa");
287
288	EXPORT_SYMBOL(qmgr_regs);
289	EXPORT_SYMBOL(qmgr_set_irq);
290	EXPORT_SYMBOL(qmgr_enable_irq);
291	EXPORT_SYMBOL(qmgr_disable_irq);
e6da96ac KH	292	#if DEBUG_QMGR
e6da96ac KH	293	EXPORT_SYMBOL(qmgr_queue_descs);
82a96f57	294	EXPORT_SYMBOL(qmgr_request_queue);
e6da96ac KH	295	#else
	296	EXPORT_SYMBOL(__qmgr_request_queue);
	297	#endif
82a96f57	298	EXPORT_SYMBOL(qmgr_release_queue);