projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| c680b77e LB |
1 | /* |
| 2 | * arch/arm/mach-iop33x/iq80331.c | |
| 3 | * | |
| 4 | * Board support code for the Intel IQ80331 platform. | |
| 5 | * | |
| 6 | * Author: Dave Jiang <dave.jiang@intel.com> | |
| 7 | * Copyright (C) 2003 Intel Corp. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify it | |
| 10 | * under the terms of the GNU General Public License as published by the | |
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 12 | * option) any later version. | |
| 13 | */ | |
| 14 | ||
| 15 | #include <linux/mm.h> | |
| 16 | #include <linux/init.h> | |
| 17 | #include <linux/kernel.h> | |
| 18 | #include <linux/pci.h> | |
| 19 | #include <linux/string.h> | |
| c680b77e LB |
20 | #include <linux/serial_core.h> |
| 21 | #include <linux/serial_8250.h> | |
| 22 | #include <linux/mtd/physmap.h> | |
| 23 | #include <linux/platform_device.h> | |
| fced80c7 | 24 | #include <linux/io.h> |
| a09e64fb | 25 | #include <mach/hardware.h> |
| c680b77e LB |
26 | #include <asm/irq.h> |
| 27 | #include <asm/mach/arch.h> | |
| 28 | #include <asm/mach/map.h> | |
| 29 | #include <asm/mach/pci.h> | |
| 30 | #include <asm/mach/time.h> | |
| 31 | #include <asm/mach-types.h> | |
| 32 | #include <asm/page.h> | |
| 33 | #include <asm/pgtable.h> | |
| a09e64fb | 34 | #include <mach/time.h> |
| c680b77e LB |
35 | |
| 36 | /* | |
| 37 | * IQ80331 timer tick configuration. | |
| 38 | */ | |
| 39 | static void __init iq80331_timer_init(void) | |
| 40 | { | |
| 41 | /* D-Step parts run at a higher internal bus frequency */ | |
| 42 | if (*IOP3XX_ATURID >= 0xa) | |
| 3668b45d | 43 | iop_init_time(333000000); |
| c680b77e | 44 | else |
| 3668b45d | 45 | iop_init_time(266000000); |
| c680b77e LB |
46 | } |
| 47 | ||
| c680b77e LB |
48 | |
| 49 | /* | |
| 50 | * IQ80331 PCI. | |
| 51 | */ | |
| d73d8011 | 52 | static int __init |
| d5341942 | 53 | iq80331_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
| c680b77e LB |
54 | { |
| 55 | int irq; | |
| 56 | ||
| 57 | if (slot == 1 && pin == 1) { | |
| 58 | /* PCI-X Slot INTA */ | |
| c852ac80 | 59 | irq = IRQ_IOP33X_XINT1; |
| c680b77e LB |
60 | } else if (slot == 1 && pin == 2) { |
| 61 | /* PCI-X Slot INTB */ | |
| c852ac80 | 62 | irq = IRQ_IOP33X_XINT2; |
| c680b77e LB |
63 | } else if (slot == 1 && pin == 3) { |
| 64 | /* PCI-X Slot INTC */ | |
| c852ac80 | 65 | irq = IRQ_IOP33X_XINT3; |
| c680b77e LB |
66 | } else if (slot == 1 && pin == 4) { |
| 67 | /* PCI-X Slot INTD */ | |
| c852ac80 | 68 | irq = IRQ_IOP33X_XINT0; |
| c680b77e LB |
69 | } else if (slot == 2) { |
| 70 | /* GigE */ | |
| c852ac80 | 71 | irq = IRQ_IOP33X_XINT2; |
| c680b77e LB |
72 | } else { |
| 73 | printk(KERN_ERR "iq80331_pci_map_irq() called for unknown " | |
| 74 | "device PCI:%d:%d:%d\n", dev->bus->number, | |
| 75 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); | |
| 76 | irq = -1; | |
| 77 | } | |
| 78 | ||
| 79 | return irq; | |
| 80 | } | |
| 81 | ||
| 82 | static struct hw_pci iq80331_pci __initdata = { | |
| c680b77e | 83 | .nr_controllers = 1, |
| c23bfc38 | 84 | .ops = &iop3xx_ops, |
| c680b77e | 85 | .setup = iop3xx_pci_setup, |
| c34002c1 | 86 | .preinit = iop3xx_pci_preinit_cond, |
| c680b77e LB |
87 | .map_irq = iq80331_pci_map_irq, |
| 88 | }; | |
| 89 | ||
| 90 | static int __init iq80331_pci_init(void) | |
| 91 | { | |
| e90ddd81 DW |
92 | if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) && |
| 93 | machine_is_iq80331()) | |
| c680b77e LB |
94 | pci_common_init(&iq80331_pci); |
| 95 | ||
| 96 | return 0; | |
| 97 | } | |
| 98 | ||
| 99 | subsys_initcall(iq80331_pci_init); | |
| 100 | ||
| 101 | ||
| 102 | /* | |
| 103 | * IQ80331 machine initialisation. | |
| 104 | */ | |
| 105 | static struct physmap_flash_data iq80331_flash_data = { | |
| 106 | .width = 1, | |
| 107 | }; | |
| 108 | ||
| 109 | static struct resource iq80331_flash_resource = { | |
| 110 | .start = 0xc0000000, | |
| 111 | .end = 0xc07fffff, | |
| 112 | .flags = IORESOURCE_MEM, | |
| 113 | }; | |
| 114 | ||
| 115 | static struct platform_device iq80331_flash_device = { | |
| 116 | .name = "physmap-flash", | |
| 117 | .id = 0, | |
| 118 | .dev = { | |
| 119 | .platform_data = &iq80331_flash_data, | |
| 120 | }, | |
| 121 | .num_resources = 1, | |
| 122 | .resource = &iq80331_flash_resource, | |
| 123 | }; | |
| 124 | ||
| 125 | static void __init iq80331_init_machine(void) | |
| 126 | { | |
| 127 | platform_device_register(&iop3xx_i2c0_device); | |
| 128 | platform_device_register(&iop3xx_i2c1_device); | |
| 129 | platform_device_register(&iop33x_uart0_device); | |
| 130 | platform_device_register(&iop33x_uart1_device); | |
| 131 | platform_device_register(&iq80331_flash_device); | |
| 2492c845 DW |
132 | platform_device_register(&iop3xx_dma_0_channel); |
| 133 | platform_device_register(&iop3xx_dma_1_channel); | |
| 134 | platform_device_register(&iop3xx_aau_channel); | |
| c680b77e LB |
135 | } |
| 136 | ||
| 137 | MACHINE_START(IQ80331, "Intel IQ80331") | |
| 138 | /* Maintainer: Intel Corp. */ | |
| e5c76c00 | 139 | .atag_offset = 0x100, |
| c680b77e | 140 | .map_io = iop3xx_map_io, |
| c852ac80 | 141 | .init_irq = iop33x_init_irq, |
| 6bb27d73 | 142 | .init_time = iq80331_timer_init, |
| c680b77e | 143 | .init_machine = iq80331_init_machine, |
| bec92b1e | 144 | .restart = iop3xx_restart, |
| c680b77e | 145 | MACHINE_END |